[mirror_ubuntu-artful-kernel.git] / arch / arm / include / asm / v7m.h

/*
 * Common defines for v7m cpus
 */
#define V7M_SCS_ICTR			IOMEM(0xe000e004)
#define V7M_SCS_ICTR_INTLINESNUM_MASK		0x0000000f

#define BASEADDR_V7M_SCB		IOMEM(0xe000ed00)

#define V7M_SCB_CPUID			0x00

#define V7M_SCB_ICSR			0x04
#define V7M_SCB_ICSR_PENDSVSET			(1 << 28)
#define V7M_SCB_ICSR_PENDSVCLR			(1 << 27)
#define V7M_SCB_ICSR_RETTOBASE			(1 << 11)

#define V7M_SCB_VTOR			0x08

#define V7M_SCB_AIRCR			0x0c
#define V7M_SCB_AIRCR_VECTKEY			(0x05fa << 16)
#define V7M_SCB_AIRCR_SYSRESETREQ		(1 << 2)

#define V7M_SCB_SCR			0x10
#define V7M_SCB_SCR_SLEEPDEEP			(1 << 2)

#define V7M_SCB_CCR			0x14
#define V7M_SCB_CCR_STKALIGN			(1 << 9)

#define V7M_SCB_SHPR2			0x1c
#define V7M_SCB_SHPR3			0x20

#define V7M_SCB_SHCSR			0x24
#define V7M_SCB_SHCSR_USGFAULTENA		(1 << 18)
#define V7M_SCB_SHCSR_BUSFAULTENA		(1 << 17)
#define V7M_SCB_SHCSR_MEMFAULTENA		(1 << 16)

#define V7M_xPSR_FRAMEPTRALIGN			0x00000200
#define V7M_xPSR_EXCEPTIONNO			0x000001ff

/*
 * When branching to an address that has bits [31:28] == 0xf an exception return
 * occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP
 * extension Bit [4] defines if the exception frame has space allocated for FP
 * state information, SBOP otherwise. Bit [3] defines the mode that is returned
 * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
 * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
 */
#define EXC_RET_STACK_MASK			0x00000004
#define EXC_RET_THREADMODE_PROCESSSTACK		0xfffffffd

#ifndef __ASSEMBLY__

enum reboot_mode;

void armv7m_restart(enum reboot_mode mode, const char *cmd);

#endif /* __ASSEMBLY__ */
Commit	Line	Data
55bdd694 CM	1	/*
	2	* Common defines for v7m cpus
	3	*/
	4	#define V7M_SCS_ICTR IOMEM(0xe000e004)
	5	#define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
	6
	7	#define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
	8
	9	#define V7M_SCB_CPUID 0x00
	10
	11	#define V7M_SCB_ICSR 0x04
	12	#define V7M_SCB_ICSR_PENDSVSET (1 << 28)
	13	#define V7M_SCB_ICSR_PENDSVCLR (1 << 27)
	14	#define V7M_SCB_ICSR_RETTOBASE (1 << 11)
	15
	16	#define V7M_SCB_VTOR 0x08
	17
6a7d2c62 UKK	18	#define V7M_SCB_AIRCR 0x0c
	19	#define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
	20	#define V7M_SCB_AIRCR_SYSRESETREQ (1 << 2)
	21
55bdd694 CM	22	#define V7M_SCB_SCR 0x10
	23	#define V7M_SCB_SCR_SLEEPDEEP (1 << 2)
	24
	25	#define V7M_SCB_CCR 0x14
	26	#define V7M_SCB_CCR_STKALIGN (1 << 9)
	27
	28	#define V7M_SCB_SHPR2 0x1c
	29	#define V7M_SCB_SHPR3 0x20
	30
	31	#define V7M_SCB_SHCSR 0x24
	32	#define V7M_SCB_SHCSR_USGFAULTENA (1 << 18)
	33	#define V7M_SCB_SHCSR_BUSFAULTENA (1 << 17)
	34	#define V7M_SCB_SHCSR_MEMFAULTENA (1 << 16)
	35
	36	#define V7M_xPSR_FRAMEPTRALIGN 0x00000200
	37	#define V7M_xPSR_EXCEPTIONNO 0x000001ff
	38
	39	/*
	40	* When branching to an address that has bits [31:28] == 0xf an exception return
	41	* occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP
	42	* extension Bit [4] defines if the exception frame has space allocated for FP
	43	* state information, SBOP otherwise. Bit [3] defines the mode that is returned
	44	* to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
	45	* (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
	46	*/
	47	#define EXC_RET_STACK_MASK 0x00000004
	48	#define EXC_RET_THREADMODE_PROCESSSTACK 0xfffffffd
6a7d2c62 UKK	49
	50	#ifndef __ASSEMBLY__
	51
	52	enum reboot_mode;
	53
	54	void armv7m_restart(enum reboot_mode mode, const char *cmd);
	55
	56	#endif /* __ASSEMBLY__ */