[mirror_ubuntu-zesty-kernel.git] / arch / arm / include / debug / at91.S

/*
 *  Copyright (C) 2003-2005 SAN People
 *
 * Debugging macro include header
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
*/

#define AT91_DBGU_SR		(0x14)	/* Status Register */
#define AT91_DBGU_THR		(0x1c)	/* Transmitter Holding Register */
#define AT91_DBGU_TXRDY		(1 << 1)	/* Transmitter Ready */
#define AT91_DBGU_TXEMPTY	(1 << 9)	/* Transmitter Empty */

	.macro	addruart, rp, rv, tmp
	ldr	\rp, =CONFIG_DEBUG_UART_PHYS		@ System peripherals (phys address)
	ldr	\rv, =CONFIG_DEBUG_UART_VIRT		@ System peripherals (virt address)
	.endm

	.macro	senduart,rd,rx
	strb	\rd, [\rx, #(AT91_DBGU_THR)]		@ Write to Transmitter Holding Register
	.endm

	.macro	waituart,rd,rx
1001:	ldr	\rd, [\rx, #(AT91_DBGU_SR)]		@ Read Status Register
	tst	\rd, #AT91_DBGU_TXRDY			@ DBGU_TXRDY = 1 when ready to transmit
	beq	1001b
	.endm

	.macro	busyuart,rd,rx
1001:	ldr	\rd, [\rx, #(AT91_DBGU_SR)]		@ Read Status Register
	tst	\rd, #AT91_DBGU_TXEMPTY			@ DBGU_TXEMPTY = 1 when transmission complete
	beq	1001b
	.endm
Commit	Line	Data
73a59c1c	1	/*
73a59c1c SP	2	* Copyright (C) 2003-2005 SAN People
	3	*
	4	* Debugging macro include header
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	*/
	11
5f58c970 AB	12	#define AT91_DBGU_SR (0x14) /* Status Register */
	13	#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
	14	#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
	15	#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
	16
639da5ee	17	.macro addruart, rp, rv, tmp
6f112a08	18	ldr \rp, =CONFIG_DEBUG_UART_PHYS @ System peripherals (phys address)
0b37e9e8	19	ldr \rv, =CONFIG_DEBUG_UART_VIRT @ System peripherals (virt address)
73a59c1c SP	20	.endm
	21
	22	.macro senduart,rd,rx
1ff5b1b4	23	strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register
73a59c1c SP	24	.endm
	25
	26	.macro waituart,rd,rx
1ff5b1b4 JCPV	27	1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
1ff5b1b4 JCPV	28	tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
73a59c1c SP	29	beq 1001b
	30	.endm
	31
	32	.macro busyuart,rd,rx
1ff5b1b4 JCPV	33	1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
1ff5b1b4 JCPV	34	tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
73a59c1c SP	35	beq 1001b
	36	.endm
	37