[mirror_ubuntu-bionic-kernel.git] / arch / arm / kernel / bios32.c

/*
 *  linux/arch/arm/kernel/bios32.c
 *
 *  PCI bios-type initialisation for PCI machines
 *
 *  Bits taken from various places.
 */
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/io.h>

#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/mach/pci.h>

static int debug_pci;

/*
 * We can't use pci_find_device() here since we are
 * called from interrupt context.
 */
static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		u16 status;

		/*
		 * ignore host bridge - we handle
		 * that separately
		 */
		if (dev->bus->number == 0 && dev->devfn == 0)
			continue;

		pci_read_config_word(dev, PCI_STATUS, &status);
		if (status == 0xffff)
			continue;

		if ((status & status_mask) == 0)
			continue;

		/* clear the status errors */
		pci_write_config_word(dev, PCI_STATUS, status & status_mask);

		if (warn)
			printk("(%s: %04X) ", pci_name(dev), status);
	}

	list_for_each_entry(dev, &bus->devices, bus_list)
		if (dev->subordinate)
			pcibios_bus_report_status(dev->subordinate, status_mask, warn);
}

void pcibios_report_status(u_int status_mask, int warn)
{
	struct list_head *l;

	list_for_each(l, &pci_root_buses) {
		struct pci_bus *bus = pci_bus_b(l);

		pcibios_bus_report_status(bus, status_mask, warn);
	}
}

/*
 * We don't use this to fix the device, but initialisation of it.
 * It's not the correct use for this, but it works.
 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
 * the following area:
 * 1. park on CPU
 * 2. ISA bridge ping-pong
 * 3. ISA bridge master handling of target RETRY
 *
 * Bug 3 is responsible for the sound DMA grinding to a halt.  We now
 * live with bug 2.
 */
static void pci_fixup_83c553(struct pci_dev *dev)
{
	/*
	 * Set memory region to start at address 0, and enable IO
	 */
	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
	pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);

	dev->resource[0].end -= dev->resource[0].start;
	dev->resource[0].start = 0;

	/*
	 * All memory requests from ISA to be channelled to PCI
	 */
	pci_write_config_byte(dev, 0x48, 0xff);

	/*
	 * Enable ping-pong on bus master to ISA bridge transactions.
	 * This improves the sound DMA substantially.  The fixed
	 * priority arbiter also helps (see below).
	 */
	pci_write_config_byte(dev, 0x42, 0x01);

	/*
	 * Enable PCI retry
	 */
	pci_write_config_byte(dev, 0x40, 0x22);

	/*
	 * We used to set the arbiter to "park on last master" (bit
	 * 1 set), but unfortunately the CyberPro does not park the
	 * bus.  We must therefore park on CPU.  Unfortunately, this
	 * may trigger yet another bug in the 553.
	 */
	pci_write_config_byte(dev, 0x83, 0x02);

	/*
	 * Make the ISA DMA request lowest priority, and disable
	 * rotating priorities completely.
	 */
	pci_write_config_byte(dev, 0x80, 0x11);
	pci_write_config_byte(dev, 0x81, 0x00);

	/*
	 * Route INTA input to IRQ 11, and set IRQ11 to be level
	 * sensitive.
	 */
	pci_write_config_word(dev, 0x44, 0xb000);
	outb(0x08, 0x4d1);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);

static void pci_fixup_unassign(struct pci_dev *dev)
{
	dev->resource[0].end -= dev->resource[0].start;
	dev->resource[0].start = 0;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);

/*
 * Prevent the PCI layer from seeing the resources allocated to this device
 * if it is the host bridge by marking it as such.  These resources are of
 * no consequence to the PCI layer (they are handled elsewhere).
 */
static void pci_fixup_dec21285(struct pci_dev *dev)
{
	int i;

	if (dev->devfn == 0) {
		dev->class &= 0xff;
		dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);

/*
 * PCI IDE controllers use non-standard I/O port decoding, respect it.
 */
static void pci_fixup_ide_bases(struct pci_dev *dev)
{
	struct resource *r;
	int i;

	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
		return;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		r = dev->resource + i;
		if ((r->start & ~0x80) == 0x374) {
			r->start |= 2;
			r->end = r->start;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);

/*
 * Put the DEC21142 to sleep
 */
static void pci_fixup_dec21142(struct pci_dev *dev)
{
	pci_write_config_dword(dev, 0x40, 0x80000000);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);

/*
 * The CY82C693 needs some rather major fixups to ensure that it does
 * the right thing.  Idea from the Alpha people, with a few additions.
 *
 * We ensure that the IDE base registers are set to 1f0/3f4 for the
 * primary bus, and 170/374 for the secondary bus.  Also, hide them
 * from the PCI subsystem view as well so we won't try to perform
 * our own auto-configuration on them.
 *
 * In addition, we ensure that the PCI IDE interrupts are routed to
 * IRQ 14 and IRQ 15 respectively.
 *
 * The above gets us to a point where the IDE on this device is
 * functional.  However, The CY82C693U _does not work_ in bus
 * master mode without locking the PCI bus solid.
 */
static void pci_fixup_cy82c693(struct pci_dev *dev)
{
	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
		u32 base0, base1;

		if (dev->class & 0x80) {	/* primary */
			base0 = 0x1f0;
			base1 = 0x3f4;
		} else {			/* secondary */
			base0 = 0x170;
			base1 = 0x374;
		}

		pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
				       base0 | PCI_BASE_ADDRESS_SPACE_IO);
		pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
				       base1 | PCI_BASE_ADDRESS_SPACE_IO);

		dev->resource[0].start = 0;
		dev->resource[0].end   = 0;
		dev->resource[0].flags = 0;

		dev->resource[1].start = 0;
		dev->resource[1].end   = 0;
		dev->resource[1].flags = 0;
	} else if (PCI_FUNC(dev->devfn) == 0) {
		/*
		 * Setup IDE IRQ routing.
		 */
		pci_write_config_byte(dev, 0x4b, 14);
		pci_write_config_byte(dev, 0x4c, 15);

		/*
		 * Disable FREQACK handshake, enable USB.
		 */
		pci_write_config_byte(dev, 0x4d, 0x41);

		/*
		 * Enable PCI retry, and PCI post-write buffer.
		 */
		pci_write_config_byte(dev, 0x44, 0x17);

		/*
		 * Enable ISA master and DMA post write buffering.
		 */
		pci_write_config_byte(dev, 0x45, 0x03);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);

static void pci_fixup_it8152(struct pci_dev *dev)
{
	int i;
	/* fixup for ITE 8152 devices */
	/* FIXME: add defines for class 0x68000 and 0x80103 */
	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
	    dev->class == 0x68000 ||
	    dev->class == 0x80103) {
		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);

/*
 * If the bus contains any of these devices, then we must not turn on
 * parity checking of any kind.  Currently this is CyberPro 20x0 only.
 */
static inline int pdev_bad_for_parity(struct pci_dev *dev)
{
	return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
		 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
		  dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
		(dev->vendor == PCI_VENDOR_ID_ITE &&
		 dev->device == PCI_DEVICE_ID_ITE_8152));

}

/*
 * pcibios_fixup_bus - Called after each bus is probed,
 * but before its children are examined.
 */
void pcibios_fixup_bus(struct pci_bus *bus)
{
	struct pci_dev *dev;
	u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;

	/*
	 * Walk the devices on this bus, working out what we can
	 * and can't support.
	 */
	list_for_each_entry(dev, &bus->devices, bus_list) {
		u16 status;

		pci_read_config_word(dev, PCI_STATUS, &status);

		/*
		 * If any device on this bus does not support fast back
		 * to back transfers, then the bus as a whole is not able
		 * to support them.  Having fast back to back transfers
		 * on saves us one PCI cycle per transaction.
		 */
		if (!(status & PCI_STATUS_FAST_BACK))
			features &= ~PCI_COMMAND_FAST_BACK;

		if (pdev_bad_for_parity(dev))
			features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);

		switch (dev->class >> 8) {
		case PCI_CLASS_BRIDGE_PCI:
			pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
			status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
			status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
			pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
			break;

		case PCI_CLASS_BRIDGE_CARDBUS:
			pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
			status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
			pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
			break;
		}
	}

	/*
	 * Now walk the devices again, this time setting them up.
	 */
	list_for_each_entry(dev, &bus->devices, bus_list) {
		u16 cmd;

		pci_read_config_word(dev, PCI_COMMAND, &cmd);
		cmd |= features;
		pci_write_config_word(dev, PCI_COMMAND, cmd);

		pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
				      L1_CACHE_BYTES >> 2);
	}

	/*
	 * Propagate the flags to the PCI bridge.
	 */
	if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
		if (features & PCI_COMMAND_FAST_BACK)
			bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
		if (features & PCI_COMMAND_PARITY)
			bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
	}

	/*
	 * Report what we did for this bus
	 */
	printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
		bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
}
EXPORT_SYMBOL(pcibios_fixup_bus);

/*
 * Swizzle the device pin each time we cross a bridge.  If a platform does
 * not provide a swizzle function, we perform the standard PCI swizzling.
 *
 * The default swizzling walks up the bus tree one level at a time, applying
 * the standard swizzle function at each step, stopping when it finds the PCI
 * root bus.  This will return the slot number of the bridge device on the
 * root bus and the interrupt pin on that device which should correspond
 * with the downstream device interrupt.
 *
 * Platforms may override this, in which case the slot and pin returned
 * depend entirely on the platform code.  However, please note that the
 * PCI standard swizzle is implemented on plug-in cards and Cardbus based
 * PCI extenders, so it can not be ignored.
 */
static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin)
{
	struct pci_sys_data *sys = dev->sysdata;
	int slot, oldpin = *pin;

	if (sys->swizzle)
		slot = sys->swizzle(dev, pin);
	else
		slot = pci_common_swizzle(dev, pin);

	if (debug_pci)
		printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
			pci_name(dev), oldpin, *pin, slot);

	return slot;
}

/*
 * Map a slot/pin to an IRQ.
 */
static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	struct pci_sys_data *sys = dev->sysdata;
	int irq = -1;

	if (sys->map_irq)
		irq = sys->map_irq(dev, slot, pin);

	if (debug_pci)
		printk("PCI: %s mapping slot %d pin %d => irq %d\n",
			pci_name(dev), slot, pin, irq);

	return irq;
}

static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)
{
	int ret;
	struct pci_host_bridge_window *window;

	if (list_empty(&sys->resources)) {
		pci_add_resource_offset(&sys->resources,
			 &iomem_resource, sys->mem_offset);
	}

	list_for_each_entry(window, &sys->resources, list) {
		if (resource_type(window->res) == IORESOURCE_IO)
			return 0;
	}

	sys->io_res.start = (busnr * SZ_64K) ?  : pcibios_min_io;
	sys->io_res.end = (busnr + 1) * SZ_64K - 1;
	sys->io_res.flags = IORESOURCE_IO;
	sys->io_res.name = sys->io_res_name;
	sprintf(sys->io_res_name, "PCI%d I/O", busnr);

	ret = request_resource(&ioport_resource, &sys->io_res);
	if (ret) {
		pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
		return ret;
	}
	pci_add_resource_offset(&sys->resources, &sys->io_res,
				sys->io_offset);

	return 0;
}

static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
{
	struct pci_sys_data *sys = NULL;
	int ret;
	int nr, busnr;

	for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
		sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
		if (!sys)
			panic("PCI: unable to allocate sys data!");

#ifdef CONFIG_PCI_DOMAINS
		sys->domain  = hw->domain;
#endif
		sys->busnr   = busnr;
		sys->swizzle = hw->swizzle;
		sys->map_irq = hw->map_irq;
		INIT_LIST_HEAD(&sys->resources);

		if (hw->private_data)
			sys->private_data = hw->private_data[nr];

		ret = hw->setup(nr, sys);

		if (ret > 0) {
			ret = pcibios_init_resources(nr, sys);
			if (ret)  {
				kfree(sys);
				break;
			}

			if (hw->scan)
				sys->bus = hw->scan(nr, sys);
			else
				sys->bus = pci_scan_root_bus(NULL, sys->busnr,
						hw->ops, sys, &sys->resources);

			if (!sys->bus)
				panic("PCI: unable to scan bus!");

			busnr = sys->bus->busn_res.end + 1;

			list_add(&sys->node, head);
		} else {
			kfree(sys);
			if (ret < 0)
				break;
		}
	}
}

void pci_common_init(struct hw_pci *hw)
{
	struct pci_sys_data *sys;
	LIST_HEAD(head);

	pci_add_flags(PCI_REASSIGN_ALL_RSRC);
	if (hw->preinit)
		hw->preinit();
	pcibios_init_hw(hw, &head);
	if (hw->postinit)
		hw->postinit();

	pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);

	list_for_each_entry(sys, &head, node) {
		struct pci_bus *bus = sys->bus;

		if (!pci_has_flag(PCI_PROBE_ONLY)) {
			/*
			 * Size the bridge windows.
			 */
			pci_bus_size_bridges(bus);

			/*
			 * Assign resources.
			 */
			pci_bus_assign_resources(bus);

			/*
			 * Enable bridges
			 */
			pci_enable_bridges(bus);
		}

		/*
		 * Tell drivers about devices found.
		 */
		pci_bus_add_devices(bus);
	}
}

#ifndef CONFIG_PCI_HOST_ITE8152
void pcibios_set_master(struct pci_dev *dev)
{
	/* No special bus mastering setup handling */
}
#endif

char * __init pcibios_setup(char *str)
{
	if (!strcmp(str, "debug")) {
		debug_pci = 1;
		return NULL;
	} else if (!strcmp(str, "firmware")) {
		pci_add_flags(PCI_PROBE_ONLY);
		return NULL;
	}
	return str;
}

/*
 * From arch/i386/kernel/pci-i386.c:
 *
 * We need to avoid collisions with `mirrored' VGA ports
 * and other strange ISA hardware, so we always want the
 * addresses to be allocated in the 0x000-0x0ff region
 * modulo 0x400.
 *
 * Why? Because some silly external IO cards only decode
 * the low 10 bits of the IO address. The 0x00-0xff region
 * is reserved for motherboard devices that decode all 16
 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 * but we want to try to avoid allocating at 0x2900-0x2bff
 * which might be mirrored at 0x0100-0x03ff..
 */
resource_size_t pcibios_align_resource(void *data, const struct resource *res,
				resource_size_t size, resource_size_t align)
{
	resource_size_t start = res->start;

	if (res->flags & IORESOURCE_IO && start & 0x300)
		start = (start + 0x3ff) & ~0x3ff;

	start = (start + align - 1) & ~(align - 1);

	return start;
}

/**
 * pcibios_enable_device - Enable I/O and memory.
 * @dev: PCI device to be enabled
 */
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int idx;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;
	for (idx = 0; idx < 6; idx++) {
		/* Only set up the requested stuff */
		if (!(mask & (1 << idx)))
			continue;

		r = dev->resource + idx;
		if (!r->start && r->end) {
			printk(KERN_ERR "PCI: Device %s not available because"
			       " of resource collisions\n", pci_name(dev));
			return -EINVAL;
		}
		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}

	/*
	 * Bridges (eg, cardbus bridges) need to be fully enabled
	 */
	if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
		cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;

	if (cmd != old_cmd) {
		printk("PCI: enabling device %s (%04x -> %04x)\n",
		       pci_name(dev), old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}

int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
			enum pci_mmap_state mmap_state, int write_combine)
{
	struct pci_sys_data *root = dev->sysdata;
	unsigned long phys;

	if (mmap_state == pci_mmap_io) {
		return -EINVAL;
	} else {
		phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT);
	}

	/*
	 * Mark this as IO
	 */
	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);

	if (remap_pfn_range(vma, vma->vm_start, phys,
			     vma->vm_end - vma->vm_start,
			     vma->vm_page_prot))
		return -EAGAIN;

	return 0;
}

void __init pci_map_io_early(unsigned long pfn)
{
	struct map_desc pci_io_desc = {
		.virtual	= PCI_IO_VIRT_BASE,
		.type		= MT_DEVICE,
		.length		= SZ_64K,
	};

	pci_io_desc.pfn = pfn;
	iotable_init(&pci_io_desc, 1);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/kernel/bios32.c
	3	*
	4	* PCI bios-type initialisation for PCI machines
	5	*
	6	* Bits taken from various places.
	7	*/
ecea4ab6	8	#include <linux/export.h>
1da177e4 LT	9	#include <linux/kernel.h>
	10	#include <linux/pci.h>
	11	#include <linux/slab.h>
	12	#include <linux/init.h>
fced80c7	13	#include <linux/io.h>
1da177e4	14
1da177e4	15	#include <asm/mach-types.h>
c2794437	16	#include <asm/mach/map.h>
1da177e4 LT	17	#include <asm/mach/pci.h>
	18
	19	static int debug_pci;
1da177e4 LT	20
	21	/*
	22	* We can't use pci_find_device() here since we are
	23	* called from interrupt context.
	24	*/
	25	static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
	26	{
	27	struct pci_dev *dev;
	28
	29	list_for_each_entry(dev, &bus->devices, bus_list) {
	30	u16 status;
	31
	32	/*
	33	* ignore host bridge - we handle
	34	* that separately
	35	*/
	36	if (dev->bus->number == 0 && dev->devfn == 0)
	37	continue;
	38
	39	pci_read_config_word(dev, PCI_STATUS, &status);
	40	if (status == 0xffff)
	41	continue;
	42
	43	if ((status & status_mask) == 0)
	44	continue;
	45
	46	/* clear the status errors */
	47	pci_write_config_word(dev, PCI_STATUS, status & status_mask);
	48
	49	if (warn)
	50	printk("(%s: %04X) ", pci_name(dev), status);
	51	}
	52
	53	list_for_each_entry(dev, &bus->devices, bus_list)
	54	if (dev->subordinate)
	55	pcibios_bus_report_status(dev->subordinate, status_mask, warn);
	56	}
	57
	58	void pcibios_report_status(u_int status_mask, int warn)
	59	{
	60	struct list_head *l;
	61
	62	list_for_each(l, &pci_root_buses) {
	63	struct pci_bus *bus = pci_bus_b(l);
	64
	65	pcibios_bus_report_status(bus, status_mask, warn);
	66	}
	67	}
	68
	69	/*
	70	* We don't use this to fix the device, but initialisation of it.
	71	* It's not the correct use for this, but it works.
	72	* Note that the arbiter/ISA bridge appears to be buggy, specifically in
	73	* the following area:
	74	* 1. park on CPU
	75	* 2. ISA bridge ping-pong
	76	* 3. ISA bridge master handling of target RETRY
	77	*
	78	* Bug 3 is responsible for the sound DMA grinding to a halt. We now
	79	* live with bug 2.
	80	*/
351a102d	81	static void pci_fixup_83c553(struct pci_dev *dev)
1da177e4 LT	82	{
	83	/*
	84	* Set memory region to start at address 0, and enable IO
	85	*/
	86	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
	87	pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
	88
	89	dev->resource[0].end -= dev->resource[0].start;
	90	dev->resource[0].start = 0;
	91
	92	/*
	93	* All memory requests from ISA to be channelled to PCI
	94	*/
	95	pci_write_config_byte(dev, 0x48, 0xff);
	96
	97	/*
	98	* Enable ping-pong on bus master to ISA bridge transactions.
	99	* This improves the sound DMA substantially. The fixed
	100	* priority arbiter also helps (see below).
	101	*/
	102	pci_write_config_byte(dev, 0x42, 0x01);
	103
	104	/*
	105	* Enable PCI retry
	106	*/
	107	pci_write_config_byte(dev, 0x40, 0x22);
	108
	109	/*
	110	* We used to set the arbiter to "park on last master" (bit
	111	* 1 set), but unfortunately the CyberPro does not park the
	112	* bus. We must therefore park on CPU. Unfortunately, this
	113	* may trigger yet another bug in the 553.
	114	*/
	115	pci_write_config_byte(dev, 0x83, 0x02);
	116
	117	/*
	118	* Make the ISA DMA request lowest priority, and disable
	119	* rotating priorities completely.
	120	*/
	121	pci_write_config_byte(dev, 0x80, 0x11);
	122	pci_write_config_byte(dev, 0x81, 0x00);
	123
	124	/*
	125	* Route INTA input to IRQ 11, and set IRQ11 to be level
	126	* sensitive.
	127	*/
	128	pci_write_config_word(dev, 0x44, 0xb000);
	129	outb(0x08, 0x4d1);
	130	}
	131	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
	132
351a102d	133	static void pci_fixup_unassign(struct pci_dev *dev)
1da177e4 LT	134	{
	135	dev->resource[0].end -= dev->resource[0].start;
	136	dev->resource[0].start = 0;
	137	}
	138	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
	139
	140	/*
	141	* Prevent the PCI layer from seeing the resources allocated to this device
	142	* if it is the host bridge by marking it as such. These resources are of
	143	* no consequence to the PCI layer (they are handled elsewhere).
	144	*/
351a102d	145	static void pci_fixup_dec21285(struct pci_dev *dev)
1da177e4 LT	146	{
	147	int i;
	148
	149	if (dev->devfn == 0) {
	150	dev->class &= 0xff;
	151	dev->class \|= PCI_CLASS_BRIDGE_HOST << 8;
	152	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	153	dev->resource[i].start = 0;
	154	dev->resource[i].end = 0;
	155	dev->resource[i].flags = 0;
	156	}
	157	}
	158	}
	159	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
	160
1da177e4 LT	161	/*
	162	* PCI IDE controllers use non-standard I/O port decoding, respect it.
	163	*/
351a102d	164	static void pci_fixup_ide_bases(struct pci_dev *dev)
1da177e4 LT	165	{
	166	struct resource *r;
	167	int i;
	168
	169	if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
	170	return;
	171
	172	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	173	r = dev->resource + i;
	174	if ((r->start & ~0x80) == 0x374) {
	175	r->start \|= 2;
	176	r->end = r->start;
	177	}
	178	}
	179	}
	180	DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
	181
	182	/*
	183	* Put the DEC21142 to sleep
	184	*/
351a102d	185	static void pci_fixup_dec21142(struct pci_dev *dev)
1da177e4 LT	186	{
	187	pci_write_config_dword(dev, 0x40, 0x80000000);
	188	}
	189	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
	190
	191	/*
	192	* The CY82C693 needs some rather major fixups to ensure that it does
	193	* the right thing. Idea from the Alpha people, with a few additions.
	194	*
	195	* We ensure that the IDE base registers are set to 1f0/3f4 for the
	196	* primary bus, and 170/374 for the secondary bus. Also, hide them
	197	* from the PCI subsystem view as well so we won't try to perform
	198	* our own auto-configuration on them.
	199	*
	200	* In addition, we ensure that the PCI IDE interrupts are routed to
	201	* IRQ 14 and IRQ 15 respectively.
	202	*
	203	* The above gets us to a point where the IDE on this device is
	204	* functional. However, The CY82C693U _does not work_ in bus
	205	* master mode without locking the PCI bus solid.
	206	*/
351a102d	207	static void pci_fixup_cy82c693(struct pci_dev *dev)
1da177e4 LT	208	{
	209	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
	210	u32 base0, base1;
	211
	212	if (dev->class & 0x80) { /* primary */
	213	base0 = 0x1f0;
	214	base1 = 0x3f4;
	215	} else { /* secondary */
	216	base0 = 0x170;
	217	base1 = 0x374;
	218	}
	219
	220	pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
	221	base0 \| PCI_BASE_ADDRESS_SPACE_IO);
	222	pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
	223	base1 \| PCI_BASE_ADDRESS_SPACE_IO);
	224
	225	dev->resource[0].start = 0;
	226	dev->resource[0].end = 0;
	227	dev->resource[0].flags = 0;
	228
	229	dev->resource[1].start = 0;
	230	dev->resource[1].end = 0;
	231	dev->resource[1].flags = 0;
	232	} else if (PCI_FUNC(dev->devfn) == 0) {
	233	/*
	234	* Setup IDE IRQ routing.
	235	*/
	236	pci_write_config_byte(dev, 0x4b, 14);
	237	pci_write_config_byte(dev, 0x4c, 15);
	238
	239	/*
	240	* Disable FREQACK handshake, enable USB.
	241	*/
	242	pci_write_config_byte(dev, 0x4d, 0x41);
	243
	244	/*
	245	* Enable PCI retry, and PCI post-write buffer.
	246	*/
	247	pci_write_config_byte(dev, 0x44, 0x17);
	248
	249	/*
	250	* Enable ISA master and DMA post write buffering.
	251	*/
	252	pci_write_config_byte(dev, 0x45, 0x03);
	253	}
	254	}
	255	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
	256
351a102d	257	static void pci_fixup_it8152(struct pci_dev *dev)
a8fc0789 MR	258	{
	259	int i;
	260	/* fixup for ITE 8152 devices */
	261	/* FIXME: add defines for class 0x68000 and 0x80103 */
	262	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST \|\|
	263	dev->class == 0x68000 \|\|
	264	dev->class == 0x80103) {
	265	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	266	dev->resource[i].start = 0;
	267	dev->resource[i].end = 0;
	268	dev->resource[i].flags = 0;
	269	}
	270	}
	271	}
	272	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
	273
1da177e4 LT	274	/*
	275	* If the bus contains any of these devices, then we must not turn on
	276	* parity checking of any kind. Currently this is CyberPro 20x0 only.
	277	*/
	278	static inline int pdev_bad_for_parity(struct pci_dev *dev)
	279	{
a8fc0789 MR	280	return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
	281	(dev->device == PCI_DEVICE_ID_INTERG_2000 \|\|
	282	dev->device == PCI_DEVICE_ID_INTERG_2010)) \|\|
	283	(dev->vendor == PCI_VENDOR_ID_ITE &&
	284	dev->device == PCI_DEVICE_ID_ITE_8152));
	285
1da177e4 LT	286	}
1da177e4 LT	287
1da177e4 LT	288	/*
	289	* pcibios_fixup_bus - Called after each bus is probed,
	290	* but before its children are examined.
	291	*/
46edfc54	292	void pcibios_fixup_bus(struct pci_bus *bus)
1da177e4	293	{
1da177e4 LT	294	struct pci_dev *dev;
	295	u16 features = PCI_COMMAND_SERR \| PCI_COMMAND_PARITY \| PCI_COMMAND_FAST_BACK;
	296
1da177e4 LT	297	/*
	298	* Walk the devices on this bus, working out what we can
	299	* and can't support.
	300	*/
	301	list_for_each_entry(dev, &bus->devices, bus_list) {
	302	u16 status;
	303
1da177e4 LT	304	pci_read_config_word(dev, PCI_STATUS, &status);
	305
	306	/*
	307	* If any device on this bus does not support fast back
	308	* to back transfers, then the bus as a whole is not able
	309	* to support them. Having fast back to back transfers
	310	* on saves us one PCI cycle per transaction.
	311	*/
	312	if (!(status & PCI_STATUS_FAST_BACK))
	313	features &= ~PCI_COMMAND_FAST_BACK;
	314
	315	if (pdev_bad_for_parity(dev))
	316	features &= ~(PCI_COMMAND_SERR \| PCI_COMMAND_PARITY);
	317
	318	switch (dev->class >> 8) {
1da177e4 LT	319	case PCI_CLASS_BRIDGE_PCI:
	320	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
	321	status \|= PCI_BRIDGE_CTL_PARITY\|PCI_BRIDGE_CTL_MASTER_ABORT;
	322	status &= ~(PCI_BRIDGE_CTL_BUS_RESET\|PCI_BRIDGE_CTL_FAST_BACK);
	323	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
	324	break;
	325
	326	case PCI_CLASS_BRIDGE_CARDBUS:
	327	pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
	328	status \|= PCI_CB_BRIDGE_CTL_PARITY\|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
	329	pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
	330	break;
	331	}
	332	}
	333
	334	/*
	335	* Now walk the devices again, this time setting them up.
	336	*/
	337	list_for_each_entry(dev, &bus->devices, bus_list) {
	338	u16 cmd;
	339
	340	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	341	cmd \|= features;
	342	pci_write_config_word(dev, PCI_COMMAND, cmd);
	343
	344	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
	345	L1_CACHE_BYTES >> 2);
	346	}
	347
	348	/*
	349	* Propagate the flags to the PCI bridge.
	350	*/
	351	if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
	352	if (features & PCI_COMMAND_FAST_BACK)
	353	bus->bridge_ctl \|= PCI_BRIDGE_CTL_FAST_BACK;
	354	if (features & PCI_COMMAND_PARITY)
	355	bus->bridge_ctl \|= PCI_BRIDGE_CTL_PARITY;
	356	}
	357
	358	/*
	359	* Report what we did for this bus
	360	*/
	361	printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
	362	bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
	363	}
b214bea5	364	EXPORT_SYMBOL(pcibios_fixup_bus);
1da177e4	365
1da177e4	366	/*
daeb4c0c RK	367	* Swizzle the device pin each time we cross a bridge. If a platform does
	368	* not provide a swizzle function, we perform the standard PCI swizzling.
	369	*
	370	* The default swizzling walks up the bus tree one level at a time, applying
	371	* the standard swizzle function at each step, stopping when it finds the PCI
	372	* root bus. This will return the slot number of the bridge device on the
	373	* root bus and the interrupt pin on that device which should correspond
	374	* with the downstream device interrupt.
	375	*
	376	* Platforms may override this, in which case the slot and pin returned
	377	* depend entirely on the platform code. However, please note that the
	378	* PCI standard swizzle is implemented on plug-in cards and Cardbus based
	379	* PCI extenders, so it can not be ignored.
1da177e4	380	*/
351a102d	381	static u8 pcibios_swizzle(struct pci_dev dev, u8 pin)
1da177e4 LT	382	{
1da177e4 LT	383	struct pci_sys_data *sys = dev->sysdata;
daeb4c0c	384	int slot, oldpin = *pin;
1da177e4 LT	385
	386	if (sys->swizzle)
	387	slot = sys->swizzle(dev, pin);
daeb4c0c RK	388	else
daeb4c0c RK	389	slot = pci_common_swizzle(dev, pin);
1da177e4 LT	390
	391	if (debug_pci)
	392	printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
	393	pci_name(dev), oldpin, *pin, slot);
	394
	395	return slot;
	396	}
	397
	398	/*
	399	* Map a slot/pin to an IRQ.
	400	*/
d5341942	401	static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
1da177e4 LT	402	{
	403	struct pci_sys_data *sys = dev->sysdata;
	404	int irq = -1;
	405
	406	if (sys->map_irq)
	407	irq = sys->map_irq(dev, slot, pin);
	408
	409	if (debug_pci)
	410	printk("PCI: %s mapping slot %d pin %d => irq %d\n",
	411	pci_name(dev), slot, pin, irq);
	412
	413	return irq;
	414	}
	415
276fd3c5	416	static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)
3c5d1699 RH	417	{
	418	int ret;
	419	struct pci_host_bridge_window *window;
	420
	421	if (list_empty(&sys->resources)) {
	422	pci_add_resource_offset(&sys->resources,
	423	&iomem_resource, sys->mem_offset);
	424	}
	425
	426	list_for_each_entry(window, &sys->resources, list) {
	427	if (resource_type(window->res) == IORESOURCE_IO)
	428	return 0;
	429	}
	430
	431	sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io;
	432	sys->io_res.end = (busnr + 1) * SZ_64K - 1;
	433	sys->io_res.flags = IORESOURCE_IO;
	434	sys->io_res.name = sys->io_res_name;
	435	sprintf(sys->io_res_name, "PCI%d I/O", busnr);
	436
	437	ret = request_resource(&ioport_resource, &sys->io_res);
	438	if (ret) {
	439	pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
	440	return ret;
	441	}
	442	pci_add_resource_offset(&sys->resources, &sys->io_res,
	443	sys->io_offset);
	444
	445	return 0;
	446	}
	447
276fd3c5	448	static void pcibios_init_hw(struct hw_pci hw, struct list_head head)
1da177e4 LT	449	{
	450	struct pci_sys_data *sys = NULL;
	451	int ret;
	452	int nr, busnr;
	453
	454	for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
d2a02b93	455	sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
1da177e4 LT	456	if (!sys)
	457	panic("PCI: unable to allocate sys data!");
	458
52882173 AV	459	#ifdef CONFIG_PCI_DOMAINS
	460	sys->domain = hw->domain;
	461	#endif
1da177e4 LT	462	sys->busnr = busnr;
	463	sys->swizzle = hw->swizzle;
	464	sys->map_irq = hw->map_irq;
37d15909	465	INIT_LIST_HEAD(&sys->resources);
1da177e4	466
352af7d4 TR	467	if (hw->private_data)
	468	sys->private_data = hw->private_data[nr];
	469
1da177e4 LT	470	ret = hw->setup(nr, sys);
	471
	472	if (ret > 0) {
3c5d1699 RH	473	ret = pcibios_init_resources(nr, sys);
	474	if (ret) {
	475	kfree(sys);
	476	break;
37d15909 BH	477	}
37d15909 BH	478
c23bfc38 RK	479	if (hw->scan)
	480	sys->bus = hw->scan(nr, sys);
	481	else
	482	sys->bus = pci_scan_root_bus(NULL, sys->busnr,
	483	hw->ops, sys, &sys->resources);
1da177e4 LT	484
	485	if (!sys->bus)
	486	panic("PCI: unable to scan bus!");
	487
b918c62e	488	busnr = sys->bus->busn_res.end + 1;
1da177e4	489
90cf2418	490	list_add(&sys->node, head);
1da177e4 LT	491	} else {
	492	kfree(sys);
	493	if (ret < 0)
	494	break;
	495	}
	496	}
	497	}
	498
276fd3c5	499	void pci_common_init(struct hw_pci *hw)
1da177e4 LT	500	{
1da177e4 LT	501	struct pci_sys_data *sys;
90cf2418	502	LIST_HEAD(head);
1da177e4	503
6696cbc3	504	pci_add_flags(PCI_REASSIGN_ALL_RSRC);
1da177e4 LT	505	if (hw->preinit)
1da177e4 LT	506	hw->preinit();
90cf2418	507	pcibios_init_hw(hw, &head);
1da177e4 LT	508	if (hw->postinit)
	509	hw->postinit();
	510
	511	pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
	512
90cf2418	513	list_for_each_entry(sys, &head, node) {
1da177e4 LT	514	struct pci_bus *bus = sys->bus;
1da177e4 LT	515
a4fab044	516	if (!pci_has_flag(PCI_PROBE_ONLY)) {
1da177e4 LT	517	/*
	518	* Size the bridge windows.
	519	*/
	520	pci_bus_size_bridges(bus);
	521
	522	/*
	523	* Assign resources.
	524	*/
	525	pci_bus_assign_resources(bus);
a9f43c11 CT	526
	527	/*
	528	* Enable bridges
	529	*/
	530	pci_enable_bridges(bus);
1da177e4 LT	531	}
	532
	533	/*
	534	* Tell drivers about devices found.
	535	*/
	536	pci_bus_add_devices(bus);
	537	}
	538	}
	539
168c8619 MS	540	#ifndef CONFIG_PCI_HOST_ITE8152
	541	void pcibios_set_master(struct pci_dev *dev)
	542	{
	543	/* No special bus mastering setup handling */
	544	}
	545	#endif
	546
1da177e4 LT	547	char * __init pcibios_setup(char *str)
	548	{
	549	if (!strcmp(str, "debug")) {
	550	debug_pci = 1;
	551	return NULL;
	552	} else if (!strcmp(str, "firmware")) {
a4fab044	553	pci_add_flags(PCI_PROBE_ONLY);
1da177e4 LT	554	return NULL;
	555	}
	556	return str;
	557	}
	558
	559	/*
	560	* From arch/i386/kernel/pci-i386.c:
	561	*
	562	* We need to avoid collisions with `mirrored' VGA ports
	563	* and other strange ISA hardware, so we always want the
	564	* addresses to be allocated in the 0x000-0x0ff region
	565	* modulo 0x400.
	566	*
	567	* Why? Because some silly external IO cards only decode
	568	* the low 10 bits of the IO address. The 0x00-0xff region
	569	* is reserved for motherboard devices that decode all 16
	570	* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
	571	* but we want to try to avoid allocating at 0x2900-0x2bff
	572	* which might be mirrored at 0x0100-0x03ff..
	573	*/
3b7a17fc	574	resource_size_t pcibios_align_resource(void data, const struct resource res,
b26b2d49	575	resource_size_t size, resource_size_t align)
1da177e4	576	{
e31dd6e4	577	resource_size_t start = res->start;
1da177e4 LT	578
	579	if (res->flags & IORESOURCE_IO && start & 0x300)
	580	start = (start + 0x3ff) & ~0x3ff;
	581
b26b2d49 DB	582	start = (start + align - 1) & ~(align - 1);
	583
	584	return start;
1da177e4 LT	585	}
	586
	587	/**
	588	* pcibios_enable_device - Enable I/O and memory.
	589	* @dev: PCI device to be enabled
	590	*/
	591	int pcibios_enable_device(struct pci_dev *dev, int mask)
	592	{
	593	u16 cmd, old_cmd;
	594	int idx;
	595	struct resource *r;
	596
	597	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	598	old_cmd = cmd;
	599	for (idx = 0; idx < 6; idx++) {
	600	/* Only set up the requested stuff */
	601	if (!(mask & (1 << idx)))
	602	continue;
	603
	604	r = dev->resource + idx;
	605	if (!r->start && r->end) {
	606	printk(KERN_ERR "PCI: Device %s not available because"
	607	" of resource collisions\n", pci_name(dev));
	608	return -EINVAL;
	609	}
	610	if (r->flags & IORESOURCE_IO)
	611	cmd \|= PCI_COMMAND_IO;
	612	if (r->flags & IORESOURCE_MEM)
	613	cmd \|= PCI_COMMAND_MEMORY;
	614	}
	615
	616	/*
	617	* Bridges (eg, cardbus bridges) need to be fully enabled
	618	*/
	619	if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
	620	cmd \|= PCI_COMMAND_IO \| PCI_COMMAND_MEMORY;
	621
	622	if (cmd != old_cmd) {
	623	printk("PCI: enabling device %s (%04x -> %04x)\n",
	624	pci_name(dev), old_cmd, cmd);
	625	pci_write_config_word(dev, PCI_COMMAND, cmd);
	626	}
	627	return 0;
	628	}
	629
	630	int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	631	enum pci_mmap_state mmap_state, int write_combine)
	632	{
	633	struct pci_sys_data *root = dev->sysdata;
	634	unsigned long phys;
	635
	636	if (mmap_state == pci_mmap_io) {
	637	return -EINVAL;
	638	} else {
	639	phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT);
	640	}
	641
	642	/*
	643	* Mark this as IO
	644	*/
1da177e4 LT	645	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
	646
	647	if (remap_pfn_range(vma, vma->vm_start, phys,
	648	vma->vm_end - vma->vm_start,
	649	vma->vm_page_prot))
	650	return -EAGAIN;
	651
	652	return 0;
	653	}
c2794437 RH	654
	655	void __init pci_map_io_early(unsigned long pfn)
	656	{
	657	struct map_desc pci_io_desc = {
	658	.virtual = PCI_IO_VIRT_BASE,
	659	.type = MT_DEVICE,
	660	.length = SZ_64K,
	661	};
	662
	663	pci_io_desc.pfn = pfn;
	664	iotable_init(&pci_io_desc, 1);
	665	}