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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | /* |
3 | * linux/arch/arm/kernel/bios32.c | |
4 | * | |
5 | * PCI bios-type initialisation for PCI machines | |
6 | * | |
7 | * Bits taken from various places. | |
8 | */ | |
ecea4ab6 | 9 | #include <linux/export.h> |
1da177e4 LT |
10 | #include <linux/kernel.h> |
11 | #include <linux/pci.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/init.h> | |
fced80c7 | 14 | #include <linux/io.h> |
1da177e4 | 15 | |
1da177e4 | 16 | #include <asm/mach-types.h> |
c2794437 | 17 | #include <asm/mach/map.h> |
1da177e4 LT |
18 | #include <asm/mach/pci.h> |
19 | ||
20 | static int debug_pci; | |
1da177e4 LT |
21 | |
22 | /* | |
5ee09efe | 23 | * We can't use pci_get_device() here since we are |
1da177e4 LT |
24 | * called from interrupt context. |
25 | */ | |
26 | static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn) | |
27 | { | |
28 | struct pci_dev *dev; | |
29 | ||
30 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
31 | u16 status; | |
32 | ||
33 | /* | |
34 | * ignore host bridge - we handle | |
35 | * that separately | |
36 | */ | |
37 | if (dev->bus->number == 0 && dev->devfn == 0) | |
38 | continue; | |
39 | ||
40 | pci_read_config_word(dev, PCI_STATUS, &status); | |
41 | if (status == 0xffff) | |
42 | continue; | |
43 | ||
44 | if ((status & status_mask) == 0) | |
45 | continue; | |
46 | ||
47 | /* clear the status errors */ | |
48 | pci_write_config_word(dev, PCI_STATUS, status & status_mask); | |
49 | ||
50 | if (warn) | |
51 | printk("(%s: %04X) ", pci_name(dev), status); | |
52 | } | |
53 | ||
54 | list_for_each_entry(dev, &bus->devices, bus_list) | |
55 | if (dev->subordinate) | |
56 | pcibios_bus_report_status(dev->subordinate, status_mask, warn); | |
57 | } | |
58 | ||
59 | void pcibios_report_status(u_int status_mask, int warn) | |
60 | { | |
f0197e0c | 61 | struct pci_bus *bus; |
1da177e4 | 62 | |
f0197e0c | 63 | list_for_each_entry(bus, &pci_root_buses, node) |
1da177e4 | 64 | pcibios_bus_report_status(bus, status_mask, warn); |
1da177e4 LT |
65 | } |
66 | ||
67 | /* | |
68 | * We don't use this to fix the device, but initialisation of it. | |
69 | * It's not the correct use for this, but it works. | |
70 | * Note that the arbiter/ISA bridge appears to be buggy, specifically in | |
71 | * the following area: | |
72 | * 1. park on CPU | |
73 | * 2. ISA bridge ping-pong | |
74 | * 3. ISA bridge master handling of target RETRY | |
75 | * | |
76 | * Bug 3 is responsible for the sound DMA grinding to a halt. We now | |
77 | * live with bug 2. | |
78 | */ | |
351a102d | 79 | static void pci_fixup_83c553(struct pci_dev *dev) |
1da177e4 LT |
80 | { |
81 | /* | |
82 | * Set memory region to start at address 0, and enable IO | |
83 | */ | |
84 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY); | |
85 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO); | |
86 | ||
87 | dev->resource[0].end -= dev->resource[0].start; | |
88 | dev->resource[0].start = 0; | |
89 | ||
90 | /* | |
91 | * All memory requests from ISA to be channelled to PCI | |
92 | */ | |
93 | pci_write_config_byte(dev, 0x48, 0xff); | |
94 | ||
95 | /* | |
96 | * Enable ping-pong on bus master to ISA bridge transactions. | |
97 | * This improves the sound DMA substantially. The fixed | |
98 | * priority arbiter also helps (see below). | |
99 | */ | |
100 | pci_write_config_byte(dev, 0x42, 0x01); | |
101 | ||
102 | /* | |
103 | * Enable PCI retry | |
104 | */ | |
105 | pci_write_config_byte(dev, 0x40, 0x22); | |
106 | ||
107 | /* | |
108 | * We used to set the arbiter to "park on last master" (bit | |
109 | * 1 set), but unfortunately the CyberPro does not park the | |
110 | * bus. We must therefore park on CPU. Unfortunately, this | |
111 | * may trigger yet another bug in the 553. | |
112 | */ | |
113 | pci_write_config_byte(dev, 0x83, 0x02); | |
114 | ||
115 | /* | |
116 | * Make the ISA DMA request lowest priority, and disable | |
117 | * rotating priorities completely. | |
118 | */ | |
119 | pci_write_config_byte(dev, 0x80, 0x11); | |
120 | pci_write_config_byte(dev, 0x81, 0x00); | |
121 | ||
122 | /* | |
123 | * Route INTA input to IRQ 11, and set IRQ11 to be level | |
124 | * sensitive. | |
125 | */ | |
126 | pci_write_config_word(dev, 0x44, 0xb000); | |
127 | outb(0x08, 0x4d1); | |
128 | } | |
129 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553); | |
130 | ||
351a102d | 131 | static void pci_fixup_unassign(struct pci_dev *dev) |
1da177e4 LT |
132 | { |
133 | dev->resource[0].end -= dev->resource[0].start; | |
134 | dev->resource[0].start = 0; | |
135 | } | |
136 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign); | |
137 | ||
138 | /* | |
139 | * Prevent the PCI layer from seeing the resources allocated to this device | |
140 | * if it is the host bridge by marking it as such. These resources are of | |
141 | * no consequence to the PCI layer (they are handled elsewhere). | |
142 | */ | |
351a102d | 143 | static void pci_fixup_dec21285(struct pci_dev *dev) |
1da177e4 LT |
144 | { |
145 | int i; | |
146 | ||
147 | if (dev->devfn == 0) { | |
148 | dev->class &= 0xff; | |
149 | dev->class |= PCI_CLASS_BRIDGE_HOST << 8; | |
150 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
151 | dev->resource[i].start = 0; | |
152 | dev->resource[i].end = 0; | |
153 | dev->resource[i].flags = 0; | |
154 | } | |
155 | } | |
156 | } | |
157 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285); | |
158 | ||
1da177e4 LT |
159 | /* |
160 | * PCI IDE controllers use non-standard I/O port decoding, respect it. | |
161 | */ | |
351a102d | 162 | static void pci_fixup_ide_bases(struct pci_dev *dev) |
1da177e4 LT |
163 | { |
164 | struct resource *r; | |
165 | int i; | |
166 | ||
167 | if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) | |
168 | return; | |
169 | ||
170 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
171 | r = dev->resource + i; | |
172 | if ((r->start & ~0x80) == 0x374) { | |
173 | r->start |= 2; | |
174 | r->end = r->start; | |
175 | } | |
176 | } | |
177 | } | |
178 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); | |
179 | ||
180 | /* | |
181 | * Put the DEC21142 to sleep | |
182 | */ | |
351a102d | 183 | static void pci_fixup_dec21142(struct pci_dev *dev) |
1da177e4 LT |
184 | { |
185 | pci_write_config_dword(dev, 0x40, 0x80000000); | |
186 | } | |
187 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142); | |
188 | ||
189 | /* | |
190 | * The CY82C693 needs some rather major fixups to ensure that it does | |
191 | * the right thing. Idea from the Alpha people, with a few additions. | |
192 | * | |
193 | * We ensure that the IDE base registers are set to 1f0/3f4 for the | |
194 | * primary bus, and 170/374 for the secondary bus. Also, hide them | |
195 | * from the PCI subsystem view as well so we won't try to perform | |
196 | * our own auto-configuration on them. | |
197 | * | |
198 | * In addition, we ensure that the PCI IDE interrupts are routed to | |
199 | * IRQ 14 and IRQ 15 respectively. | |
200 | * | |
201 | * The above gets us to a point where the IDE on this device is | |
202 | * functional. However, The CY82C693U _does not work_ in bus | |
203 | * master mode without locking the PCI bus solid. | |
204 | */ | |
351a102d | 205 | static void pci_fixup_cy82c693(struct pci_dev *dev) |
1da177e4 LT |
206 | { |
207 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
208 | u32 base0, base1; | |
209 | ||
210 | if (dev->class & 0x80) { /* primary */ | |
211 | base0 = 0x1f0; | |
212 | base1 = 0x3f4; | |
213 | } else { /* secondary */ | |
214 | base0 = 0x170; | |
215 | base1 = 0x374; | |
216 | } | |
217 | ||
218 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, | |
219 | base0 | PCI_BASE_ADDRESS_SPACE_IO); | |
220 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, | |
221 | base1 | PCI_BASE_ADDRESS_SPACE_IO); | |
222 | ||
223 | dev->resource[0].start = 0; | |
224 | dev->resource[0].end = 0; | |
225 | dev->resource[0].flags = 0; | |
226 | ||
227 | dev->resource[1].start = 0; | |
228 | dev->resource[1].end = 0; | |
229 | dev->resource[1].flags = 0; | |
230 | } else if (PCI_FUNC(dev->devfn) == 0) { | |
231 | /* | |
232 | * Setup IDE IRQ routing. | |
233 | */ | |
234 | pci_write_config_byte(dev, 0x4b, 14); | |
235 | pci_write_config_byte(dev, 0x4c, 15); | |
236 | ||
237 | /* | |
238 | * Disable FREQACK handshake, enable USB. | |
239 | */ | |
240 | pci_write_config_byte(dev, 0x4d, 0x41); | |
241 | ||
242 | /* | |
243 | * Enable PCI retry, and PCI post-write buffer. | |
244 | */ | |
245 | pci_write_config_byte(dev, 0x44, 0x17); | |
246 | ||
247 | /* | |
248 | * Enable ISA master and DMA post write buffering. | |
249 | */ | |
250 | pci_write_config_byte(dev, 0x45, 0x03); | |
251 | } | |
252 | } | |
253 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693); | |
254 | ||
351a102d | 255 | static void pci_fixup_it8152(struct pci_dev *dev) |
a8fc0789 MR |
256 | { |
257 | int i; | |
258 | /* fixup for ITE 8152 devices */ | |
259 | /* FIXME: add defines for class 0x68000 and 0x80103 */ | |
260 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST || | |
261 | dev->class == 0x68000 || | |
262 | dev->class == 0x80103) { | |
263 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
264 | dev->resource[i].start = 0; | |
265 | dev->resource[i].end = 0; | |
266 | dev->resource[i].flags = 0; | |
267 | } | |
268 | } | |
269 | } | |
270 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152); | |
271 | ||
1da177e4 LT |
272 | /* |
273 | * If the bus contains any of these devices, then we must not turn on | |
274 | * parity checking of any kind. Currently this is CyberPro 20x0 only. | |
275 | */ | |
276 | static inline int pdev_bad_for_parity(struct pci_dev *dev) | |
277 | { | |
a8fc0789 MR |
278 | return ((dev->vendor == PCI_VENDOR_ID_INTERG && |
279 | (dev->device == PCI_DEVICE_ID_INTERG_2000 || | |
280 | dev->device == PCI_DEVICE_ID_INTERG_2010)) || | |
281 | (dev->vendor == PCI_VENDOR_ID_ITE && | |
282 | dev->device == PCI_DEVICE_ID_ITE_8152)); | |
283 | ||
1da177e4 LT |
284 | } |
285 | ||
1da177e4 LT |
286 | /* |
287 | * pcibios_fixup_bus - Called after each bus is probed, | |
288 | * but before its children are examined. | |
289 | */ | |
46edfc54 | 290 | void pcibios_fixup_bus(struct pci_bus *bus) |
1da177e4 | 291 | { |
1da177e4 LT |
292 | struct pci_dev *dev; |
293 | u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK; | |
294 | ||
1da177e4 LT |
295 | /* |
296 | * Walk the devices on this bus, working out what we can | |
297 | * and can't support. | |
298 | */ | |
299 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
300 | u16 status; | |
301 | ||
1da177e4 LT |
302 | pci_read_config_word(dev, PCI_STATUS, &status); |
303 | ||
304 | /* | |
305 | * If any device on this bus does not support fast back | |
306 | * to back transfers, then the bus as a whole is not able | |
307 | * to support them. Having fast back to back transfers | |
308 | * on saves us one PCI cycle per transaction. | |
309 | */ | |
310 | if (!(status & PCI_STATUS_FAST_BACK)) | |
311 | features &= ~PCI_COMMAND_FAST_BACK; | |
312 | ||
313 | if (pdev_bad_for_parity(dev)) | |
314 | features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); | |
315 | ||
316 | switch (dev->class >> 8) { | |
1da177e4 LT |
317 | case PCI_CLASS_BRIDGE_PCI: |
318 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status); | |
319 | status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT; | |
320 | status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK); | |
321 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status); | |
322 | break; | |
323 | ||
324 | case PCI_CLASS_BRIDGE_CARDBUS: | |
325 | pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status); | |
326 | status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT; | |
327 | pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status); | |
328 | break; | |
329 | } | |
330 | } | |
331 | ||
332 | /* | |
333 | * Now walk the devices again, this time setting them up. | |
334 | */ | |
335 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
336 | u16 cmd; | |
337 | ||
338 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
339 | cmd |= features; | |
340 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
341 | ||
342 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, | |
343 | L1_CACHE_BYTES >> 2); | |
344 | } | |
345 | ||
346 | /* | |
347 | * Propagate the flags to the PCI bridge. | |
348 | */ | |
349 | if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
350 | if (features & PCI_COMMAND_FAST_BACK) | |
351 | bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK; | |
352 | if (features & PCI_COMMAND_PARITY) | |
353 | bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY; | |
354 | } | |
355 | ||
356 | /* | |
357 | * Report what we did for this bus | |
358 | */ | |
4ed89f22 | 359 | pr_info("PCI: bus%d: Fast back to back transfers %sabled\n", |
1da177e4 LT |
360 | bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis"); |
361 | } | |
b214bea5 | 362 | EXPORT_SYMBOL(pcibios_fixup_bus); |
1da177e4 | 363 | |
1da177e4 | 364 | /* |
daeb4c0c RK |
365 | * Swizzle the device pin each time we cross a bridge. If a platform does |
366 | * not provide a swizzle function, we perform the standard PCI swizzling. | |
367 | * | |
368 | * The default swizzling walks up the bus tree one level at a time, applying | |
369 | * the standard swizzle function at each step, stopping when it finds the PCI | |
370 | * root bus. This will return the slot number of the bridge device on the | |
371 | * root bus and the interrupt pin on that device which should correspond | |
372 | * with the downstream device interrupt. | |
373 | * | |
374 | * Platforms may override this, in which case the slot and pin returned | |
375 | * depend entirely on the platform code. However, please note that the | |
376 | * PCI standard swizzle is implemented on plug-in cards and Cardbus based | |
377 | * PCI extenders, so it can not be ignored. | |
1da177e4 | 378 | */ |
351a102d | 379 | static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin) |
1da177e4 LT |
380 | { |
381 | struct pci_sys_data *sys = dev->sysdata; | |
daeb4c0c | 382 | int slot, oldpin = *pin; |
1da177e4 LT |
383 | |
384 | if (sys->swizzle) | |
385 | slot = sys->swizzle(dev, pin); | |
daeb4c0c RK |
386 | else |
387 | slot = pci_common_swizzle(dev, pin); | |
1da177e4 LT |
388 | |
389 | if (debug_pci) | |
390 | printk("PCI: %s swizzling pin %d => pin %d slot %d\n", | |
391 | pci_name(dev), oldpin, *pin, slot); | |
392 | ||
393 | return slot; | |
394 | } | |
395 | ||
396 | /* | |
397 | * Map a slot/pin to an IRQ. | |
398 | */ | |
d5341942 | 399 | static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
1da177e4 LT |
400 | { |
401 | struct pci_sys_data *sys = dev->sysdata; | |
402 | int irq = -1; | |
403 | ||
404 | if (sys->map_irq) | |
405 | irq = sys->map_irq(dev, slot, pin); | |
406 | ||
407 | if (debug_pci) | |
408 | printk("PCI: %s mapping slot %d pin %d => irq %d\n", | |
409 | pci_name(dev), slot, pin, irq); | |
410 | ||
411 | return irq; | |
412 | } | |
413 | ||
1fa05101 BH |
414 | static int pcibios_init_resource(int busnr, struct pci_sys_data *sys, |
415 | int io_optional) | |
3c5d1699 RH |
416 | { |
417 | int ret; | |
14d76b68 | 418 | struct resource_entry *window; |
3c5d1699 RH |
419 | |
420 | if (list_empty(&sys->resources)) { | |
421 | pci_add_resource_offset(&sys->resources, | |
422 | &iomem_resource, sys->mem_offset); | |
423 | } | |
424 | ||
1fa05101 BH |
425 | /* |
426 | * If a platform says I/O port support is optional, we don't add | |
427 | * the default I/O space. The platform is responsible for adding | |
428 | * any I/O space it needs. | |
429 | */ | |
430 | if (io_optional) | |
431 | return 0; | |
432 | ||
14d76b68 | 433 | resource_list_for_each_entry(window, &sys->resources) |
3c5d1699 RH |
434 | if (resource_type(window->res) == IORESOURCE_IO) |
435 | return 0; | |
3c5d1699 RH |
436 | |
437 | sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io; | |
438 | sys->io_res.end = (busnr + 1) * SZ_64K - 1; | |
439 | sys->io_res.flags = IORESOURCE_IO; | |
440 | sys->io_res.name = sys->io_res_name; | |
441 | sprintf(sys->io_res_name, "PCI%d I/O", busnr); | |
442 | ||
443 | ret = request_resource(&ioport_resource, &sys->io_res); | |
444 | if (ret) { | |
445 | pr_err("PCI: unable to allocate I/O port region (%d)\n", ret); | |
446 | return ret; | |
447 | } | |
448 | pci_add_resource_offset(&sys->resources, &sys->io_res, | |
449 | sys->io_offset); | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
14d86e72 LW |
454 | static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, |
455 | struct list_head *head) | |
1da177e4 LT |
456 | { |
457 | struct pci_sys_data *sys = NULL; | |
458 | int ret; | |
459 | int nr, busnr; | |
460 | ||
461 | for (nr = busnr = 0; nr < hw->nr_controllers; nr++) { | |
97ad2bdc LP |
462 | struct pci_host_bridge *bridge; |
463 | ||
464 | bridge = pci_alloc_host_bridge(sizeof(struct pci_sys_data)); | |
465 | if (WARN(!bridge, "PCI: unable to allocate bridge!")) | |
ada8b675 | 466 | break; |
1da177e4 | 467 | |
97ad2bdc LP |
468 | sys = pci_host_bridge_priv(bridge); |
469 | ||
1da177e4 LT |
470 | sys->busnr = busnr; |
471 | sys->swizzle = hw->swizzle; | |
472 | sys->map_irq = hw->map_irq; | |
37d15909 | 473 | INIT_LIST_HEAD(&sys->resources); |
1da177e4 | 474 | |
352af7d4 TR |
475 | if (hw->private_data) |
476 | sys->private_data = hw->private_data[nr]; | |
477 | ||
1da177e4 LT |
478 | ret = hw->setup(nr, sys); |
479 | ||
480 | if (ret > 0) { | |
7c7a0e94 | 481 | |
1fa05101 | 482 | ret = pcibios_init_resource(nr, sys, hw->io_optional); |
3c5d1699 | 483 | if (ret) { |
f01fc417 | 484 | pci_free_host_bridge(bridge); |
3c5d1699 | 485 | break; |
37d15909 BH |
486 | } |
487 | ||
16508469 LP |
488 | bridge->map_irq = pcibios_map_irq; |
489 | bridge->swizzle_irq = pcibios_swizzle; | |
490 | ||
c23bfc38 | 491 | if (hw->scan) |
97ad2bdc LP |
492 | ret = hw->scan(nr, bridge); |
493 | else { | |
494 | list_splice_init(&sys->resources, | |
495 | &bridge->windows); | |
496 | bridge->dev.parent = parent; | |
497 | bridge->sysdata = sys; | |
498 | bridge->busnr = sys->busnr; | |
499 | bridge->ops = hw->ops; | |
500 | bridge->msi = hw->msi_ctrl; | |
501 | bridge->align_resource = | |
502 | hw->align_resource; | |
503 | ||
504 | ret = pci_scan_root_bus_bridge(bridge); | |
505 | } | |
1da177e4 | 506 | |
97ad2bdc LP |
507 | if (WARN(ret < 0, "PCI: unable to scan bus!")) { |
508 | pci_free_host_bridge(bridge); | |
ada8b675 LP |
509 | break; |
510 | } | |
1da177e4 | 511 | |
97ad2bdc LP |
512 | sys->bus = bridge->bus; |
513 | ||
b918c62e | 514 | busnr = sys->bus->busn_res.end + 1; |
1da177e4 | 515 | |
90cf2418 | 516 | list_add(&sys->node, head); |
1da177e4 | 517 | } else { |
97ad2bdc | 518 | pci_free_host_bridge(bridge); |
1da177e4 LT |
519 | if (ret < 0) |
520 | break; | |
521 | } | |
522 | } | |
523 | } | |
524 | ||
14d86e72 | 525 | void pci_common_init_dev(struct device *parent, struct hw_pci *hw) |
1da177e4 LT |
526 | { |
527 | struct pci_sys_data *sys; | |
90cf2418 | 528 | LIST_HEAD(head); |
1da177e4 | 529 | |
6696cbc3 | 530 | pci_add_flags(PCI_REASSIGN_ALL_RSRC); |
1da177e4 LT |
531 | if (hw->preinit) |
532 | hw->preinit(); | |
14d86e72 | 533 | pcibios_init_hw(parent, hw, &head); |
1da177e4 LT |
534 | if (hw->postinit) |
535 | hw->postinit(); | |
536 | ||
90cf2418 | 537 | list_for_each_entry(sys, &head, node) { |
1da177e4 LT |
538 | struct pci_bus *bus = sys->bus; |
539 | ||
b30742aa LP |
540 | /* |
541 | * We insert PCI resources into the iomem_resource and | |
542 | * ioport_resource trees in either pci_bus_claim_resources() | |
543 | * or pci_bus_assign_resources(). | |
544 | */ | |
545 | if (pci_has_flag(PCI_PROBE_ONLY)) { | |
546 | pci_bus_claim_resources(bus); | |
547 | } else { | |
808b27a5 MK |
548 | struct pci_bus *child; |
549 | ||
1da177e4 | 550 | pci_bus_size_bridges(bus); |
1da177e4 | 551 | pci_bus_assign_resources(bus); |
1da177e4 | 552 | |
808b27a5 MK |
553 | list_for_each_entry(child, &bus->children, node) |
554 | pcie_bus_configure_settings(child); | |
555 | } | |
b30742aa | 556 | |
1da177e4 LT |
557 | pci_bus_add_devices(bus); |
558 | } | |
559 | } | |
560 | ||
168c8619 MS |
561 | #ifndef CONFIG_PCI_HOST_ITE8152 |
562 | void pcibios_set_master(struct pci_dev *dev) | |
563 | { | |
564 | /* No special bus mastering setup handling */ | |
565 | } | |
566 | #endif | |
567 | ||
1da177e4 LT |
568 | char * __init pcibios_setup(char *str) |
569 | { | |
570 | if (!strcmp(str, "debug")) { | |
571 | debug_pci = 1; | |
572 | return NULL; | |
1da177e4 LT |
573 | } |
574 | return str; | |
575 | } | |
576 | ||
577 | /* | |
578 | * From arch/i386/kernel/pci-i386.c: | |
579 | * | |
580 | * We need to avoid collisions with `mirrored' VGA ports | |
581 | * and other strange ISA hardware, so we always want the | |
582 | * addresses to be allocated in the 0x000-0x0ff region | |
583 | * modulo 0x400. | |
584 | * | |
585 | * Why? Because some silly external IO cards only decode | |
586 | * the low 10 bits of the IO address. The 0x00-0xff region | |
587 | * is reserved for motherboard devices that decode all 16 | |
588 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
589 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
590 | * which might be mirrored at 0x0100-0x03ff.. | |
591 | */ | |
3b7a17fc | 592 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
b26b2d49 | 593 | resource_size_t size, resource_size_t align) |
1da177e4 | 594 | { |
029baf14 | 595 | struct pci_dev *dev = data; |
e31dd6e4 | 596 | resource_size_t start = res->start; |
7c7a0e94 | 597 | struct pci_host_bridge *host_bridge; |
1da177e4 LT |
598 | |
599 | if (res->flags & IORESOURCE_IO && start & 0x300) | |
600 | start = (start + 0x3ff) & ~0x3ff; | |
601 | ||
b26b2d49 DB |
602 | start = (start + align - 1) & ~(align - 1); |
603 | ||
7c7a0e94 GP |
604 | host_bridge = pci_find_host_bridge(dev->bus); |
605 | ||
606 | if (host_bridge->align_resource) | |
607 | return host_bridge->align_resource(dev, res, | |
608 | start, size, align); | |
029baf14 | 609 | |
b26b2d49 | 610 | return start; |
1da177e4 LT |
611 | } |
612 | ||
c2794437 RH |
613 | void __init pci_map_io_early(unsigned long pfn) |
614 | { | |
615 | struct map_desc pci_io_desc = { | |
616 | .virtual = PCI_IO_VIRT_BASE, | |
617 | .type = MT_DEVICE, | |
618 | .length = SZ_64K, | |
619 | }; | |
620 | ||
621 | pci_io_desc.pfn = pfn; | |
622 | iotable_init(&pci_io_desc, 1); | |
623 | } |