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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/dma-isa.c | |
3 | * | |
4 | * Copyright (C) 1999-2000 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * ISA DMA primitives | |
11 | * Taken from various sources, including: | |
12 | * linux/include/asm/dma.h: Defines for using and allocating dma channels. | |
13 | * Written by Hennus Bergman, 1992. | |
14 | * High DMA channel support & info by Hannu Savolainen and John Boyd, | |
15 | * Nov. 1992. | |
16 | * arch/arm/kernel/dma-ebsa285.c | |
17 | * Copyright (C) 1998 Phil Blundell | |
18 | */ | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/init.h> | |
7cdad482 | 21 | #include <linux/dma-mapping.h> |
fced80c7 | 22 | #include <linux/io.h> |
1da177e4 LT |
23 | |
24 | #include <asm/dma.h> | |
1da177e4 LT |
25 | #include <asm/mach/dma.h> |
26 | ||
27 | #define ISA_DMA_MODE_READ 0x44 | |
28 | #define ISA_DMA_MODE_WRITE 0x48 | |
29 | #define ISA_DMA_MODE_CASCADE 0xc0 | |
30 | #define ISA_DMA_AUTOINIT 0x10 | |
31 | ||
32 | #define ISA_DMA_MASK 0 | |
33 | #define ISA_DMA_MODE 1 | |
34 | #define ISA_DMA_CLRFF 2 | |
35 | #define ISA_DMA_PGHI 3 | |
36 | #define ISA_DMA_PGLO 4 | |
37 | #define ISA_DMA_ADDR 5 | |
38 | #define ISA_DMA_COUNT 6 | |
39 | ||
40 | static unsigned int isa_dma_port[8][7] = { | |
41 | /* MASK MODE CLRFF PAGE_HI PAGE_LO ADDR COUNT */ | |
42 | { 0x0a, 0x0b, 0x0c, 0x487, 0x087, 0x00, 0x01 }, | |
43 | { 0x0a, 0x0b, 0x0c, 0x483, 0x083, 0x02, 0x03 }, | |
44 | { 0x0a, 0x0b, 0x0c, 0x481, 0x081, 0x04, 0x05 }, | |
45 | { 0x0a, 0x0b, 0x0c, 0x482, 0x082, 0x06, 0x07 }, | |
46 | { 0xd4, 0xd6, 0xd8, 0x000, 0x000, 0xc0, 0xc2 }, | |
47 | { 0xd4, 0xd6, 0xd8, 0x48b, 0x08b, 0xc4, 0xc6 }, | |
48 | { 0xd4, 0xd6, 0xd8, 0x489, 0x089, 0xc8, 0xca }, | |
49 | { 0xd4, 0xd6, 0xd8, 0x48a, 0x08a, 0xcc, 0xce } | |
50 | }; | |
51 | ||
1df81302 | 52 | static int isa_get_dma_residue(unsigned int chan, dma_t *dma) |
1da177e4 | 53 | { |
1df81302 | 54 | unsigned int io_port = isa_dma_port[chan][ISA_DMA_COUNT]; |
1da177e4 LT |
55 | int count; |
56 | ||
57 | count = 1 + inb(io_port); | |
58 | count |= inb(io_port) << 8; | |
59 | ||
1df81302 | 60 | return chan < 4 ? count : (count << 1); |
1da177e4 LT |
61 | } |
62 | ||
1df81302 | 63 | static void isa_enable_dma(unsigned int chan, dma_t *dma) |
1da177e4 LT |
64 | { |
65 | if (dma->invalid) { | |
66 | unsigned long address, length; | |
7cdad482 RK |
67 | unsigned int mode; |
68 | enum dma_data_direction direction; | |
1da177e4 | 69 | |
1df81302 | 70 | mode = chan & 3; |
1da177e4 LT |
71 | switch (dma->dma_mode & DMA_MODE_MASK) { |
72 | case DMA_MODE_READ: | |
73 | mode |= ISA_DMA_MODE_READ; | |
7cdad482 | 74 | direction = DMA_FROM_DEVICE; |
1da177e4 LT |
75 | break; |
76 | ||
77 | case DMA_MODE_WRITE: | |
78 | mode |= ISA_DMA_MODE_WRITE; | |
7cdad482 | 79 | direction = DMA_TO_DEVICE; |
1da177e4 LT |
80 | break; |
81 | ||
82 | case DMA_MODE_CASCADE: | |
83 | mode |= ISA_DMA_MODE_CASCADE; | |
7cdad482 | 84 | direction = DMA_BIDIRECTIONAL; |
1da177e4 LT |
85 | break; |
86 | ||
87 | default: | |
7cdad482 | 88 | direction = DMA_NONE; |
1da177e4 LT |
89 | break; |
90 | } | |
91 | ||
7cdad482 | 92 | if (!dma->sg) { |
1da177e4 LT |
93 | /* |
94 | * Cope with ISA-style drivers which expect cache | |
95 | * coherence. | |
96 | */ | |
7cdad482 RK |
97 | dma->sg = &dma->buf; |
98 | dma->sgcount = 1; | |
99 | dma->buf.length = dma->count; | |
100 | dma->buf.dma_address = dma_map_single(NULL, | |
101 | dma->addr, dma->count, | |
1da177e4 LT |
102 | direction); |
103 | } | |
104 | ||
105 | address = dma->buf.dma_address; | |
106 | length = dma->buf.length - 1; | |
107 | ||
1df81302 RK |
108 | outb(address >> 16, isa_dma_port[chan][ISA_DMA_PGLO]); |
109 | outb(address >> 24, isa_dma_port[chan][ISA_DMA_PGHI]); | |
1da177e4 | 110 | |
1df81302 | 111 | if (chan >= 4) { |
1da177e4 LT |
112 | address >>= 1; |
113 | length >>= 1; | |
114 | } | |
115 | ||
1df81302 | 116 | outb(0, isa_dma_port[chan][ISA_DMA_CLRFF]); |
1da177e4 | 117 | |
1df81302 RK |
118 | outb(address, isa_dma_port[chan][ISA_DMA_ADDR]); |
119 | outb(address >> 8, isa_dma_port[chan][ISA_DMA_ADDR]); | |
1da177e4 | 120 | |
1df81302 RK |
121 | outb(length, isa_dma_port[chan][ISA_DMA_COUNT]); |
122 | outb(length >> 8, isa_dma_port[chan][ISA_DMA_COUNT]); | |
1da177e4 LT |
123 | |
124 | if (dma->dma_mode & DMA_AUTOINIT) | |
125 | mode |= ISA_DMA_AUTOINIT; | |
126 | ||
1df81302 | 127 | outb(mode, isa_dma_port[chan][ISA_DMA_MODE]); |
1da177e4 LT |
128 | dma->invalid = 0; |
129 | } | |
1df81302 | 130 | outb(chan & 3, isa_dma_port[chan][ISA_DMA_MASK]); |
1da177e4 LT |
131 | } |
132 | ||
1df81302 | 133 | static void isa_disable_dma(unsigned int chan, dma_t *dma) |
1da177e4 | 134 | { |
1df81302 | 135 | outb(chan | 4, isa_dma_port[chan][ISA_DMA_MASK]); |
1da177e4 LT |
136 | } |
137 | ||
138 | static struct dma_ops isa_dma_ops = { | |
139 | .type = "ISA", | |
140 | .enable = isa_enable_dma, | |
141 | .disable = isa_disable_dma, | |
142 | .residue = isa_get_dma_residue, | |
143 | }; | |
144 | ||
3170a5e8 AB |
145 | static struct resource dma_resources[] = { { |
146 | .name = "dma1", | |
147 | .start = 0x0000, | |
148 | .end = 0x000f | |
149 | }, { | |
150 | .name = "dma low page", | |
151 | .start = 0x0080, | |
152 | .end = 0x008f | |
153 | }, { | |
154 | .name = "dma2", | |
155 | .start = 0x00c0, | |
156 | .end = 0x00df | |
157 | }, { | |
158 | .name = "dma high page", | |
159 | .start = 0x0480, | |
160 | .end = 0x048f | |
161 | } }; | |
1da177e4 | 162 | |
2f757f2a RK |
163 | static dma_t isa_dma[8]; |
164 | ||
165 | /* | |
166 | * ISA DMA always starts at channel 0 | |
167 | */ | |
168 | void __init isa_init_dma(void) | |
1da177e4 LT |
169 | { |
170 | /* | |
171 | * Try to autodetect presence of an ISA DMA controller. | |
172 | * We do some minimal initialisation, and check that | |
173 | * channel 0's DMA address registers are writeable. | |
174 | */ | |
175 | outb(0xff, 0x0d); | |
176 | outb(0xff, 0xda); | |
177 | ||
178 | /* | |
179 | * Write high and low address, and then read them back | |
180 | * in the same order. | |
181 | */ | |
182 | outb(0x55, 0x00); | |
183 | outb(0xaa, 0x00); | |
184 | ||
185 | if (inb(0) == 0x55 && inb(0) == 0xaa) { | |
2f757f2a | 186 | unsigned int chan, i; |
1da177e4 | 187 | |
1df81302 | 188 | for (chan = 0; chan < 8; chan++) { |
2f757f2a | 189 | isa_dma[chan].d_ops = &isa_dma_ops; |
1df81302 | 190 | isa_disable_dma(chan, NULL); |
1da177e4 LT |
191 | } |
192 | ||
193 | outb(0x40, 0x0b); | |
194 | outb(0x41, 0x0b); | |
195 | outb(0x42, 0x0b); | |
196 | outb(0x43, 0x0b); | |
197 | ||
198 | outb(0xc0, 0xd6); | |
199 | outb(0x41, 0xd6); | |
200 | outb(0x42, 0xd6); | |
201 | outb(0x43, 0xd6); | |
202 | ||
203 | outb(0, 0xd4); | |
204 | ||
205 | outb(0x10, 0x08); | |
206 | outb(0x10, 0xd0); | |
207 | ||
208 | /* | |
209 | * Is this correct? According to my documentation, it | |
210 | * doesn't appear to be. It should be: | |
211 | * outb(0x3f, 0x40b); outb(0x3f, 0x4d6); | |
212 | */ | |
213 | outb(0x30, 0x40b); | |
214 | outb(0x31, 0x40b); | |
215 | outb(0x32, 0x40b); | |
216 | outb(0x33, 0x40b); | |
217 | outb(0x31, 0x4d6); | |
218 | outb(0x32, 0x4d6); | |
219 | outb(0x33, 0x4d6); | |
220 | ||
221 | request_dma(DMA_ISA_CASCADE, "cascade"); | |
222 | ||
df1a2903 | 223 | for (i = 0; i < ARRAY_SIZE(dma_resources); i++) |
1da177e4 | 224 | request_resource(&ioport_resource, dma_resources + i); |
2f757f2a RK |
225 | |
226 | for (chan = 0; chan < 8; chan++) { | |
227 | int ret = isa_dma_add(chan, &isa_dma[chan]); | |
228 | if (ret) | |
229 | printk(KERN_ERR "ISADMA%u: unable to register: %d\n", | |
230 | chan, ret); | |
231 | } | |
1da177e4 LT |
232 | } |
233 | } |