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Commit | Line | Data |
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d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
1da177e4 LT |
2 | /* |
3 | * linux/arch/arm/kernel/entry-armv.S | |
4 | * | |
5 | * Copyright (C) 1996,1997,1998 Russell King. | |
6 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) | |
afeb90ca | 7 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
1da177e4 | 8 | * |
1da177e4 LT |
9 | * Low-level vector interface routines |
10 | * | |
70b6f2b4 NP |
11 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction |
12 | * that causes it to save wrong values... Be aware! | |
1da177e4 | 13 | */ |
1da177e4 | 14 | |
9b9cf81a PG |
15 | #include <linux/init.h> |
16 | ||
6f6f6a70 | 17 | #include <asm/assembler.h> |
f09b9979 | 18 | #include <asm/memory.h> |
753790e7 RK |
19 | #include <asm/glue-df.h> |
20 | #include <asm/glue-pf.h> | |
1da177e4 | 21 | #include <asm/vfpmacros.h> |
4c301f9b | 22 | #ifndef CONFIG_GENERIC_IRQ_MULTI_HANDLER |
a09e64fb | 23 | #include <mach/entry-macro.S> |
243c8654 | 24 | #endif |
d6551e88 | 25 | #include <asm/thread_notify.h> |
c4c5716e | 26 | #include <asm/unwind.h> |
cc20d429 | 27 | #include <asm/unistd.h> |
f159f4ed | 28 | #include <asm/tls.h> |
9f97da78 | 29 | #include <asm/system_info.h> |
1da177e4 LT |
30 | |
31 | #include "entry-header.S" | |
cd544ce7 | 32 | #include <asm/entry-macro-multi.S> |
a0266c21 | 33 | #include <asm/probes.h> |
1da177e4 | 34 | |
187a51ad | 35 | /* |
d9600c99 | 36 | * Interrupt handling. |
187a51ad RK |
37 | */ |
38 | .macro irq_handler | |
4c301f9b | 39 | #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER |
d9600c99 | 40 | ldr r1, =handle_arch_irq |
52108641 | 41 | mov r0, sp |
14327c66 | 42 | badr lr, 9997f |
abeb24ae MZ |
43 | ldr pc, [r1] |
44 | #else | |
cd544ce7 | 45 | arch_irq_handler_default |
abeb24ae | 46 | #endif |
f00ec48f | 47 | 9997: |
187a51ad RK |
48 | .endm |
49 | ||
ac8b9c1c | 50 | .macro pabt_helper |
8dfe7ac9 | 51 | @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 |
ac8b9c1c | 52 | #ifdef MULTI_PABORT |
0402bece | 53 | ldr ip, .LCprocfns |
ac8b9c1c | 54 | mov lr, pc |
0402bece | 55 | ldr pc, [ip, #PROCESSOR_PABT_FUNC] |
ac8b9c1c RK |
56 | #else |
57 | bl CPU_PABORT_HANDLER | |
58 | #endif | |
59 | .endm | |
60 | ||
61 | .macro dabt_helper | |
62 | ||
63 | @ | |
64 | @ Call the processor-specific abort handler: | |
65 | @ | |
da740472 | 66 | @ r2 - pt_regs |
3e287bec RK |
67 | @ r4 - aborted context pc |
68 | @ r5 - aborted context psr | |
ac8b9c1c RK |
69 | @ |
70 | @ The abort handler must return the aborted address in r0, and | |
71 | @ the fault status register in r1. r9 must be preserved. | |
72 | @ | |
73 | #ifdef MULTI_DABORT | |
0402bece | 74 | ldr ip, .LCprocfns |
ac8b9c1c | 75 | mov lr, pc |
0402bece | 76 | ldr pc, [ip, #PROCESSOR_DABT_FUNC] |
ac8b9c1c RK |
77 | #else |
78 | bl CPU_DABORT_HANDLER | |
79 | #endif | |
80 | .endm | |
81 | ||
c6089061 | 82 | .section .entry.text,"ax",%progbits |
785d3cd2 | 83 | |
1da177e4 LT |
84 | /* |
85 | * Invalid mode handlers | |
86 | */ | |
ccea7a19 | 87 | .macro inv_entry, reason |
5745eef6 | 88 | sub sp, sp, #PT_REGS_SIZE |
b86040a5 CM |
89 | ARM( stmib sp, {r1 - lr} ) |
90 | THUMB( stmia sp, {r0 - r12} ) | |
91 | THUMB( str sp, [sp, #S_SP] ) | |
92 | THUMB( str lr, [sp, #S_LR] ) | |
1da177e4 LT |
93 | mov r1, #\reason |
94 | .endm | |
95 | ||
96 | __pabt_invalid: | |
ccea7a19 RK |
97 | inv_entry BAD_PREFETCH |
98 | b common_invalid | |
93ed3970 | 99 | ENDPROC(__pabt_invalid) |
1da177e4 LT |
100 | |
101 | __dabt_invalid: | |
ccea7a19 RK |
102 | inv_entry BAD_DATA |
103 | b common_invalid | |
93ed3970 | 104 | ENDPROC(__dabt_invalid) |
1da177e4 LT |
105 | |
106 | __irq_invalid: | |
ccea7a19 RK |
107 | inv_entry BAD_IRQ |
108 | b common_invalid | |
93ed3970 | 109 | ENDPROC(__irq_invalid) |
1da177e4 LT |
110 | |
111 | __und_invalid: | |
ccea7a19 RK |
112 | inv_entry BAD_UNDEFINSTR |
113 | ||
114 | @ | |
115 | @ XXX fall through to common_invalid | |
116 | @ | |
117 | ||
118 | @ | |
119 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) | |
120 | @ | |
121 | common_invalid: | |
122 | zero_fp | |
123 | ||
124 | ldmia r0, {r4 - r6} | |
125 | add r0, sp, #S_PC @ here for interlock avoidance | |
126 | mov r7, #-1 @ "" "" "" "" | |
127 | str r4, [sp] @ save preserved r0 | |
128 | stmia r0, {r5 - r7} @ lr_<exception>, | |
129 | @ cpsr_<exception>, "old_r0" | |
1da177e4 | 130 | |
1da177e4 | 131 | mov r0, sp |
1da177e4 | 132 | b bad_mode |
93ed3970 | 133 | ENDPROC(__und_invalid) |
1da177e4 LT |
134 | |
135 | /* | |
136 | * SVC mode handlers | |
137 | */ | |
2dede2d8 NP |
138 | |
139 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | |
140 | #define SPFIX(code...) code | |
141 | #else | |
142 | #define SPFIX(code...) | |
143 | #endif | |
144 | ||
2190fed6 | 145 | .macro svc_entry, stack_hole=0, trace=1, uaccess=1 |
c4c5716e CM |
146 | UNWIND(.fnstart ) |
147 | UNWIND(.save {r0 - pc} ) | |
e6a9dc61 | 148 | sub sp, sp, #(SVC_REGS_SIZE + \stack_hole - 4) |
b86040a5 CM |
149 | #ifdef CONFIG_THUMB2_KERNEL |
150 | SPFIX( str r0, [sp] ) @ temporarily saved | |
151 | SPFIX( mov r0, sp ) | |
152 | SPFIX( tst r0, #4 ) @ test original stack alignment | |
153 | SPFIX( ldr r0, [sp] ) @ restored | |
154 | #else | |
2dede2d8 | 155 | SPFIX( tst sp, #4 ) |
b86040a5 CM |
156 | #endif |
157 | SPFIX( subeq sp, sp, #4 ) | |
158 | stmia sp, {r1 - r12} | |
ccea7a19 | 159 | |
b059bdc3 RK |
160 | ldmia r0, {r3 - r5} |
161 | add r7, sp, #S_SP - 4 @ here for interlock avoidance | |
162 | mov r6, #-1 @ "" "" "" "" | |
e6a9dc61 | 163 | add r2, sp, #(SVC_REGS_SIZE + \stack_hole - 4) |
b059bdc3 RK |
164 | SPFIX( addeq r2, r2, #4 ) |
165 | str r3, [sp, #-4]! @ save the "real" r0 copied | |
ccea7a19 RK |
166 | @ from the exception stack |
167 | ||
b059bdc3 | 168 | mov r3, lr |
1da177e4 LT |
169 | |
170 | @ | |
171 | @ We are now ready to fill in the remaining blanks on the stack: | |
172 | @ | |
b059bdc3 RK |
173 | @ r2 - sp_svc |
174 | @ r3 - lr_svc | |
175 | @ r4 - lr_<exception>, already fixed up for correct return/restart | |
176 | @ r5 - spsr_<exception> | |
177 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) | |
1da177e4 | 178 | @ |
b059bdc3 | 179 | stmia r7, {r2 - r6} |
1da177e4 | 180 | |
e6978e4b RK |
181 | get_thread_info tsk |
182 | ldr r0, [tsk, #TI_ADDR_LIMIT] | |
183 | mov r1, #TASK_SIZE | |
184 | str r1, [tsk, #TI_ADDR_LIMIT] | |
185 | str r0, [sp, #SVC_ADDR_LIMIT] | |
186 | ||
2190fed6 RK |
187 | uaccess_save r0 |
188 | .if \uaccess | |
189 | uaccess_disable r0 | |
190 | .endif | |
191 | ||
c0e7f7ee | 192 | .if \trace |
02fe2845 RK |
193 | #ifdef CONFIG_TRACE_IRQFLAGS |
194 | bl trace_hardirqs_off | |
195 | #endif | |
c0e7f7ee | 196 | .endif |
f2741b78 | 197 | .endm |
1da177e4 | 198 | |
f2741b78 RK |
199 | .align 5 |
200 | __dabt_svc: | |
2190fed6 | 201 | svc_entry uaccess=0 |
1da177e4 | 202 | mov r2, sp |
da740472 | 203 | dabt_helper |
e16b31bf | 204 | THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR |
b059bdc3 | 205 | svc_exit r5 @ return from exception |
c4c5716e | 206 | UNWIND(.fnend ) |
93ed3970 | 207 | ENDPROC(__dabt_svc) |
1da177e4 LT |
208 | |
209 | .align 5 | |
210 | __irq_svc: | |
ccea7a19 | 211 | svc_entry |
187a51ad | 212 | irq_handler |
1613cc11 | 213 | |
1da177e4 | 214 | #ifdef CONFIG_PREEMPT |
1613cc11 | 215 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count |
706fdd9f | 216 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
28fab1a2 RK |
217 | teq r8, #0 @ if preempt count != 0 |
218 | movne r0, #0 @ force flags to 0 | |
1da177e4 LT |
219 | tst r0, #_TIF_NEED_RESCHED |
220 | blne svc_preempt | |
1da177e4 | 221 | #endif |
30891c90 | 222 | |
9b56febe | 223 | svc_exit r5, irq = 1 @ return from exception |
c4c5716e | 224 | UNWIND(.fnend ) |
93ed3970 | 225 | ENDPROC(__irq_svc) |
1da177e4 LT |
226 | |
227 | .ltorg | |
228 | ||
229 | #ifdef CONFIG_PREEMPT | |
230 | svc_preempt: | |
28fab1a2 | 231 | mov r8, lr |
1da177e4 | 232 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
706fdd9f | 233 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
1da177e4 | 234 | tst r0, #_TIF_NEED_RESCHED |
6ebbf2ce | 235 | reteq r8 @ go again |
1da177e4 LT |
236 | b 1b |
237 | #endif | |
238 | ||
15ac49b6 RK |
239 | __und_fault: |
240 | @ Correct the PC such that it is pointing at the instruction | |
241 | @ which caused the fault. If the faulting instruction was ARM | |
242 | @ the PC will be pointing at the next instruction, and have to | |
243 | @ subtract 4. Otherwise, it is Thumb, and the PC will be | |
244 | @ pointing at the second half of the Thumb instruction. We | |
245 | @ have to subtract 2. | |
246 | ldr r2, [r0, #S_PC] | |
247 | sub r2, r2, r1 | |
248 | str r2, [r0, #S_PC] | |
249 | b do_undefinstr | |
250 | ENDPROC(__und_fault) | |
251 | ||
1da177e4 LT |
252 | .align 5 |
253 | __und_svc: | |
d30a0c8b NP |
254 | #ifdef CONFIG_KPROBES |
255 | @ If a kprobe is about to simulate a "stmdb sp..." instruction, | |
256 | @ it obviously needs free stack space which then will belong to | |
257 | @ the saved context. | |
a0266c21 | 258 | svc_entry MAX_STACK_SIZE |
d30a0c8b | 259 | #else |
ccea7a19 | 260 | svc_entry |
d30a0c8b | 261 | #endif |
1da177e4 LT |
262 | @ |
263 | @ call emulation code, which returns using r9 if it has emulated | |
264 | @ the instruction, or the more conventional lr if we are to treat | |
265 | @ this as a real undefined instruction | |
266 | @ | |
267 | @ r0 - instruction | |
268 | @ | |
15ac49b6 | 269 | #ifndef CONFIG_THUMB2_KERNEL |
b059bdc3 | 270 | ldr r0, [r4, #-4] |
83e686ea | 271 | #else |
15ac49b6 | 272 | mov r1, #2 |
b059bdc3 | 273 | ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 |
85519189 | 274 | cmp r0, #0xe800 @ 32-bit instruction if xx >= 0 |
15ac49b6 RK |
275 | blo __und_svc_fault |
276 | ldrh r9, [r4] @ bottom 16 bits | |
277 | add r4, r4, #2 | |
278 | str r4, [sp, #S_PC] | |
279 | orr r0, r9, r0, lsl #16 | |
83e686ea | 280 | #endif |
14327c66 | 281 | badr r9, __und_svc_finish |
b059bdc3 | 282 | mov r2, r4 |
1da177e4 LT |
283 | bl call_fpe |
284 | ||
15ac49b6 RK |
285 | mov r1, #4 @ PC correction to apply |
286 | __und_svc_fault: | |
1da177e4 | 287 | mov r0, sp @ struct pt_regs *regs |
15ac49b6 | 288 | bl __und_fault |
1da177e4 | 289 | |
15ac49b6 | 290 | __und_svc_finish: |
87eed3c7 | 291 | get_thread_info tsk |
b059bdc3 RK |
292 | ldr r5, [sp, #S_PSR] @ Get SVC cpsr |
293 | svc_exit r5 @ return from exception | |
c4c5716e | 294 | UNWIND(.fnend ) |
93ed3970 | 295 | ENDPROC(__und_svc) |
1da177e4 LT |
296 | |
297 | .align 5 | |
298 | __pabt_svc: | |
ccea7a19 | 299 | svc_entry |
4fb28474 | 300 | mov r2, sp @ regs |
8dfe7ac9 | 301 | pabt_helper |
b059bdc3 | 302 | svc_exit r5 @ return from exception |
c4c5716e | 303 | UNWIND(.fnend ) |
93ed3970 | 304 | ENDPROC(__pabt_svc) |
1da177e4 | 305 | |
c0e7f7ee DT |
306 | .align 5 |
307 | __fiq_svc: | |
308 | svc_entry trace=0 | |
309 | mov r0, sp @ struct pt_regs *regs | |
310 | bl handle_fiq_as_nmi | |
311 | svc_exit_via_fiq | |
312 | UNWIND(.fnend ) | |
313 | ENDPROC(__fiq_svc) | |
314 | ||
1da177e4 | 315 | .align 5 |
49f680ea RK |
316 | .LCcralign: |
317 | .word cr_alignment | |
48d7927b | 318 | #ifdef MULTI_DABORT |
1da177e4 LT |
319 | .LCprocfns: |
320 | .word processor | |
321 | #endif | |
322 | .LCfp: | |
323 | .word fp_enter | |
1da177e4 | 324 | |
c0e7f7ee DT |
325 | /* |
326 | * Abort mode handlers | |
327 | */ | |
328 | ||
329 | @ | |
330 | @ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode | |
331 | @ and reuses the same macros. However in abort mode we must also | |
332 | @ save/restore lr_abt and spsr_abt to make nested aborts safe. | |
333 | @ | |
334 | .align 5 | |
335 | __fiq_abt: | |
336 | svc_entry trace=0 | |
337 | ||
338 | ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) | |
339 | THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) | |
340 | THUMB( msr cpsr_c, r0 ) | |
341 | mov r1, lr @ Save lr_abt | |
342 | mrs r2, spsr @ Save spsr_abt, abort is now safe | |
343 | ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) | |
344 | THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) | |
345 | THUMB( msr cpsr_c, r0 ) | |
346 | stmfd sp!, {r1 - r2} | |
347 | ||
348 | add r0, sp, #8 @ struct pt_regs *regs | |
349 | bl handle_fiq_as_nmi | |
350 | ||
351 | ldmfd sp!, {r1 - r2} | |
352 | ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) | |
353 | THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) | |
354 | THUMB( msr cpsr_c, r0 ) | |
355 | mov lr, r1 @ Restore lr_abt, abort is unsafe | |
356 | msr spsr_cxsf, r2 @ Restore spsr_abt | |
357 | ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) | |
358 | THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) | |
359 | THUMB( msr cpsr_c, r0 ) | |
360 | ||
361 | svc_exit_via_fiq | |
362 | UNWIND(.fnend ) | |
363 | ENDPROC(__fiq_abt) | |
364 | ||
1da177e4 LT |
365 | /* |
366 | * User mode handlers | |
2dede2d8 | 367 | * |
5745eef6 | 368 | * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE |
1da177e4 | 369 | */ |
2dede2d8 | 370 | |
5745eef6 | 371 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (PT_REGS_SIZE & 7) |
2dede2d8 NP |
372 | #error "sizeof(struct pt_regs) must be a multiple of 8" |
373 | #endif | |
374 | ||
2190fed6 | 375 | .macro usr_entry, trace=1, uaccess=1 |
c4c5716e CM |
376 | UNWIND(.fnstart ) |
377 | UNWIND(.cantunwind ) @ don't unwind the user space | |
5745eef6 | 378 | sub sp, sp, #PT_REGS_SIZE |
b86040a5 CM |
379 | ARM( stmib sp, {r1 - r12} ) |
380 | THUMB( stmia sp, {r0 - r12} ) | |
ccea7a19 | 381 | |
195b58ad RK |
382 | ATRAP( mrc p15, 0, r7, c1, c0, 0) |
383 | ATRAP( ldr r8, .LCcralign) | |
384 | ||
b059bdc3 | 385 | ldmia r0, {r3 - r5} |
ccea7a19 | 386 | add r0, sp, #S_PC @ here for interlock avoidance |
b059bdc3 | 387 | mov r6, #-1 @ "" "" "" "" |
ccea7a19 | 388 | |
b059bdc3 | 389 | str r3, [sp] @ save the "real" r0 copied |
ccea7a19 | 390 | @ from the exception stack |
1da177e4 | 391 | |
195b58ad RK |
392 | ATRAP( ldr r8, [r8, #0]) |
393 | ||
1da177e4 LT |
394 | @ |
395 | @ We are now ready to fill in the remaining blanks on the stack: | |
396 | @ | |
b059bdc3 RK |
397 | @ r4 - lr_<exception>, already fixed up for correct return/restart |
398 | @ r5 - spsr_<exception> | |
399 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) | |
1da177e4 LT |
400 | @ |
401 | @ Also, separately save sp_usr and lr_usr | |
402 | @ | |
b059bdc3 | 403 | stmia r0, {r4 - r6} |
b86040a5 CM |
404 | ARM( stmdb r0, {sp, lr}^ ) |
405 | THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) | |
1da177e4 | 406 | |
2190fed6 RK |
407 | .if \uaccess |
408 | uaccess_disable ip | |
409 | .endif | |
410 | ||
1da177e4 | 411 | @ Enable the alignment trap while in kernel mode |
195b58ad RK |
412 | ATRAP( teq r8, r7) |
413 | ATRAP( mcrne p15, 0, r8, c1, c0, 0) | |
1da177e4 LT |
414 | |
415 | @ | |
416 | @ Clear FP to mark the first stack frame | |
417 | @ | |
418 | zero_fp | |
f2741b78 | 419 | |
c0e7f7ee | 420 | .if \trace |
11b8b25c | 421 | #ifdef CONFIG_TRACE_IRQFLAGS |
f2741b78 RK |
422 | bl trace_hardirqs_off |
423 | #endif | |
b0088480 | 424 | ct_user_exit save = 0 |
c0e7f7ee | 425 | .endif |
1da177e4 LT |
426 | .endm |
427 | ||
b49c0f24 | 428 | .macro kuser_cmpxchg_check |
db695c05 | 429 | #if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) |
b49c0f24 NP |
430 | #ifndef CONFIG_MMU |
431 | #warning "NPTL on non MMU needs fixing" | |
432 | #else | |
433 | @ Make sure our user space atomic helper is restarted | |
434 | @ if it was interrupted in a critical region. Here we | |
435 | @ perform a quick test inline since it should be false | |
436 | @ 99.9999% of the time. The rest is done out of line. | |
b059bdc3 | 437 | cmp r4, #TASK_SIZE |
40fb79c8 | 438 | blhs kuser_cmpxchg64_fixup |
b49c0f24 NP |
439 | #endif |
440 | #endif | |
441 | .endm | |
442 | ||
1da177e4 LT |
443 | .align 5 |
444 | __dabt_usr: | |
2190fed6 | 445 | usr_entry uaccess=0 |
b49c0f24 | 446 | kuser_cmpxchg_check |
1da177e4 | 447 | mov r2, sp |
da740472 RK |
448 | dabt_helper |
449 | b ret_from_exception | |
c4c5716e | 450 | UNWIND(.fnend ) |
93ed3970 | 451 | ENDPROC(__dabt_usr) |
1da177e4 LT |
452 | |
453 | .align 5 | |
454 | __irq_usr: | |
ccea7a19 | 455 | usr_entry |
bc089602 | 456 | kuser_cmpxchg_check |
187a51ad | 457 | irq_handler |
1613cc11 | 458 | get_thread_info tsk |
1da177e4 | 459 | mov why, #0 |
9fc2552a | 460 | b ret_to_user_from_irq |
c4c5716e | 461 | UNWIND(.fnend ) |
93ed3970 | 462 | ENDPROC(__irq_usr) |
1da177e4 LT |
463 | |
464 | .ltorg | |
465 | ||
466 | .align 5 | |
467 | __und_usr: | |
2190fed6 | 468 | usr_entry uaccess=0 |
bc089602 | 469 | |
b059bdc3 RK |
470 | mov r2, r4 |
471 | mov r3, r5 | |
1da177e4 | 472 | |
15ac49b6 RK |
473 | @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the |
474 | @ faulting instruction depending on Thumb mode. | |
475 | @ r3 = regs->ARM_cpsr | |
1da177e4 | 476 | @ |
15ac49b6 RK |
477 | @ The emulation code returns using r9 if it has emulated the |
478 | @ instruction, or the more conventional lr if we are to treat | |
479 | @ this as a real undefined instruction | |
1da177e4 | 480 | @ |
14327c66 | 481 | badr r9, ret_from_exception |
15ac49b6 | 482 | |
1417a6b8 CM |
483 | @ IRQs must be enabled before attempting to read the instruction from |
484 | @ user space since that could cause a page/translation fault if the | |
485 | @ page table was modified by another CPU. | |
486 | enable_irq | |
487 | ||
cb170a45 | 488 | tst r3, #PSR_T_BIT @ Thumb mode? |
15ac49b6 RK |
489 | bne __und_usr_thumb |
490 | sub r4, r2, #4 @ ARM instr at LR - 4 | |
491 | 1: ldrt r0, [r4] | |
457c2403 BD |
492 | ARM_BE8(rev r0, r0) @ little endian instruction |
493 | ||
2190fed6 RK |
494 | uaccess_disable ip |
495 | ||
15ac49b6 RK |
496 | @ r0 = 32-bit ARM instruction which caused the exception |
497 | @ r2 = PC value for the following instruction (:= regs->ARM_pc) | |
498 | @ r4 = PC value for the faulting instruction | |
499 | @ lr = 32-bit undefined instruction function | |
14327c66 | 500 | badr lr, __und_usr_fault_32 |
15ac49b6 RK |
501 | b call_fpe |
502 | ||
503 | __und_usr_thumb: | |
cb170a45 | 504 | @ Thumb instruction |
15ac49b6 | 505 | sub r4, r2, #2 @ First half of thumb instr at LR - 2 |
ef4c5368 DM |
506 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 |
507 | /* | |
508 | * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms | |
509 | * can never be supported in a single kernel, this code is not applicable at | |
510 | * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be | |
511 | * made about .arch directives. | |
512 | */ | |
513 | #if __LINUX_ARM_ARCH__ < 7 | |
514 | /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ | |
515 | #define NEED_CPU_ARCHITECTURE | |
516 | ldr r5, .LCcpu_architecture | |
517 | ldr r5, [r5] | |
518 | cmp r5, #CPU_ARCH_ARMv7 | |
15ac49b6 | 519 | blo __und_usr_fault_16 @ 16bit undefined instruction |
ef4c5368 DM |
520 | /* |
521 | * The following code won't get run unless the running CPU really is v7, so | |
522 | * coding round the lack of ldrht on older arches is pointless. Temporarily | |
523 | * override the assembler target arch with the minimum required instead: | |
524 | */ | |
525 | .arch armv6t2 | |
526 | #endif | |
15ac49b6 | 527 | 2: ldrht r5, [r4] |
f8fe23ec | 528 | ARM_BE8(rev16 r5, r5) @ little endian instruction |
85519189 | 529 | cmp r5, #0xe800 @ 32bit instruction if xx != 0 |
2190fed6 | 530 | blo __und_usr_fault_16_pan @ 16bit undefined instruction |
15ac49b6 | 531 | 3: ldrht r0, [r2] |
f8fe23ec | 532 | ARM_BE8(rev16 r0, r0) @ little endian instruction |
2190fed6 | 533 | uaccess_disable ip |
cb170a45 | 534 | add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 |
15ac49b6 | 535 | str r2, [sp, #S_PC] @ it's a 2x16bit instr, update |
cb170a45 | 536 | orr r0, r0, r5, lsl #16 |
14327c66 | 537 | badr lr, __und_usr_fault_32 |
15ac49b6 RK |
538 | @ r0 = the two 16-bit Thumb instructions which caused the exception |
539 | @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) | |
540 | @ r4 = PC value for the first 16-bit Thumb instruction | |
541 | @ lr = 32bit undefined instruction function | |
ef4c5368 DM |
542 | |
543 | #if __LINUX_ARM_ARCH__ < 7 | |
544 | /* If the target arch was overridden, change it back: */ | |
545 | #ifdef CONFIG_CPU_32v6K | |
546 | .arch armv6k | |
cb170a45 | 547 | #else |
ef4c5368 DM |
548 | .arch armv6 |
549 | #endif | |
550 | #endif /* __LINUX_ARM_ARCH__ < 7 */ | |
551 | #else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ | |
15ac49b6 | 552 | b __und_usr_fault_16 |
cb170a45 | 553 | #endif |
15ac49b6 | 554 | UNWIND(.fnend) |
93ed3970 | 555 | ENDPROC(__und_usr) |
cb170a45 | 556 | |
1da177e4 | 557 | /* |
15ac49b6 | 558 | * The out of line fixup for the ldrt instructions above. |
1da177e4 | 559 | */ |
c4a84ae3 | 560 | .pushsection .text.fixup, "ax" |
667d1b48 | 561 | .align 2 |
3780f7ab | 562 | 4: str r4, [sp, #S_PC] @ retry current instruction |
6ebbf2ce | 563 | ret r9 |
4260415f RK |
564 | .popsection |
565 | .pushsection __ex_table,"a" | |
cb170a45 | 566 | .long 1b, 4b |
c89cefed | 567 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 |
cb170a45 PB |
568 | .long 2b, 4b |
569 | .long 3b, 4b | |
570 | #endif | |
4260415f | 571 | .popsection |
1da177e4 LT |
572 | |
573 | /* | |
574 | * Check whether the instruction is a co-processor instruction. | |
575 | * If yes, we need to call the relevant co-processor handler. | |
576 | * | |
577 | * Note that we don't do a full check here for the co-processor | |
578 | * instructions; all instructions with bit 27 set are well | |
579 | * defined. The only instructions that should fault are the | |
580 | * co-processor instructions. However, we have to watch out | |
581 | * for the ARM6/ARM7 SWI bug. | |
582 | * | |
b5872db4 CM |
583 | * NEON is a special case that has to be handled here. Not all |
584 | * NEON instructions are co-processor instructions, so we have | |
585 | * to make a special case of checking for them. Plus, there's | |
586 | * five groups of them, so we have a table of mask/opcode pairs | |
587 | * to check against, and if any match then we branch off into the | |
588 | * NEON handler code. | |
589 | * | |
1da177e4 | 590 | * Emulators may wish to make use of the following registers: |
15ac49b6 RK |
591 | * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) |
592 | * r2 = PC value to resume execution after successful emulation | |
db6ccbb6 | 593 | * r9 = normal "successful" return address |
15ac49b6 | 594 | * r10 = this threads thread_info structure |
db6ccbb6 | 595 | * lr = unrecognised instruction return address |
1417a6b8 | 596 | * IRQs enabled, FIQs enabled. |
1da177e4 | 597 | */ |
cb170a45 PB |
598 | @ |
599 | @ Fall-through from Thumb-2 __und_usr | |
600 | @ | |
601 | #ifdef CONFIG_NEON | |
d3f79584 | 602 | get_thread_info r10 @ get current thread |
cb170a45 PB |
603 | adr r6, .LCneon_thumb_opcodes |
604 | b 2f | |
605 | #endif | |
1da177e4 | 606 | call_fpe: |
d3f79584 | 607 | get_thread_info r10 @ get current thread |
b5872db4 | 608 | #ifdef CONFIG_NEON |
cb170a45 | 609 | adr r6, .LCneon_arm_opcodes |
d3f79584 | 610 | 2: ldr r5, [r6], #4 @ mask value |
b5872db4 | 611 | ldr r7, [r6], #4 @ opcode bits matching in mask |
d3f79584 RK |
612 | cmp r5, #0 @ end mask? |
613 | beq 1f | |
614 | and r8, r0, r5 | |
b5872db4 CM |
615 | cmp r8, r7 @ NEON instruction? |
616 | bne 2b | |
b5872db4 CM |
617 | mov r7, #1 |
618 | strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used | |
619 | strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used | |
620 | b do_vfp @ let VFP handler handle this | |
621 | 1: | |
622 | #endif | |
1da177e4 | 623 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 |
cb170a45 | 624 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 |
6ebbf2ce | 625 | reteq lr |
1da177e4 | 626 | and r8, r0, #0x00000f00 @ mask out CP number |
b86040a5 | 627 | THUMB( lsr r8, r8, #8 ) |
1da177e4 LT |
628 | mov r7, #1 |
629 | add r6, r10, #TI_USED_CP | |
b86040a5 CM |
630 | ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] |
631 | THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] | |
1da177e4 LT |
632 | #ifdef CONFIG_IWMMXT |
633 | @ Test if we need to give access to iWMMXt coprocessors | |
634 | ldr r5, [r10, #TI_FLAGS] | |
635 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only | |
e44fc388 | 636 | movscs r7, r5, lsr #(TIF_USING_IWMMXT + 1) |
1da177e4 LT |
637 | bcs iwmmxt_task_enable |
638 | #endif | |
b86040a5 CM |
639 | ARM( add pc, pc, r8, lsr #6 ) |
640 | THUMB( lsl r8, r8, #2 ) | |
641 | THUMB( add pc, r8 ) | |
642 | nop | |
643 | ||
6ebbf2ce | 644 | ret.w lr @ CP#0 |
b86040a5 CM |
645 | W(b) do_fpe @ CP#1 (FPE) |
646 | W(b) do_fpe @ CP#2 (FPE) | |
6ebbf2ce | 647 | ret.w lr @ CP#3 |
c17fad11 LB |
648 | #ifdef CONFIG_CRUNCH |
649 | b crunch_task_enable @ CP#4 (MaverickCrunch) | |
650 | b crunch_task_enable @ CP#5 (MaverickCrunch) | |
651 | b crunch_task_enable @ CP#6 (MaverickCrunch) | |
652 | #else | |
6ebbf2ce RK |
653 | ret.w lr @ CP#4 |
654 | ret.w lr @ CP#5 | |
655 | ret.w lr @ CP#6 | |
c17fad11 | 656 | #endif |
6ebbf2ce RK |
657 | ret.w lr @ CP#7 |
658 | ret.w lr @ CP#8 | |
659 | ret.w lr @ CP#9 | |
1da177e4 | 660 | #ifdef CONFIG_VFP |
b86040a5 CM |
661 | W(b) do_vfp @ CP#10 (VFP) |
662 | W(b) do_vfp @ CP#11 (VFP) | |
1da177e4 | 663 | #else |
6ebbf2ce RK |
664 | ret.w lr @ CP#10 (VFP) |
665 | ret.w lr @ CP#11 (VFP) | |
1da177e4 | 666 | #endif |
6ebbf2ce RK |
667 | ret.w lr @ CP#12 |
668 | ret.w lr @ CP#13 | |
669 | ret.w lr @ CP#14 (Debug) | |
670 | ret.w lr @ CP#15 (Control) | |
1da177e4 | 671 | |
ef4c5368 DM |
672 | #ifdef NEED_CPU_ARCHITECTURE |
673 | .align 2 | |
674 | .LCcpu_architecture: | |
675 | .word __cpu_architecture | |
676 | #endif | |
677 | ||
b5872db4 CM |
678 | #ifdef CONFIG_NEON |
679 | .align 6 | |
680 | ||
cb170a45 | 681 | .LCneon_arm_opcodes: |
b5872db4 CM |
682 | .word 0xfe000000 @ mask |
683 | .word 0xf2000000 @ opcode | |
684 | ||
685 | .word 0xff100000 @ mask | |
686 | .word 0xf4000000 @ opcode | |
687 | ||
cb170a45 PB |
688 | .word 0x00000000 @ mask |
689 | .word 0x00000000 @ opcode | |
690 | ||
691 | .LCneon_thumb_opcodes: | |
692 | .word 0xef000000 @ mask | |
693 | .word 0xef000000 @ opcode | |
694 | ||
695 | .word 0xff100000 @ mask | |
696 | .word 0xf9000000 @ opcode | |
697 | ||
b5872db4 CM |
698 | .word 0x00000000 @ mask |
699 | .word 0x00000000 @ opcode | |
700 | #endif | |
701 | ||
1da177e4 LT |
702 | do_fpe: |
703 | ldr r4, .LCfp | |
704 | add r10, r10, #TI_FPSTATE @ r10 = workspace | |
705 | ldr pc, [r4] @ Call FP module USR entry point | |
706 | ||
707 | /* | |
708 | * The FP module is called with these registers set: | |
709 | * r0 = instruction | |
710 | * r2 = PC+4 | |
711 | * r9 = normal "successful" return address | |
712 | * r10 = FP workspace | |
713 | * lr = unrecognised FP instruction return address | |
714 | */ | |
715 | ||
124efc27 | 716 | .pushsection .data |
1abd3502 | 717 | .align 2 |
1da177e4 | 718 | ENTRY(fp_enter) |
db6ccbb6 | 719 | .word no_fp |
124efc27 | 720 | .popsection |
1da177e4 | 721 | |
83e686ea | 722 | ENTRY(no_fp) |
6ebbf2ce | 723 | ret lr |
83e686ea | 724 | ENDPROC(no_fp) |
db6ccbb6 | 725 | |
15ac49b6 RK |
726 | __und_usr_fault_32: |
727 | mov r1, #4 | |
728 | b 1f | |
2190fed6 RK |
729 | __und_usr_fault_16_pan: |
730 | uaccess_disable ip | |
15ac49b6 RK |
731 | __und_usr_fault_16: |
732 | mov r1, #2 | |
1417a6b8 | 733 | 1: mov r0, sp |
14327c66 | 734 | badr lr, ret_from_exception |
15ac49b6 RK |
735 | b __und_fault |
736 | ENDPROC(__und_usr_fault_32) | |
737 | ENDPROC(__und_usr_fault_16) | |
1da177e4 LT |
738 | |
739 | .align 5 | |
740 | __pabt_usr: | |
ccea7a19 | 741 | usr_entry |
4fb28474 | 742 | mov r2, sp @ regs |
8dfe7ac9 | 743 | pabt_helper |
c4c5716e | 744 | UNWIND(.fnend ) |
1da177e4 LT |
745 | /* fall through */ |
746 | /* | |
747 | * This is the return code to user mode for abort handlers | |
748 | */ | |
749 | ENTRY(ret_from_exception) | |
c4c5716e CM |
750 | UNWIND(.fnstart ) |
751 | UNWIND(.cantunwind ) | |
1da177e4 LT |
752 | get_thread_info tsk |
753 | mov why, #0 | |
754 | b ret_to_user | |
c4c5716e | 755 | UNWIND(.fnend ) |
93ed3970 CM |
756 | ENDPROC(__pabt_usr) |
757 | ENDPROC(ret_from_exception) | |
1da177e4 | 758 | |
c0e7f7ee DT |
759 | .align 5 |
760 | __fiq_usr: | |
761 | usr_entry trace=0 | |
762 | kuser_cmpxchg_check | |
763 | mov r0, sp @ struct pt_regs *regs | |
764 | bl handle_fiq_as_nmi | |
765 | get_thread_info tsk | |
766 | restore_user_regs fast = 0, offset = 0 | |
767 | UNWIND(.fnend ) | |
768 | ENDPROC(__fiq_usr) | |
769 | ||
1da177e4 LT |
770 | /* |
771 | * Register switch for ARMv3 and ARMv4 processors | |
772 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info | |
773 | * previous and next are guaranteed not to be the same. | |
774 | */ | |
775 | ENTRY(__switch_to) | |
c4c5716e CM |
776 | UNWIND(.fnstart ) |
777 | UNWIND(.cantunwind ) | |
1da177e4 | 778 | add ip, r1, #TI_CPU_SAVE |
b86040a5 CM |
779 | ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack |
780 | THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack | |
781 | THUMB( str sp, [ip], #4 ) | |
782 | THUMB( str lr, [ip], #4 ) | |
a4780ade AH |
783 | ldr r4, [r2, #TI_TP_VALUE] |
784 | ldr r5, [r2, #TI_TP_VALUE + 4] | |
247055aa | 785 | #ifdef CONFIG_CPU_USE_DOMAINS |
1eef5d2f RK |
786 | mrc p15, 0, r6, c3, c0, 0 @ Get domain register |
787 | str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register | |
d6551e88 | 788 | ldr r6, [r2, #TI_CPU_DOMAIN] |
afeb90ca | 789 | #endif |
a4780ade | 790 | switch_tls r1, r4, r5, r3, r7 |
050e9baa | 791 | #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) |
df0698be NP |
792 | ldr r7, [r2, #TI_TASK] |
793 | ldr r8, =__stack_chk_guard | |
ffa47aa6 AB |
794 | .if (TSK_STACK_CANARY > IMM12_MASK) |
795 | add r7, r7, #TSK_STACK_CANARY & ~IMM12_MASK | |
796 | .endif | |
797 | ldr r7, [r7, #TSK_STACK_CANARY & IMM12_MASK] | |
df0698be | 798 | #endif |
247055aa | 799 | #ifdef CONFIG_CPU_USE_DOMAINS |
1da177e4 | 800 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
1da177e4 | 801 | #endif |
d6551e88 RK |
802 | mov r5, r0 |
803 | add r4, r2, #TI_CPU_SAVE | |
804 | ldr r0, =thread_notify_head | |
805 | mov r1, #THREAD_NOTIFY_SWITCH | |
806 | bl atomic_notifier_call_chain | |
050e9baa | 807 | #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) |
df0698be NP |
808 | str r7, [r8] |
809 | #endif | |
b86040a5 | 810 | THUMB( mov ip, r4 ) |
d6551e88 | 811 | mov r0, r5 |
b86040a5 CM |
812 | ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously |
813 | THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously | |
814 | THUMB( ldr sp, [ip], #4 ) | |
815 | THUMB( ldr pc, [ip] ) | |
c4c5716e | 816 | UNWIND(.fnend ) |
93ed3970 | 817 | ENDPROC(__switch_to) |
1da177e4 LT |
818 | |
819 | __INIT | |
2d2669b6 NP |
820 | |
821 | /* | |
822 | * User helpers. | |
823 | * | |
2d2669b6 NP |
824 | * Each segment is 32-byte aligned and will be moved to the top of the high |
825 | * vector page. New segments (if ever needed) must be added in front of | |
826 | * existing ones. This mechanism should be used only for things that are | |
827 | * really small and justified, and not be abused freely. | |
828 | * | |
37b83046 | 829 | * See Documentation/arm/kernel_user_helpers.txt for formal definitions. |
2d2669b6 | 830 | */ |
b86040a5 | 831 | THUMB( .arm ) |
2d2669b6 | 832 | |
ba9b5d76 NP |
833 | .macro usr_ret, reg |
834 | #ifdef CONFIG_ARM_THUMB | |
835 | bx \reg | |
836 | #else | |
6ebbf2ce | 837 | ret \reg |
ba9b5d76 NP |
838 | #endif |
839 | .endm | |
840 | ||
5b43e7a3 RK |
841 | .macro kuser_pad, sym, size |
842 | .if (. - \sym) & 3 | |
843 | .rept 4 - (. - \sym) & 3 | |
844 | .byte 0 | |
845 | .endr | |
846 | .endif | |
847 | .rept (\size - (. - \sym)) / 4 | |
848 | .word 0xe7fddef1 | |
849 | .endr | |
850 | .endm | |
851 | ||
f6f91b0d | 852 | #ifdef CONFIG_KUSER_HELPERS |
2d2669b6 NP |
853 | .align 5 |
854 | .globl __kuser_helper_start | |
855 | __kuser_helper_start: | |
856 | ||
7c612bfd | 857 | /* |
40fb79c8 NP |
858 | * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular |
859 | * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. | |
7c612bfd NP |
860 | */ |
861 | ||
40fb79c8 NP |
862 | __kuser_cmpxchg64: @ 0xffff0f60 |
863 | ||
db695c05 | 864 | #if defined(CONFIG_CPU_32v6K) |
40fb79c8 NP |
865 | |
866 | stmfd sp!, {r4, r5, r6, r7} | |
867 | ldrd r4, r5, [r0] @ load old val | |
868 | ldrd r6, r7, [r1] @ load new val | |
869 | smp_dmb arm | |
870 | 1: ldrexd r0, r1, [r2] @ load current val | |
871 | eors r3, r0, r4 @ compare with oldval (1) | |
e44fc388 | 872 | eorseq r3, r1, r5 @ compare with oldval (2) |
40fb79c8 NP |
873 | strexdeq r3, r6, r7, [r2] @ store newval if eq |
874 | teqeq r3, #1 @ success? | |
875 | beq 1b @ if no then retry | |
ed3768a8 | 876 | smp_dmb arm |
40fb79c8 NP |
877 | rsbs r0, r3, #0 @ set returned val and C flag |
878 | ldmfd sp!, {r4, r5, r6, r7} | |
5a97d0ae | 879 | usr_ret lr |
40fb79c8 NP |
880 | |
881 | #elif !defined(CONFIG_SMP) | |
882 | ||
883 | #ifdef CONFIG_MMU | |
884 | ||
885 | /* | |
886 | * The only thing that can break atomicity in this cmpxchg64 | |
887 | * implementation is either an IRQ or a data abort exception | |
888 | * causing another process/thread to be scheduled in the middle of | |
889 | * the critical sequence. The same strategy as for cmpxchg is used. | |
890 | */ | |
891 | stmfd sp!, {r4, r5, r6, lr} | |
892 | ldmia r0, {r4, r5} @ load old val | |
893 | ldmia r1, {r6, lr} @ load new val | |
894 | 1: ldmia r2, {r0, r1} @ load current val | |
895 | eors r3, r0, r4 @ compare with oldval (1) | |
e44fc388 SA |
896 | eorseq r3, r1, r5 @ compare with oldval (2) |
897 | 2: stmiaeq r2, {r6, lr} @ store newval if eq | |
40fb79c8 NP |
898 | rsbs r0, r3, #0 @ set return val and C flag |
899 | ldmfd sp!, {r4, r5, r6, pc} | |
900 | ||
901 | .text | |
902 | kuser_cmpxchg64_fixup: | |
903 | @ Called from kuser_cmpxchg_fixup. | |
3ad55155 | 904 | @ r4 = address of interrupted insn (must be preserved). |
40fb79c8 NP |
905 | @ sp = saved regs. r7 and r8 are clobbered. |
906 | @ 1b = first critical insn, 2b = last critical insn. | |
3ad55155 | 907 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
40fb79c8 NP |
908 | mov r7, #0xffff0fff |
909 | sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) | |
3ad55155 | 910 | subs r8, r4, r7 |
e44fc388 | 911 | rsbscs r8, r8, #(2b - 1b) |
40fb79c8 NP |
912 | strcs r7, [sp, #S_PC] |
913 | #if __LINUX_ARM_ARCH__ < 6 | |
914 | bcc kuser_cmpxchg32_fixup | |
915 | #endif | |
6ebbf2ce | 916 | ret lr |
40fb79c8 NP |
917 | .previous |
918 | ||
919 | #else | |
920 | #warning "NPTL on non MMU needs fixing" | |
921 | mov r0, #-1 | |
922 | adds r0, r0, #0 | |
ba9b5d76 | 923 | usr_ret lr |
40fb79c8 NP |
924 | #endif |
925 | ||
926 | #else | |
927 | #error "incoherent kernel configuration" | |
928 | #endif | |
929 | ||
5b43e7a3 | 930 | kuser_pad __kuser_cmpxchg64, 64 |
7c612bfd | 931 | |
7c612bfd | 932 | __kuser_memory_barrier: @ 0xffff0fa0 |
ed3768a8 | 933 | smp_dmb arm |
ba9b5d76 | 934 | usr_ret lr |
7c612bfd | 935 | |
5b43e7a3 | 936 | kuser_pad __kuser_memory_barrier, 32 |
2d2669b6 NP |
937 | |
938 | __kuser_cmpxchg: @ 0xffff0fc0 | |
939 | ||
db695c05 | 940 | #if __LINUX_ARM_ARCH__ < 6 |
2d2669b6 | 941 | |
b49c0f24 NP |
942 | #ifdef CONFIG_MMU |
943 | ||
2d2669b6 | 944 | /* |
b49c0f24 NP |
945 | * The only thing that can break atomicity in this cmpxchg |
946 | * implementation is either an IRQ or a data abort exception | |
947 | * causing another process/thread to be scheduled in the middle | |
948 | * of the critical sequence. To prevent this, code is added to | |
949 | * the IRQ and data abort exception handlers to set the pc back | |
950 | * to the beginning of the critical section if it is found to be | |
951 | * within that critical section (see kuser_cmpxchg_fixup). | |
2d2669b6 | 952 | */ |
b49c0f24 NP |
953 | 1: ldr r3, [r2] @ load current val |
954 | subs r3, r3, r0 @ compare with oldval | |
955 | 2: streq r1, [r2] @ store newval if eq | |
956 | rsbs r0, r3, #0 @ set return val and C flag | |
957 | usr_ret lr | |
958 | ||
959 | .text | |
40fb79c8 | 960 | kuser_cmpxchg32_fixup: |
b49c0f24 | 961 | @ Called from kuser_cmpxchg_check macro. |
b059bdc3 | 962 | @ r4 = address of interrupted insn (must be preserved). |
b49c0f24 NP |
963 | @ sp = saved regs. r7 and r8 are clobbered. |
964 | @ 1b = first critical insn, 2b = last critical insn. | |
b059bdc3 | 965 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
b49c0f24 NP |
966 | mov r7, #0xffff0fff |
967 | sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) | |
b059bdc3 | 968 | subs r8, r4, r7 |
e44fc388 | 969 | rsbscs r8, r8, #(2b - 1b) |
b49c0f24 | 970 | strcs r7, [sp, #S_PC] |
6ebbf2ce | 971 | ret lr |
b49c0f24 NP |
972 | .previous |
973 | ||
49bca4c2 NP |
974 | #else |
975 | #warning "NPTL on non MMU needs fixing" | |
976 | mov r0, #-1 | |
977 | adds r0, r0, #0 | |
ba9b5d76 | 978 | usr_ret lr |
b49c0f24 | 979 | #endif |
2d2669b6 NP |
980 | |
981 | #else | |
982 | ||
ed3768a8 | 983 | smp_dmb arm |
b49c0f24 | 984 | 1: ldrex r3, [r2] |
2d2669b6 NP |
985 | subs r3, r3, r0 |
986 | strexeq r3, r1, [r2] | |
b49c0f24 NP |
987 | teqeq r3, #1 |
988 | beq 1b | |
2d2669b6 | 989 | rsbs r0, r3, #0 |
b49c0f24 | 990 | /* beware -- each __kuser slot must be 8 instructions max */ |
f00ec48f RK |
991 | ALT_SMP(b __kuser_memory_barrier) |
992 | ALT_UP(usr_ret lr) | |
2d2669b6 NP |
993 | |
994 | #endif | |
995 | ||
5b43e7a3 | 996 | kuser_pad __kuser_cmpxchg, 32 |
2d2669b6 | 997 | |
2d2669b6 | 998 | __kuser_get_tls: @ 0xffff0fe0 |
f159f4ed | 999 | ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init |
ba9b5d76 | 1000 | usr_ret lr |
f159f4ed | 1001 | mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code |
5b43e7a3 RK |
1002 | kuser_pad __kuser_get_tls, 16 |
1003 | .rep 3 | |
f159f4ed TL |
1004 | .word 0 @ 0xffff0ff0 software TLS value, then |
1005 | .endr @ pad up to __kuser_helper_version | |
2d2669b6 | 1006 | |
2d2669b6 NP |
1007 | __kuser_helper_version: @ 0xffff0ffc |
1008 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) | |
1009 | ||
1010 | .globl __kuser_helper_end | |
1011 | __kuser_helper_end: | |
1012 | ||
f6f91b0d RK |
1013 | #endif |
1014 | ||
b86040a5 | 1015 | THUMB( .thumb ) |
2d2669b6 | 1016 | |
1da177e4 LT |
1017 | /* |
1018 | * Vector stubs. | |
1019 | * | |
19accfd3 RK |
1020 | * This code is copied to 0xffff1000 so we can use branches in the |
1021 | * vectors, rather than ldr's. Note that this code must not exceed | |
1022 | * a page size. | |
1da177e4 LT |
1023 | * |
1024 | * Common stub entry macro: | |
1025 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
ccea7a19 RK |
1026 | * |
1027 | * SP points to a minimal amount of processor-private memory, the address | |
1028 | * of which is copied into r0 for the mode specific abort handler. | |
1da177e4 | 1029 | */ |
b7ec4795 | 1030 | .macro vector_stub, name, mode, correction=0 |
1da177e4 LT |
1031 | .align 5 |
1032 | ||
1033 | vector_\name: | |
1da177e4 LT |
1034 | .if \correction |
1035 | sub lr, lr, #\correction | |
1036 | .endif | |
ccea7a19 RK |
1037 | |
1038 | @ | |
1039 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> | |
1040 | @ (parent CPSR) | |
1041 | @ | |
1042 | stmia sp, {r0, lr} @ save r0, lr | |
1da177e4 | 1043 | mrs lr, spsr |
ccea7a19 RK |
1044 | str lr, [sp, #8] @ save spsr |
1045 | ||
1da177e4 | 1046 | @ |
ccea7a19 | 1047 | @ Prepare for SVC32 mode. IRQs remain disabled. |
1da177e4 | 1048 | @ |
ccea7a19 | 1049 | mrs r0, cpsr |
b86040a5 | 1050 | eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) |
ccea7a19 | 1051 | msr spsr_cxsf, r0 |
1da177e4 | 1052 | |
ccea7a19 RK |
1053 | @ |
1054 | @ the branch table must immediately follow this code | |
1055 | @ | |
ccea7a19 | 1056 | and lr, lr, #0x0f |
b86040a5 CM |
1057 | THUMB( adr r0, 1f ) |
1058 | THUMB( ldr lr, [r0, lr, lsl #2] ) | |
b7ec4795 | 1059 | mov r0, sp |
b86040a5 | 1060 | ARM( ldr lr, [pc, lr, lsl #2] ) |
ccea7a19 | 1061 | movs pc, lr @ branch to handler in SVC mode |
93ed3970 | 1062 | ENDPROC(vector_\name) |
88987ef9 CM |
1063 | |
1064 | .align 2 | |
1065 | @ handler addresses follow this label | |
1066 | 1: | |
1da177e4 LT |
1067 | .endm |
1068 | ||
b9b32bf7 | 1069 | .section .stubs, "ax", %progbits |
19accfd3 RK |
1070 | @ This must be the first word |
1071 | .word vector_swi | |
1072 | ||
1073 | vector_rst: | |
1074 | ARM( swi SYS_ERROR0 ) | |
1075 | THUMB( svc #0 ) | |
1076 | THUMB( nop ) | |
1077 | b vector_und | |
1078 | ||
1da177e4 LT |
1079 | /* |
1080 | * Interrupt dispatcher | |
1081 | */ | |
b7ec4795 | 1082 | vector_stub irq, IRQ_MODE, 4 |
1da177e4 LT |
1083 | |
1084 | .long __irq_usr @ 0 (USR_26 / USR_32) | |
1085 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) | |
1086 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) | |
1087 | .long __irq_svc @ 3 (SVC_26 / SVC_32) | |
1088 | .long __irq_invalid @ 4 | |
1089 | .long __irq_invalid @ 5 | |
1090 | .long __irq_invalid @ 6 | |
1091 | .long __irq_invalid @ 7 | |
1092 | .long __irq_invalid @ 8 | |
1093 | .long __irq_invalid @ 9 | |
1094 | .long __irq_invalid @ a | |
1095 | .long __irq_invalid @ b | |
1096 | .long __irq_invalid @ c | |
1097 | .long __irq_invalid @ d | |
1098 | .long __irq_invalid @ e | |
1099 | .long __irq_invalid @ f | |
1100 | ||
1101 | /* | |
1102 | * Data abort dispatcher | |
1103 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1104 | */ | |
b7ec4795 | 1105 | vector_stub dabt, ABT_MODE, 8 |
1da177e4 LT |
1106 | |
1107 | .long __dabt_usr @ 0 (USR_26 / USR_32) | |
1108 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1109 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1110 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) | |
1111 | .long __dabt_invalid @ 4 | |
1112 | .long __dabt_invalid @ 5 | |
1113 | .long __dabt_invalid @ 6 | |
1114 | .long __dabt_invalid @ 7 | |
1115 | .long __dabt_invalid @ 8 | |
1116 | .long __dabt_invalid @ 9 | |
1117 | .long __dabt_invalid @ a | |
1118 | .long __dabt_invalid @ b | |
1119 | .long __dabt_invalid @ c | |
1120 | .long __dabt_invalid @ d | |
1121 | .long __dabt_invalid @ e | |
1122 | .long __dabt_invalid @ f | |
1123 | ||
1124 | /* | |
1125 | * Prefetch abort dispatcher | |
1126 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1127 | */ | |
b7ec4795 | 1128 | vector_stub pabt, ABT_MODE, 4 |
1da177e4 LT |
1129 | |
1130 | .long __pabt_usr @ 0 (USR_26 / USR_32) | |
1131 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1132 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1133 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) | |
1134 | .long __pabt_invalid @ 4 | |
1135 | .long __pabt_invalid @ 5 | |
1136 | .long __pabt_invalid @ 6 | |
1137 | .long __pabt_invalid @ 7 | |
1138 | .long __pabt_invalid @ 8 | |
1139 | .long __pabt_invalid @ 9 | |
1140 | .long __pabt_invalid @ a | |
1141 | .long __pabt_invalid @ b | |
1142 | .long __pabt_invalid @ c | |
1143 | .long __pabt_invalid @ d | |
1144 | .long __pabt_invalid @ e | |
1145 | .long __pabt_invalid @ f | |
1146 | ||
1147 | /* | |
1148 | * Undef instr entry dispatcher | |
1149 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
1150 | */ | |
b7ec4795 | 1151 | vector_stub und, UND_MODE |
1da177e4 LT |
1152 | |
1153 | .long __und_usr @ 0 (USR_26 / USR_32) | |
1154 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) | |
1155 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) | |
1156 | .long __und_svc @ 3 (SVC_26 / SVC_32) | |
1157 | .long __und_invalid @ 4 | |
1158 | .long __und_invalid @ 5 | |
1159 | .long __und_invalid @ 6 | |
1160 | .long __und_invalid @ 7 | |
1161 | .long __und_invalid @ 8 | |
1162 | .long __und_invalid @ 9 | |
1163 | .long __und_invalid @ a | |
1164 | .long __und_invalid @ b | |
1165 | .long __und_invalid @ c | |
1166 | .long __und_invalid @ d | |
1167 | .long __und_invalid @ e | |
1168 | .long __und_invalid @ f | |
1169 | ||
1170 | .align 5 | |
1171 | ||
19accfd3 RK |
1172 | /*============================================================================= |
1173 | * Address exception handler | |
1174 | *----------------------------------------------------------------------------- | |
1175 | * These aren't too critical. | |
1176 | * (they're not supposed to happen, and won't happen in 32-bit data mode). | |
1177 | */ | |
1178 | ||
1179 | vector_addrexcptn: | |
1180 | b vector_addrexcptn | |
1181 | ||
1da177e4 | 1182 | /*============================================================================= |
c0e7f7ee | 1183 | * FIQ "NMI" handler |
1da177e4 | 1184 | *----------------------------------------------------------------------------- |
c0e7f7ee DT |
1185 | * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86 |
1186 | * systems. | |
1da177e4 | 1187 | */ |
c0e7f7ee DT |
1188 | vector_stub fiq, FIQ_MODE, 4 |
1189 | ||
1190 | .long __fiq_usr @ 0 (USR_26 / USR_32) | |
1191 | .long __fiq_svc @ 1 (FIQ_26 / FIQ_32) | |
1192 | .long __fiq_svc @ 2 (IRQ_26 / IRQ_32) | |
1193 | .long __fiq_svc @ 3 (SVC_26 / SVC_32) | |
1194 | .long __fiq_svc @ 4 | |
1195 | .long __fiq_svc @ 5 | |
1196 | .long __fiq_svc @ 6 | |
1197 | .long __fiq_abt @ 7 | |
1198 | .long __fiq_svc @ 8 | |
1199 | .long __fiq_svc @ 9 | |
1200 | .long __fiq_svc @ a | |
1201 | .long __fiq_svc @ b | |
1202 | .long __fiq_svc @ c | |
1203 | .long __fiq_svc @ d | |
1204 | .long __fiq_svc @ e | |
1205 | .long __fiq_svc @ f | |
1da177e4 | 1206 | |
31b96cae | 1207 | .globl vector_fiq |
e39e3f3e | 1208 | |
b9b32bf7 | 1209 | .section .vectors, "ax", %progbits |
b48da558 | 1210 | .L__vectors_start: |
b9b32bf7 RK |
1211 | W(b) vector_rst |
1212 | W(b) vector_und | |
b48da558 | 1213 | W(ldr) pc, .L__vectors_start + 0x1000 |
b9b32bf7 RK |
1214 | W(b) vector_pabt |
1215 | W(b) vector_dabt | |
1216 | W(b) vector_addrexcptn | |
1217 | W(b) vector_irq | |
1218 | W(b) vector_fiq | |
1da177e4 LT |
1219 | |
1220 | .data | |
1abd3502 | 1221 | .align 2 |
1da177e4 | 1222 | |
1da177e4 | 1223 | .globl cr_alignment |
1da177e4 LT |
1224 | cr_alignment: |
1225 | .space 4 |