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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/irq.c | |
3 | * | |
4 | * Copyright (C) 1992 Linus Torvalds | |
5 | * Modifications for ARM processor Copyright (C) 1995-2000 Russell King. | |
6 | * | |
8749af68 RK |
7 | * Support for Dynamic Tick Timer Copyright (C) 2004-2005 Nokia Corporation. |
8 | * Dynamic Tick Timer written by Tony Lindgren <tony@atomide.com> and | |
9 | * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>. | |
10 | * | |
1da177e4 LT |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This file contains the code used by various IRQ handling routines: | |
16 | * asking for different IRQ's should be done through these routines | |
17 | * instead of just grabbing them. Thus setups with different IRQ numbers | |
18 | * shouldn't result in any weird surprises, and installing new handlers | |
19 | * should be easier. | |
20 | * | |
21 | * IRQ's are in fact implemented a bit like signal handlers for the kernel. | |
22 | * Naturally it's not a 1:1 relation, but there are similarities. | |
23 | */ | |
1da177e4 | 24 | #include <linux/kernel_stat.h> |
1da177e4 LT |
25 | #include <linux/signal.h> |
26 | #include <linux/ioport.h> | |
27 | #include <linux/interrupt.h> | |
4a2581a0 | 28 | #include <linux/irq.h> |
ebafed7a | 29 | #include <linux/irqchip.h> |
1da177e4 LT |
30 | #include <linux/random.h> |
31 | #include <linux/smp.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/seq_file.h> | |
108900b5 | 34 | #include <linux/ratelimit.h> |
1da177e4 LT |
35 | #include <linux/errno.h> |
36 | #include <linux/list.h> | |
37 | #include <linux/kallsyms.h> | |
38 | #include <linux/proc_fs.h> | |
05c76982 | 39 | #include <linux/export.h> |
1da177e4 | 40 | |
805604ef | 41 | #include <asm/hardware/cache-l2x0.h> |
e7ecbc05 | 42 | #include <asm/hardware/cache-uniphier.h> |
f8130906 | 43 | #include <asm/outercache.h> |
5a567d78 | 44 | #include <asm/exception.h> |
8ff1443c | 45 | #include <asm/mach/arch.h> |
897d8527 | 46 | #include <asm/mach/irq.h> |
8749af68 | 47 | #include <asm/mach/time.h> |
1da177e4 | 48 | |
4a2581a0 | 49 | unsigned long irq_err_count; |
1da177e4 | 50 | |
25a5662a | 51 | int arch_show_interrupts(struct seq_file *p, int prec) |
1da177e4 | 52 | { |
baa28e35 | 53 | #ifdef CONFIG_FIQ |
25a5662a | 54 | show_fiq_list(p, prec); |
1da177e4 LT |
55 | #endif |
56 | #ifdef CONFIG_SMP | |
25a5662a | 57 | show_ipi_list(p, prec); |
1da177e4 | 58 | #endif |
25a5662a | 59 | seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); |
1da177e4 LT |
60 | return 0; |
61 | } | |
62 | ||
1da177e4 | 63 | /* |
a4841e39 RKAL |
64 | * handle_IRQ handles all hardware IRQ's. Decoded IRQs should |
65 | * not come via this function. Instead, they should provide their | |
66 | * own 'handler'. Used by platform code implementing C-based 1st | |
67 | * level decoding. | |
1da177e4 | 68 | */ |
a4841e39 | 69 | void handle_IRQ(unsigned int irq, struct pt_regs *regs) |
1da177e4 | 70 | { |
a71b092a | 71 | __handle_domain_irq(NULL, irq, false, regs); |
1da177e4 LT |
72 | } |
73 | ||
a4841e39 RKAL |
74 | /* |
75 | * asm_do_IRQ is the interface to be used from assembly code. | |
76 | */ | |
77 | asmlinkage void __exception_irq_entry | |
78 | asm_do_IRQ(unsigned int irq, struct pt_regs *regs) | |
79 | { | |
80 | handle_IRQ(irq, regs); | |
81 | } | |
82 | ||
1da177e4 LT |
83 | void __init init_IRQ(void) |
84 | { | |
805604ef RK |
85 | int ret; |
86 | ||
ebafed7a MR |
87 | if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq) |
88 | irqchip_init(); | |
89 | else | |
90 | machine_desc->init_irq(); | |
805604ef RK |
91 | |
92 | if (IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_CACHE_L2X0) && | |
93 | (machine_desc->l2c_aux_mask || machine_desc->l2c_aux_val)) { | |
0c4c2edc TF |
94 | if (!outer_cache.write_sec) |
95 | outer_cache.write_sec = machine_desc->l2c_write_sec; | |
805604ef RK |
96 | ret = l2x0_of_init(machine_desc->l2c_aux_val, |
97 | machine_desc->l2c_aux_mask); | |
98 | if (ret) | |
99 | pr_err("L2C: failed to init: %d\n", ret); | |
100 | } | |
e7ecbc05 MY |
101 | |
102 | uniphier_cache_init(); | |
1da177e4 LT |
103 | } |
104 | ||
73171d15 TP |
105 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
106 | void __init set_handle_irq(void (*handle_irq)(struct pt_regs *)) | |
107 | { | |
108 | if (handle_arch_irq) | |
109 | return; | |
110 | ||
111 | handle_arch_irq = handle_irq; | |
112 | } | |
113 | #endif | |
114 | ||
354e6f72 | 115 | #ifdef CONFIG_SPARSE_IRQ |
116 | int __init arch_probe_nr_irqs(void) | |
117 | { | |
8ff1443c | 118 | nr_irqs = machine_desc->nr_irqs ? machine_desc->nr_irqs : NR_IRQS; |
b683de2b | 119 | return nr_irqs; |
354e6f72 | 120 | } |
121 | #endif | |
122 | ||
a054a811 | 123 | #ifdef CONFIG_HOTPLUG_CPU |
78359cb8 | 124 | static bool migrate_one_irq(struct irq_desc *desc) |
f7ede370 | 125 | { |
78359cb8 | 126 | struct irq_data *d = irq_desc_get_irq_data(desc); |
84f551c7 | 127 | const struct cpumask *affinity = irq_data_get_affinity_mask(d); |
78359cb8 | 128 | struct irq_chip *c; |
61791244 | 129 | bool ret = false; |
f7ede370 | 130 | |
78359cb8 RK |
131 | /* |
132 | * If this is a per-CPU interrupt, or the affinity does not | |
133 | * include this CPU, then we have nothing to do. | |
134 | */ | |
135 | if (irqd_is_per_cpu(d) || !cpumask_test_cpu(smp_processor_id(), affinity)) | |
136 | return false; | |
137 | ||
ca15af19 | 138 | if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) { |
78359cb8 | 139 | affinity = cpu_online_mask; |
61791244 RK |
140 | ret = true; |
141 | } | |
142 | ||
78359cb8 | 143 | c = irq_data_get_irq_chip(d); |
5e7371de | 144 | if (!c->irq_set_affinity) |
78359cb8 | 145 | pr_debug("IRQ%u: unable to set affinity\n", d->irq); |
a040803a | 146 | else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret) |
84f551c7 | 147 | cpumask_copy(irq_data_get_affinity_mask(d), affinity); |
61791244 RK |
148 | |
149 | return ret; | |
f7ede370 TG |
150 | } |
151 | ||
a054a811 | 152 | /* |
78359cb8 RK |
153 | * The current CPU has been marked offline. Migrate IRQs off this CPU. |
154 | * If the affinity settings do not allow other CPUs, force them onto any | |
a054a811 | 155 | * available CPU. |
78359cb8 RK |
156 | * |
157 | * Note: we must iterate over all IRQs, whether they have an attached | |
158 | * action structure or not, as we need to get chained interrupts too. | |
a054a811 RK |
159 | */ |
160 | void migrate_irqs(void) | |
161 | { | |
78359cb8 | 162 | unsigned int i; |
354e6f72 | 163 | struct irq_desc *desc; |
61791244 RK |
164 | unsigned long flags; |
165 | ||
166 | local_irq_save(flags); | |
a054a811 | 167 | |
354e6f72 | 168 | for_each_irq_desc(i, desc) { |
342d00ae | 169 | bool affinity_broken; |
78359cb8 | 170 | |
61791244 | 171 | raw_spin_lock(&desc->lock); |
78359cb8 | 172 | affinity_broken = migrate_one_irq(desc); |
61791244 RK |
173 | raw_spin_unlock(&desc->lock); |
174 | ||
108900b5 RK |
175 | if (affinity_broken) |
176 | pr_warn_ratelimited("IRQ%u no longer affine to CPU%u\n", | |
8b521cb2 | 177 | i, smp_processor_id()); |
a054a811 | 178 | } |
61791244 RK |
179 | |
180 | local_irq_restore(flags); | |
a054a811 RK |
181 | } |
182 | #endif /* CONFIG_HOTPLUG_CPU */ |