]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/irq.c | |
3 | * | |
4 | * Copyright (C) 1992 Linus Torvalds | |
5 | * Modifications for ARM processor Copyright (C) 1995-2000 Russell King. | |
6 | * | |
8749af68 RK |
7 | * Support for Dynamic Tick Timer Copyright (C) 2004-2005 Nokia Corporation. |
8 | * Dynamic Tick Timer written by Tony Lindgren <tony@atomide.com> and | |
9 | * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>. | |
10 | * | |
1da177e4 LT |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This file contains the code used by various IRQ handling routines: | |
16 | * asking for different IRQ's should be done through these routines | |
17 | * instead of just grabbing them. Thus setups with different IRQ numbers | |
18 | * shouldn't result in any weird surprises, and installing new handlers | |
19 | * should be easier. | |
20 | * | |
21 | * IRQ's are in fact implemented a bit like signal handlers for the kernel. | |
22 | * Naturally it's not a 1:1 relation, but there are similarities. | |
23 | */ | |
1da177e4 | 24 | #include <linux/kernel_stat.h> |
1da177e4 LT |
25 | #include <linux/signal.h> |
26 | #include <linux/ioport.h> | |
27 | #include <linux/interrupt.h> | |
4a2581a0 | 28 | #include <linux/irq.h> |
ebafed7a | 29 | #include <linux/irqchip.h> |
1da177e4 LT |
30 | #include <linux/random.h> |
31 | #include <linux/smp.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/seq_file.h> | |
108900b5 | 34 | #include <linux/ratelimit.h> |
1da177e4 LT |
35 | #include <linux/errno.h> |
36 | #include <linux/list.h> | |
37 | #include <linux/kallsyms.h> | |
38 | #include <linux/proc_fs.h> | |
05c76982 | 39 | #include <linux/export.h> |
1da177e4 | 40 | |
805604ef | 41 | #include <asm/hardware/cache-l2x0.h> |
f8130906 | 42 | #include <asm/outercache.h> |
5a567d78 | 43 | #include <asm/exception.h> |
8ff1443c | 44 | #include <asm/mach/arch.h> |
897d8527 | 45 | #include <asm/mach/irq.h> |
8749af68 | 46 | #include <asm/mach/time.h> |
1da177e4 | 47 | |
4a2581a0 | 48 | unsigned long irq_err_count; |
1da177e4 | 49 | |
25a5662a | 50 | int arch_show_interrupts(struct seq_file *p, int prec) |
1da177e4 | 51 | { |
baa28e35 | 52 | #ifdef CONFIG_FIQ |
25a5662a | 53 | show_fiq_list(p, prec); |
1da177e4 LT |
54 | #endif |
55 | #ifdef CONFIG_SMP | |
25a5662a | 56 | show_ipi_list(p, prec); |
1da177e4 | 57 | #endif |
25a5662a | 58 | seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); |
1da177e4 LT |
59 | return 0; |
60 | } | |
61 | ||
1da177e4 | 62 | /* |
a4841e39 RKAL |
63 | * handle_IRQ handles all hardware IRQ's. Decoded IRQs should |
64 | * not come via this function. Instead, they should provide their | |
65 | * own 'handler'. Used by platform code implementing C-based 1st | |
66 | * level decoding. | |
1da177e4 | 67 | */ |
a4841e39 | 68 | void handle_IRQ(unsigned int irq, struct pt_regs *regs) |
1da177e4 | 69 | { |
a71b092a | 70 | __handle_domain_irq(NULL, irq, false, regs); |
1da177e4 LT |
71 | } |
72 | ||
a4841e39 RKAL |
73 | /* |
74 | * asm_do_IRQ is the interface to be used from assembly code. | |
75 | */ | |
76 | asmlinkage void __exception_irq_entry | |
77 | asm_do_IRQ(unsigned int irq, struct pt_regs *regs) | |
78 | { | |
79 | handle_IRQ(irq, regs); | |
80 | } | |
81 | ||
1da177e4 LT |
82 | void set_irq_flags(unsigned int irq, unsigned int iflags) |
83 | { | |
1b7a2d90 | 84 | unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; |
1da177e4 | 85 | |
354e6f72 | 86 | if (irq >= nr_irqs) { |
4ed89f22 | 87 | pr_err("Trying to set irq flags for IRQ%d\n", irq); |
1da177e4 LT |
88 | return; |
89 | } | |
90 | ||
4a2581a0 | 91 | if (iflags & IRQF_VALID) |
1b7a2d90 | 92 | clr |= IRQ_NOREQUEST; |
4a2581a0 | 93 | if (iflags & IRQF_PROBE) |
1b7a2d90 | 94 | clr |= IRQ_NOPROBE; |
4a2581a0 | 95 | if (!(iflags & IRQF_NOAUTOEN)) |
1b7a2d90 TG |
96 | clr |= IRQ_NOAUTOEN; |
97 | /* Order is clear bits in "clr" then set bits in "set" */ | |
98 | irq_modify_status(irq, clr, set & ~clr); | |
1da177e4 | 99 | } |
05c76982 | 100 | EXPORT_SYMBOL_GPL(set_irq_flags); |
1da177e4 LT |
101 | |
102 | void __init init_IRQ(void) | |
103 | { | |
805604ef RK |
104 | int ret; |
105 | ||
ebafed7a MR |
106 | if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq) |
107 | irqchip_init(); | |
108 | else | |
109 | machine_desc->init_irq(); | |
805604ef RK |
110 | |
111 | if (IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_CACHE_L2X0) && | |
112 | (machine_desc->l2c_aux_mask || machine_desc->l2c_aux_val)) { | |
0c4c2edc TF |
113 | if (!outer_cache.write_sec) |
114 | outer_cache.write_sec = machine_desc->l2c_write_sec; | |
805604ef RK |
115 | ret = l2x0_of_init(machine_desc->l2c_aux_val, |
116 | machine_desc->l2c_aux_mask); | |
117 | if (ret) | |
118 | pr_err("L2C: failed to init: %d\n", ret); | |
119 | } | |
1da177e4 LT |
120 | } |
121 | ||
73171d15 TP |
122 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
123 | void __init set_handle_irq(void (*handle_irq)(struct pt_regs *)) | |
124 | { | |
125 | if (handle_arch_irq) | |
126 | return; | |
127 | ||
128 | handle_arch_irq = handle_irq; | |
129 | } | |
130 | #endif | |
131 | ||
354e6f72 | 132 | #ifdef CONFIG_SPARSE_IRQ |
133 | int __init arch_probe_nr_irqs(void) | |
134 | { | |
8ff1443c | 135 | nr_irqs = machine_desc->nr_irqs ? machine_desc->nr_irqs : NR_IRQS; |
b683de2b | 136 | return nr_irqs; |
354e6f72 | 137 | } |
138 | #endif | |
139 | ||
a054a811 | 140 | #ifdef CONFIG_HOTPLUG_CPU |
78359cb8 | 141 | static bool migrate_one_irq(struct irq_desc *desc) |
f7ede370 | 142 | { |
78359cb8 | 143 | struct irq_data *d = irq_desc_get_irq_data(desc); |
84f551c7 | 144 | const struct cpumask *affinity = irq_data_get_affinity_mask(d); |
78359cb8 | 145 | struct irq_chip *c; |
61791244 | 146 | bool ret = false; |
f7ede370 | 147 | |
78359cb8 RK |
148 | /* |
149 | * If this is a per-CPU interrupt, or the affinity does not | |
150 | * include this CPU, then we have nothing to do. | |
151 | */ | |
152 | if (irqd_is_per_cpu(d) || !cpumask_test_cpu(smp_processor_id(), affinity)) | |
153 | return false; | |
154 | ||
ca15af19 | 155 | if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) { |
78359cb8 | 156 | affinity = cpu_online_mask; |
61791244 RK |
157 | ret = true; |
158 | } | |
159 | ||
78359cb8 | 160 | c = irq_data_get_irq_chip(d); |
5e7371de | 161 | if (!c->irq_set_affinity) |
78359cb8 | 162 | pr_debug("IRQ%u: unable to set affinity\n", d->irq); |
a040803a | 163 | else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret) |
84f551c7 | 164 | cpumask_copy(irq_data_get_affinity_mask(d), affinity); |
61791244 RK |
165 | |
166 | return ret; | |
f7ede370 TG |
167 | } |
168 | ||
a054a811 | 169 | /* |
78359cb8 RK |
170 | * The current CPU has been marked offline. Migrate IRQs off this CPU. |
171 | * If the affinity settings do not allow other CPUs, force them onto any | |
a054a811 | 172 | * available CPU. |
78359cb8 RK |
173 | * |
174 | * Note: we must iterate over all IRQs, whether they have an attached | |
175 | * action structure or not, as we need to get chained interrupts too. | |
a054a811 RK |
176 | */ |
177 | void migrate_irqs(void) | |
178 | { | |
78359cb8 | 179 | unsigned int i; |
354e6f72 | 180 | struct irq_desc *desc; |
61791244 RK |
181 | unsigned long flags; |
182 | ||
183 | local_irq_save(flags); | |
a054a811 | 184 | |
354e6f72 | 185 | for_each_irq_desc(i, desc) { |
342d00ae | 186 | bool affinity_broken; |
78359cb8 | 187 | |
61791244 | 188 | raw_spin_lock(&desc->lock); |
78359cb8 | 189 | affinity_broken = migrate_one_irq(desc); |
61791244 RK |
190 | raw_spin_unlock(&desc->lock); |
191 | ||
108900b5 RK |
192 | if (affinity_broken) |
193 | pr_warn_ratelimited("IRQ%u no longer affine to CPU%u\n", | |
8b521cb2 | 194 | i, smp_processor_id()); |
a054a811 | 195 | } |
61791244 RK |
196 | |
197 | local_irq_restore(flags); | |
a054a811 RK |
198 | } |
199 | #endif /* CONFIG_HOTPLUG_CPU */ |