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ARM: kprobes: Add emulate_ldrdstrd()
[mirror_ubuntu-bionic-kernel.git] / arch / arm / kernel / kprobes-arm.c
CommitLineData
35aa1df4
QB		 1/*
2 * arch/arm/kernel/kprobes-decode.c
3 *
4 * Copyright (C) 2006, 2007 Motorola Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 */
15
16/*
17 * We do not have hardware single-stepping on ARM, This
18 * effort is further complicated by the ARM not having a
19 * "next PC" register. Instructions that change the PC
20 * can't be safely single-stepped in a MP environment, so
21 * we have a lot of work to do:
22 *
23 * In the prepare phase:
24 * *) If it is an instruction that does anything
25 * with the CPU mode, we reject it for a kprobe.
26 * (This is out of laziness rather than need. The
27 * instructions could be simulated.)
28 *
29 * *) Otherwise, decode the instruction rewriting its
30 * registers to take fixed, ordered registers and
31 * setting a handler for it to run the instruction.
32 *
33 * In the execution phase by an instruction's handler:
34 *
35 * *) If the PC is written to by the instruction, the
36 * instruction must be fully simulated in software.
35aa1df4
QB		 37 *
38 * *) Otherwise, a modified form of the instruction is
39 * directly executed. Its handler calls the
40 * instruction in insn[0]. In insn[1] is a
41 * "mov pc, lr" to return.
42 *
43 * Before calling, load up the reordered registers
44 * from the original instruction's registers. If one
45 * of the original input registers is the PC, compute
46 * and adjust the appropriate input register.
47 *
48 * After call completes, copy the output registers to
49 * the original instruction's original registers.
50 *
51 * We don't use a real breakpoint instruction since that
52 * would have us in the kernel go from SVC mode to SVC
53 * mode losing the link register. Instead we use an
54 * undefined instruction. To simplify processing, the
55 * undefined instruction used for kprobes must be reserved
56 * exclusively for kprobes use.
57 *
58 * TODO: ifdef out some instruction decoding based on architecture.
59 */
60
61#include <linux/kernel.h>
62#include <linux/kprobes.h>
63
221bf15f
JM		 64#include "kprobes.h"
65
35aa1df4
QB		 66#define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
67
68#define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
69
7be7ee2d
JM		 70#if __LINUX_ARM_ARCH__ >= 6
71#define BLX(reg) "blx "reg" \n\t"
72#else
73#define BLX(reg) "mov lr, pc \n\t" \
74 "mov pc, "reg" \n\t"
75#endif
76
983ebd93
JM		 77#define is_r15(insn, bitpos) (((insn) & (0xf << bitpos)) == (0xf << bitpos))
78
35aa1df4
QB		 79#define PSR_fs (PSR_f|PSR_s)
80
81#define KPROBE_RETURN_INSTRUCTION 0xe1a0f00e /* mov pc, lr */
35aa1df4
QB		 82
83typedef long (insn_0arg_fn_t)(void);
84typedef long (insn_1arg_fn_t)(long);
85typedef long (insn_2arg_fn_t)(long, long);
86typedef long (insn_3arg_fn_t)(long, long, long);
87typedef long (insn_4arg_fn_t)(long, long, long, long);
88typedef long long (insn_llret_0arg_fn_t)(void);
89typedef long long (insn_llret_3arg_fn_t)(long, long, long);
90typedef long long (insn_llret_4arg_fn_t)(long, long, long, long);
91
92union reg_pair {
93 long long dr;
94#ifdef __LITTLE_ENDIAN
95 struct { long r0, r1; };
96#else
97 struct { long r1, r0; };
98#endif
99};
100
35aa1df4
QB		 101/*
102 * The insnslot_?arg_r[w]flags() functions below are to keep the
103 * msr -> *fn -> mrs instruction sequences indivisible so that
104 * the state of the CPSR flags aren't inadvertently modified
105 * just before or just after the call.
106 */
107
108static inline long __kprobes
109insnslot_0arg_rflags(long cpsr, insn_0arg_fn_t *fn)
110{
111 register long ret asm("r0");
112
113 __asm__ __volatile__ (
114 "msr cpsr_fs, %[cpsr] \n\t"
115 "mov lr, pc \n\t"
116 "mov pc, %[fn] \n\t"
117 : "=r" (ret)
118 : [cpsr] "r" (cpsr), [fn] "r" (fn)
119 : "lr", "cc"
120 );
121 return ret;
122}
123
124static inline long long __kprobes
125insnslot_llret_0arg_rflags(long cpsr, insn_llret_0arg_fn_t *fn)
126{
127 register long ret0 asm("r0");
128 register long ret1 asm("r1");
129 union reg_pair fnr;
130
131 __asm__ __volatile__ (
132 "msr cpsr_fs, %[cpsr] \n\t"
133 "mov lr, pc \n\t"
134 "mov pc, %[fn] \n\t"
135 : "=r" (ret0), "=r" (ret1)
136 : [cpsr] "r" (cpsr), [fn] "r" (fn)
137 : "lr", "cc"
138 );
139 fnr.r0 = ret0;
140 fnr.r1 = ret1;
141 return fnr.dr;
142}
143
144static inline long __kprobes
145insnslot_1arg_rflags(long r0, long cpsr, insn_1arg_fn_t *fn)
146{
147 register long rr0 asm("r0") = r0;
148 register long ret asm("r0");
149
150 __asm__ __volatile__ (
151 "msr cpsr_fs, %[cpsr] \n\t"
152 "mov lr, pc \n\t"
153 "mov pc, %[fn] \n\t"
154 : "=r" (ret)
155 : "0" (rr0), [cpsr] "r" (cpsr), [fn] "r" (fn)
156 : "lr", "cc"
157 );
158 return ret;
159}
160
161static inline long __kprobes
162insnslot_2arg_rflags(long r0, long r1, long cpsr, insn_2arg_fn_t *fn)
163{
164 register long rr0 asm("r0") = r0;
165 register long rr1 asm("r1") = r1;
166 register long ret asm("r0");
167
168 __asm__ __volatile__ (
169 "msr cpsr_fs, %[cpsr] \n\t"
170 "mov lr, pc \n\t"
171 "mov pc, %[fn] \n\t"
172 : "=r" (ret)
173 : "0" (rr0), "r" (rr1),
174 [cpsr] "r" (cpsr), [fn] "r" (fn)
175 : "lr", "cc"
176 );
177 return ret;
178}
179
180static inline long __kprobes
181insnslot_3arg_rflags(long r0, long r1, long r2, long cpsr, insn_3arg_fn_t *fn)
182{
183 register long rr0 asm("r0") = r0;
184 register long rr1 asm("r1") = r1;
185 register long rr2 asm("r2") = r2;
186 register long ret asm("r0");
187
188 __asm__ __volatile__ (
189 "msr cpsr_fs, %[cpsr] \n\t"
190 "mov lr, pc \n\t"
191 "mov pc, %[fn] \n\t"
192 : "=r" (ret)
193 : "0" (rr0), "r" (rr1), "r" (rr2),
194 [cpsr] "r" (cpsr), [fn] "r" (fn)
195 : "lr", "cc"
196 );
197 return ret;
198}
199
200static inline long long __kprobes
201insnslot_llret_3arg_rflags(long r0, long r1, long r2, long cpsr,
202 insn_llret_3arg_fn_t *fn)
203{
204 register long rr0 asm("r0") = r0;
205 register long rr1 asm("r1") = r1;
206 register long rr2 asm("r2") = r2;
207 register long ret0 asm("r0");
208 register long ret1 asm("r1");
209 union reg_pair fnr;
210
211 __asm__ __volatile__ (
212 "msr cpsr_fs, %[cpsr] \n\t"
213 "mov lr, pc \n\t"
214 "mov pc, %[fn] \n\t"
215 : "=r" (ret0), "=r" (ret1)
216 : "0" (rr0), "r" (rr1), "r" (rr2),
217 [cpsr] "r" (cpsr), [fn] "r" (fn)
218 : "lr", "cc"
219 );
220 fnr.r0 = ret0;
221 fnr.r1 = ret1;
222 return fnr.dr;
223}
224
225static inline long __kprobes
226insnslot_4arg_rflags(long r0, long r1, long r2, long r3, long cpsr,
227 insn_4arg_fn_t *fn)
228{
229 register long rr0 asm("r0") = r0;
230 register long rr1 asm("r1") = r1;
231 register long rr2 asm("r2") = r2;
232 register long rr3 asm("r3") = r3;
233 register long ret asm("r0");
234
235 __asm__ __volatile__ (
236 "msr cpsr_fs, %[cpsr] \n\t"
237 "mov lr, pc \n\t"
238 "mov pc, %[fn] \n\t"
239 : "=r" (ret)
240 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
241 [cpsr] "r" (cpsr), [fn] "r" (fn)
242 : "lr", "cc"
243 );
244 return ret;
245}
246
247static inline long __kprobes
248insnslot_1arg_rwflags(long r0, long *cpsr, insn_1arg_fn_t *fn)
249{
250 register long rr0 asm("r0") = r0;
251 register long ret asm("r0");
252 long oldcpsr = *cpsr;
253 long newcpsr;
254
255 __asm__ __volatile__ (
256 "msr cpsr_fs, %[oldcpsr] \n\t"
257 "mov lr, pc \n\t"
258 "mov pc, %[fn] \n\t"
259 "mrs %[newcpsr], cpsr \n\t"
260 : "=r" (ret), [newcpsr] "=r" (newcpsr)
261 : "0" (rr0), [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
262 : "lr", "cc"
263 );
264 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
265 return ret;
266}
267
268static inline long __kprobes
269insnslot_2arg_rwflags(long r0, long r1, long *cpsr, insn_2arg_fn_t *fn)
270{
271 register long rr0 asm("r0") = r0;
272 register long rr1 asm("r1") = r1;
273 register long ret asm("r0");
274 long oldcpsr = *cpsr;
275 long newcpsr;
276
277 __asm__ __volatile__ (
278 "msr cpsr_fs, %[oldcpsr] \n\t"
279 "mov lr, pc \n\t"
280 "mov pc, %[fn] \n\t"
281 "mrs %[newcpsr], cpsr \n\t"
282 : "=r" (ret), [newcpsr] "=r" (newcpsr)
283 : "0" (rr0), "r" (rr1), [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
284 : "lr", "cc"
285 );
286 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
287 return ret;
288}
289
290static inline long __kprobes
291insnslot_3arg_rwflags(long r0, long r1, long r2, long *cpsr,
292 insn_3arg_fn_t *fn)
293{
294 register long rr0 asm("r0") = r0;
295 register long rr1 asm("r1") = r1;
296 register long rr2 asm("r2") = r2;
297 register long ret asm("r0");
298 long oldcpsr = *cpsr;
299 long newcpsr;
300
301 __asm__ __volatile__ (
302 "msr cpsr_fs, %[oldcpsr] \n\t"
303 "mov lr, pc \n\t"
304 "mov pc, %[fn] \n\t"
305 "mrs %[newcpsr], cpsr \n\t"
306 : "=r" (ret), [newcpsr] "=r" (newcpsr)
307 : "0" (rr0), "r" (rr1), "r" (rr2),
308 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
309 : "lr", "cc"
310 );
311 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
312 return ret;
313}
314
315static inline long __kprobes
316insnslot_4arg_rwflags(long r0, long r1, long r2, long r3, long *cpsr,
317 insn_4arg_fn_t *fn)
318{
319 register long rr0 asm("r0") = r0;
320 register long rr1 asm("r1") = r1;
321 register long rr2 asm("r2") = r2;
322 register long rr3 asm("r3") = r3;
323 register long ret asm("r0");
324 long oldcpsr = *cpsr;
325 long newcpsr;
326
327 __asm__ __volatile__ (
328 "msr cpsr_fs, %[oldcpsr] \n\t"
329 "mov lr, pc \n\t"
330 "mov pc, %[fn] \n\t"
331 "mrs %[newcpsr], cpsr \n\t"
332 : "=r" (ret), [newcpsr] "=r" (newcpsr)
333 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
334 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
335 : "lr", "cc"
336 );
337 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
338 return ret;
339}
340
341static inline long long __kprobes
342insnslot_llret_4arg_rwflags(long r0, long r1, long r2, long r3, long *cpsr,
343 insn_llret_4arg_fn_t *fn)
344{
345 register long rr0 asm("r0") = r0;
346 register long rr1 asm("r1") = r1;
347 register long rr2 asm("r2") = r2;
348 register long rr3 asm("r3") = r3;
349 register long ret0 asm("r0");
350 register long ret1 asm("r1");
351 long oldcpsr = *cpsr;
352 long newcpsr;
353 union reg_pair fnr;
354
355 __asm__ __volatile__ (
356 "msr cpsr_fs, %[oldcpsr] \n\t"
357 "mov lr, pc \n\t"
358 "mov pc, %[fn] \n\t"
359 "mrs %[newcpsr], cpsr \n\t"
360 : "=r" (ret0), "=r" (ret1), [newcpsr] "=r" (newcpsr)
361 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
362 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
363 : "lr", "cc"
364 );
365 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
366 fnr.r0 = ret0;
367 fnr.r1 = ret1;
368 return fnr.dr;
369}
370
371/*
372 * To avoid the complications of mimicing single-stepping on a
373 * processor without a Next-PC or a single-step mode, and to
374 * avoid having to deal with the side-effects of boosting, we
375 * simulate or emulate (almost) all ARM instructions.
376 *
377 * "Simulation" is where the instruction's behavior is duplicated in
378 * C code. "Emulation" is where the original instruction is rewritten
379 * and executed, often by altering its registers.
380 *
381 * By having all behavior of the kprobe'd instruction completed before
382 * returning from the kprobe_handler(), all locks (scheduler and
383 * interrupt) can safely be released. There is no need for secondary
384 * breakpoints, no race with MP or preemptable kernels, nor having to
385 * clean up resources counts at a later time impacting overall system
386 * performance. By rewriting the instruction, only the minimum registers
387 * need to be loaded and saved back optimizing performance.
388 *
389 * Calling the insnslot_*_rwflags version of a function doesn't hurt
390 * anything even when the CPSR flags aren't updated by the
391 * instruction. It's just a little slower in return for saving
392 * a little space by not having a duplicate function that doesn't
393 * update the flags. (The same optimization can be said for
394 * instructions that do or don't perform register writeback)
395 * Also, instructions can either read the flags, only write the
396 * flags, or read and write the flags. To save combinations
397 * rather than for sheer performance, flag functions just assume
398 * read and write of flags.
399 */
400
401static void __kprobes simulate_bbl(struct kprobe *p, struct pt_regs *regs)
402{
35aa1df4
QB		 403 kprobe_opcode_t insn = p->opcode;
404 long iaddr = (long)p->addr;
405 int disp = branch_displacement(insn);
406
35aa1df4
QB		 407 if (insn & (1 << 24))
408 regs->ARM_lr = iaddr + 4;
409
410 regs->ARM_pc = iaddr + 8 + disp;
411}
412
413static void __kprobes simulate_blx1(struct kprobe *p, struct pt_regs *regs)
414{
415 kprobe_opcode_t insn = p->opcode;
416 long iaddr = (long)p->addr;
417 int disp = branch_displacement(insn);
418
419 regs->ARM_lr = iaddr + 4;
420 regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2);
421 regs->ARM_cpsr |= PSR_T_BIT;
422}
423
424static void __kprobes simulate_blx2bx(struct kprobe *p, struct pt_regs *regs)
425{
35aa1df4
QB		 426 kprobe_opcode_t insn = p->opcode;
427 int rm = insn & 0xf;
428 long rmv = regs->uregs[rm];
429
35aa1df4
QB		 430 if (insn & (1 << 5))
431 regs->ARM_lr = (long)p->addr + 4;
432
433 regs->ARM_pc = rmv & ~0x1;
434 regs->ARM_cpsr &= ~PSR_T_BIT;
435 if (rmv & 0x1)
436 regs->ARM_cpsr |= PSR_T_BIT;
437}
438
c412aba2
JM		 439static void __kprobes simulate_mrs(struct kprobe *p, struct pt_regs *regs)
440{
441 kprobe_opcode_t insn = p->opcode;
442 int rd = (insn >> 12) & 0xf;
443 unsigned long mask = 0xf8ff03df; /* Mask out execution state */
444 regs->uregs[rd] = regs->ARM_cpsr & mask;
445}
446
35aa1df4
QB		 447static void __kprobes simulate_mov_ipsp(struct kprobe *p, struct pt_regs *regs)
448{
449 regs->uregs[12] = regs->uregs[13];
450}
451
35aa1df4
QB		 452static void __kprobes emulate_ldrd(struct kprobe *p, struct pt_regs *regs)
453{
454 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
455 kprobe_opcode_t insn = p->opcode;
cf3cc1aa 456 long ppc = (long)p->addr + 8;
35aa1df4
QB		 457 int rd = (insn >> 12) & 0xf;
458 int rn = (insn >> 16) & 0xf;
459 int rm = insn & 0xf; /* rm may be invalid, don't care. */
cf3cc1aa
VR		 460 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
461 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
35aa1df4
QB		 462
463 /* Not following the C calling convention here, so need asm(). */
464 __asm__ __volatile__ (
465 "ldr r0, %[rn] \n\t"
466 "ldr r1, %[rm] \n\t"
467 "msr cpsr_fs, %[cpsr]\n\t"
468 "mov lr, pc \n\t"
469 "mov pc, %[i_fn] \n\t"
470 "str r0, %[rn] \n\t" /* in case of writeback */
471 "str r2, %[rd0] \n\t"
472 "str r3, %[rd1] \n\t"
cf3cc1aa 473 : [rn] "+m" (rnv),
35aa1df4
QB		 474 [rd0] "=m" (regs->uregs[rd]),
475 [rd1] "=m" (regs->uregs[rd+1])
cf3cc1aa 476 : [rm] "m" (rmv),
35aa1df4
QB		 477 [cpsr] "r" (regs->ARM_cpsr),
478 [i_fn] "r" (i_fn)
479 : "r0", "r1", "r2", "r3", "lr", "cc"
480 );
5c6b76fc
JM		 481 if (is_writeback(insn))
482 regs->uregs[rn] = rnv;
35aa1df4
QB		 483}
484
485static void __kprobes emulate_strd(struct kprobe *p, struct pt_regs *regs)
486{
487 insn_4arg_fn_t *i_fn = (insn_4arg_fn_t *)&p->ainsn.insn[0];
488 kprobe_opcode_t insn = p->opcode;
cf3cc1aa 489 long ppc = (long)p->addr + 8;
35aa1df4
QB		 490 int rd = (insn >> 12) & 0xf;
491 int rn = (insn >> 16) & 0xf;
492 int rm = insn & 0xf;
cf3cc1aa
VR		 493 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
494 /* rm/rmv may be invalid, don't care. */
495 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
496 long rnv_wb;
35aa1df4 497
cf3cc1aa 498 rnv_wb = insnslot_4arg_rflags(rnv, rmv, regs->uregs[rd],
35aa1df4
QB		 499 regs->uregs[rd+1],
500 regs->ARM_cpsr, i_fn);
5c6b76fc
JM		 501 if (is_writeback(insn))
502 regs->uregs[rn] = rnv_wb;
35aa1df4
QB		 503}
504
505static void __kprobes emulate_ldr(struct kprobe *p, struct pt_regs *regs)
506{
507 insn_llret_3arg_fn_t *i_fn = (insn_llret_3arg_fn_t *)&p->ainsn.insn[0];
508 kprobe_opcode_t insn = p->opcode;
0ebe25f9 509 long ppc = (long)p->addr + 8;
35aa1df4
QB		 510 union reg_pair fnr;
511 int rd = (insn >> 12) & 0xf;
512 int rn = (insn >> 16) & 0xf;
513 int rm = insn & 0xf;
514 long rdv;
0ebe25f9
NP		 515 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
516 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
35aa1df4
QB		 517 long cpsr = regs->ARM_cpsr;
518
519 fnr.dr = insnslot_llret_3arg_rflags(rnv, 0, rmv, cpsr, i_fn);
0652f067
VR		 520 if (rn != 15)
521 regs->uregs[rn] = fnr.r0; /* Save Rn in case of writeback. */
35aa1df4
QB		 522 rdv = fnr.r1;
523
524 if (rd == 15) {
525#if __LINUX_ARM_ARCH__ >= 5
526 cpsr &= ~PSR_T_BIT;
527 if (rdv & 0x1)
528 cpsr |= PSR_T_BIT;
529 regs->ARM_cpsr = cpsr;
530 rdv &= ~0x1;
531#else
532 rdv &= ~0x2;
533#endif
534 }
535 regs->uregs[rd] = rdv;
536}
537
538static void __kprobes emulate_str(struct kprobe *p, struct pt_regs *regs)
539{
540 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
541 kprobe_opcode_t insn = p->opcode;
542 long iaddr = (long)p->addr;
543 int rd = (insn >> 12) & 0xf;
544 int rn = (insn >> 16) & 0xf;
545 int rm = insn & 0xf;
546 long rdv = (rd == 15) ? iaddr + str_pc_offset : regs->uregs[rd];
547 long rnv = (rn == 15) ? iaddr + 8 : regs->uregs[rn];
548 long rmv = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */
0652f067 549 long rnv_wb;
35aa1df4 550
0652f067
VR		 551 rnv_wb = insnslot_3arg_rflags(rnv, rdv, rmv, regs->ARM_cpsr, i_fn);
552 if (rn != 15)
553 regs->uregs[rn] = rnv_wb; /* Save Rn in case of writeback. */
35aa1df4
QB		 554}
555
35aa1df4
QB		 556static void __kprobes emulate_sat(struct kprobe *p, struct pt_regs *regs)
557{
558 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
559 kprobe_opcode_t insn = p->opcode;
560 int rd = (insn >> 12) & 0xf;
561 int rm = insn & 0xf;
562 long rmv = regs->uregs[rm];
563
564 /* Writes Q flag */
565 regs->uregs[rd] = insnslot_1arg_rwflags(rmv, &regs->ARM_cpsr, i_fn);
566}
567
568static void __kprobes emulate_sel(struct kprobe *p, struct pt_regs *regs)
569{
570 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
571 kprobe_opcode_t insn = p->opcode;
572 int rd = (insn >> 12) & 0xf;
573 int rn = (insn >> 16) & 0xf;
574 int rm = insn & 0xf;
575 long rnv = regs->uregs[rn];
576 long rmv = regs->uregs[rm];
577
578 /* Reads GE bits */
579 regs->uregs[rd] = insnslot_2arg_rflags(rnv, rmv, regs->ARM_cpsr, i_fn);
580}
581
582static void __kprobes emulate_none(struct kprobe *p, struct pt_regs *regs)
583{
584 insn_0arg_fn_t *i_fn = (insn_0arg_fn_t *)&p->ainsn.insn[0];
585
586 insnslot_0arg_rflags(regs->ARM_cpsr, i_fn);
587}
588
41713d13 589static void __kprobes emulate_nop(struct kprobe *p, struct pt_regs *regs)
35aa1df4 590{
35aa1df4
QB		 591}
592
c9836777
JM		 593static void __kprobes
594emulate_rd12_modify(struct kprobe *p, struct pt_regs *regs)
595{
596 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
597 kprobe_opcode_t insn = p->opcode;
598 int rd = (insn >> 12) & 0xf;
599 long rdv = regs->uregs[rd];
600
601 regs->uregs[rd] = insnslot_1arg_rflags(rdv, regs->ARM_cpsr, i_fn);
602}
603
20e8155e
JM		 604static void __kprobes
605emulate_rd12rn0_modify(struct kprobe *p, struct pt_regs *regs)
606{
607 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
608 kprobe_opcode_t insn = p->opcode;
609 int rd = (insn >> 12) & 0xf;
610 int rn = insn & 0xf;
611 long rdv = regs->uregs[rd];
612 long rnv = regs->uregs[rn];
613
614 regs->uregs[rd] = insnslot_2arg_rflags(rdv, rnv, regs->ARM_cpsr, i_fn);
615}
616
35aa1df4
QB		 617static void __kprobes emulate_rd12rm0(struct kprobe *p, struct pt_regs *regs)
618{
619 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
620 kprobe_opcode_t insn = p->opcode;
621 int rd = (insn >> 12) & 0xf;
622 int rm = insn & 0xf;
623 long rmv = regs->uregs[rm];
624
625 regs->uregs[rd] = insnslot_1arg_rflags(rmv, regs->ARM_cpsr, i_fn);
626}
627
628static void __kprobes
629emulate_rd12rn16rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
630{
631 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
632 kprobe_opcode_t insn = p->opcode;
633 int rd = (insn >> 12) & 0xf;
634 int rn = (insn >> 16) & 0xf;
635 int rm = insn & 0xf;
636 long rnv = regs->uregs[rn];
637 long rmv = regs->uregs[rm];
638
639 regs->uregs[rd] =
640 insnslot_2arg_rwflags(rnv, rmv, &regs->ARM_cpsr, i_fn);
641}
642
643static void __kprobes
644emulate_rd16rn12rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
645{
646 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
647 kprobe_opcode_t insn = p->opcode;
648 int rd = (insn >> 16) & 0xf;
649 int rn = (insn >> 12) & 0xf;
650 int rs = (insn >> 8) & 0xf;
651 int rm = insn & 0xf;
652 long rnv = regs->uregs[rn];
653 long rsv = regs->uregs[rs];
654 long rmv = regs->uregs[rm];
655
656 regs->uregs[rd] =
657 insnslot_3arg_rwflags(rnv, rsv, rmv, &regs->ARM_cpsr, i_fn);
658}
659
660static void __kprobes
661emulate_rd16rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
662{
663 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
664 kprobe_opcode_t insn = p->opcode;
665 int rd = (insn >> 16) & 0xf;
666 int rs = (insn >> 8) & 0xf;
667 int rm = insn & 0xf;
668 long rsv = regs->uregs[rs];
669 long rmv = regs->uregs[rm];
670
671 regs->uregs[rd] =
672 insnslot_2arg_rwflags(rsv, rmv, &regs->ARM_cpsr, i_fn);
673}
674
675static void __kprobes
676emulate_rdhi16rdlo12rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
677{
678 insn_llret_4arg_fn_t *i_fn = (insn_llret_4arg_fn_t *)&p->ainsn.insn[0];
679 kprobe_opcode_t insn = p->opcode;
680 union reg_pair fnr;
681 int rdhi = (insn >> 16) & 0xf;
682 int rdlo = (insn >> 12) & 0xf;
683 int rs = (insn >> 8) & 0xf;
684 int rm = insn & 0xf;
685 long rsv = regs->uregs[rs];
686 long rmv = regs->uregs[rm];
687
688 fnr.dr = insnslot_llret_4arg_rwflags(regs->uregs[rdhi],
689 regs->uregs[rdlo], rsv, rmv,
690 &regs->ARM_cpsr, i_fn);
691 regs->uregs[rdhi] = fnr.r0;
692 regs->uregs[rdlo] = fnr.r1;
693}
694
695static void __kprobes
696emulate_alu_imm_rflags(struct kprobe *p, struct pt_regs *regs)
697{
698 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
699 kprobe_opcode_t insn = p->opcode;
700 int rd = (insn >> 12) & 0xf;
701 int rn = (insn >> 16) & 0xf;
702 long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn];
703
704 regs->uregs[rd] = insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
705}
706
707static void __kprobes
708emulate_alu_imm_rwflags(struct kprobe *p, struct pt_regs *regs)
709{
710 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
711 kprobe_opcode_t insn = p->opcode;
712 int rd = (insn >> 12) & 0xf;
713 int rn = (insn >> 16) & 0xf;
714 long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn];
715
716 regs->uregs[rd] = insnslot_1arg_rwflags(rnv, &regs->ARM_cpsr, i_fn);
717}
718
ad111ce4
JM		 719static void __kprobes
720emulate_alu_tests_imm(struct kprobe *p, struct pt_regs *regs)
721{
722 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
723 kprobe_opcode_t insn = p->opcode;
724 int rn = (insn >> 16) & 0xf;
725 long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn];
726
727 insnslot_1arg_rwflags(rnv, &regs->ARM_cpsr, i_fn);
728}
729
35aa1df4
QB		 730static void __kprobes
731emulate_alu_rflags(struct kprobe *p, struct pt_regs *regs)
732{
733 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
734 kprobe_opcode_t insn = p->opcode;
735 long ppc = (long)p->addr + 8;
736 int rd = (insn >> 12) & 0xf;
737 int rn = (insn >> 16) & 0xf; /* rn/rnv/rs/rsv may be */
738 int rs = (insn >> 8) & 0xf; /* invalid, don't care. */
739 int rm = insn & 0xf;
740 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
741 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
742 long rsv = regs->uregs[rs];
743
744 regs->uregs[rd] =
745 insnslot_3arg_rflags(rnv, rmv, rsv, regs->ARM_cpsr, i_fn);
746}
747
748static void __kprobes
749emulate_alu_rwflags(struct kprobe *p, struct pt_regs *regs)
750{
751 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
752 kprobe_opcode_t insn = p->opcode;
753 long ppc = (long)p->addr + 8;
754 int rd = (insn >> 12) & 0xf;
755 int rn = (insn >> 16) & 0xf; /* rn/rnv/rs/rsv may be */
756 int rs = (insn >> 8) & 0xf; /* invalid, don't care. */
757 int rm = insn & 0xf;
758 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
759 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
760 long rsv = regs->uregs[rs];
761
762 regs->uregs[rd] =
763 insnslot_3arg_rwflags(rnv, rmv, rsv, &regs->ARM_cpsr, i_fn);
764}
765
ad111ce4
JM		 766static void __kprobes
767emulate_alu_tests(struct kprobe *p, struct pt_regs *regs)
768{
769 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
770 kprobe_opcode_t insn = p->opcode;
771 long ppc = (long)p->addr + 8;
772 int rn = (insn >> 16) & 0xf;
773 int rs = (insn >> 8) & 0xf; /* rs/rsv may be invalid, don't care. */
774 int rm = insn & 0xf;
775 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
776 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
777 long rsv = regs->uregs[rs];
778
779 insnslot_3arg_rwflags(rnv, rmv, rsv, &regs->ARM_cpsr, i_fn);
780}
781
35aa1df4
QB		 782static enum kprobe_insn __kprobes
783prep_emulate_ldr_str(kprobe_opcode_t insn, struct arch_specific_insn *asi)
784{
6823fc85
JM		 785 int not_imm = (insn & (1 << 26)) ? (insn & (1 << 25))
786 : (~insn & (1 << 22));
35aa1df4 787
54823acc
JM		 788 if (is_writeback(insn) && is_r15(insn, 16))
789 return INSN_REJECTED; /* Writeback to PC */
790
35aa1df4
QB		 791 insn &= 0xfff00fff;
792 insn |= 0x00001000; /* Rn = r0, Rd = r1 */
6823fc85 793 if (not_imm) {
35aa1df4
QB		 794 insn &= ~0xf;
795 insn |= 2; /* Rm = r2 */
796 }
797 asi->insn[0] = insn;
798 asi->insn_handler = (insn & (1 << 20)) ? emulate_ldr : emulate_str;
799 return INSN_GOOD;
800}
801
c9836777
JM		 802static enum kprobe_insn __kprobes
803prep_emulate_rd12_modify(kprobe_opcode_t insn, struct arch_specific_insn *asi)
804{
805 if (is_r15(insn, 12))
806 return INSN_REJECTED; /* Rd is PC */
807
808 insn &= 0xffff0fff; /* Rd = r0 */
809 asi->insn[0] = insn;
810 asi->insn_handler = emulate_rd12_modify;
811 return INSN_GOOD;
812}
813
20e8155e
JM		 814static enum kprobe_insn __kprobes
815prep_emulate_rd12rn0_modify(kprobe_opcode_t insn,
816 struct arch_specific_insn *asi)
817{
818 if (is_r15(insn, 12))
819 return INSN_REJECTED; /* Rd is PC */
820
821 insn &= 0xffff0ff0; /* Rd = r0 */
822 insn |= 0x00000001; /* Rn = r1 */
823 asi->insn[0] = insn;
824 asi->insn_handler = emulate_rd12rn0_modify;
825 return INSN_GOOD;
826}
827
35aa1df4
QB		 828static enum kprobe_insn __kprobes
829prep_emulate_rd12rm0(kprobe_opcode_t insn, struct arch_specific_insn *asi)
830{
983ebd93
JM		 831 if (is_r15(insn, 12))
832 return INSN_REJECTED; /* Rd is PC */
833
35aa1df4
QB		 834 insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */
835 asi->insn[0] = insn;
836 asi->insn_handler = emulate_rd12rm0;
837 return INSN_GOOD;
838}
839
35aa1df4
QB		 840static enum kprobe_insn __kprobes
841prep_emulate_rd12rn16rm0_wflags(kprobe_opcode_t insn,
842 struct arch_specific_insn *asi)
843{
983ebd93
JM		 844 if (is_r15(insn, 12))
845 return INSN_REJECTED; /* Rd is PC */
846
35aa1df4
QB		 847 insn &= 0xfff00ff0; /* Rd = r0, Rn = r0 */
848 insn |= 0x00000001; /* Rm = r1 */
849 asi->insn[0] = insn;
850 asi->insn_handler = emulate_rd12rn16rm0_rwflags;
851 return INSN_GOOD;
852}
853
854static enum kprobe_insn __kprobes
855prep_emulate_rd16rs8rm0_wflags(kprobe_opcode_t insn,
856 struct arch_specific_insn *asi)
857{
983ebd93
JM		 858 if (is_r15(insn, 16))
859 return INSN_REJECTED; /* Rd is PC */
860
35aa1df4
QB		 861 insn &= 0xfff0f0f0; /* Rd = r0, Rs = r0 */
862 insn |= 0x00000001; /* Rm = r1 */
863 asi->insn[0] = insn;
864 asi->insn_handler = emulate_rd16rs8rm0_rwflags;
865 return INSN_GOOD;
866}
867
868static enum kprobe_insn __kprobes
869prep_emulate_rd16rn12rs8rm0_wflags(kprobe_opcode_t insn,
870 struct arch_specific_insn *asi)
871{
983ebd93
JM		 872 if (is_r15(insn, 16))
873 return INSN_REJECTED; /* Rd is PC */
874
35aa1df4
QB		 875 insn &= 0xfff000f0; /* Rd = r0, Rn = r0 */
876 insn |= 0x00000102; /* Rs = r1, Rm = r2 */
877 asi->insn[0] = insn;
878 asi->insn_handler = emulate_rd16rn12rs8rm0_rwflags;
879 return INSN_GOOD;
880}
881
882static enum kprobe_insn __kprobes
883prep_emulate_rdhi16rdlo12rs8rm0_wflags(kprobe_opcode_t insn,
884 struct arch_specific_insn *asi)
885{
983ebd93
JM		 886 if (is_r15(insn, 16) || is_r15(insn, 12))
887 return INSN_REJECTED; /* RdHi or RdLo is PC */
888
35aa1df4
QB		 889 insn &= 0xfff000f0; /* RdHi = r0, RdLo = r1 */
890 insn |= 0x00001203; /* Rs = r2, Rm = r3 */
891 asi->insn[0] = insn;
892 asi->insn_handler = emulate_rdhi16rdlo12rs8rm0_rwflags;
893 return INSN_GOOD;
894}
895
8723942f
JM		 896static void __kprobes
897emulate_ldrdstrd(struct kprobe *p, struct pt_regs *regs)
898{
899 kprobe_opcode_t insn = p->opcode;
900 unsigned long pc = (unsigned long)p->addr + 8;
901 int rt = (insn >> 12) & 0xf;
902 int rn = (insn >> 16) & 0xf;
903 int rm = insn & 0xf;
904
905 register unsigned long rtv asm("r0") = regs->uregs[rt];
906 register unsigned long rt2v asm("r1") = regs->uregs[rt+1];
907 register unsigned long rnv asm("r2") = (rn == 15) ? pc
908 : regs->uregs[rn];
909 register unsigned long rmv asm("r3") = regs->uregs[rm];
910
911 __asm__ __volatile__ (
912 BLX("%[fn]")
913 : "=r" (rtv), "=r" (rt2v), "=r" (rnv)
914 : "0" (rtv), "1" (rt2v), "2" (rnv), "r" (rmv),
915 [fn] "r" (p->ainsn.insn_fn)
916 : "lr", "memory", "cc"
917 );
918
919 regs->uregs[rt] = rtv;
920 regs->uregs[rt+1] = rt2v;
921 if (is_writeback(insn))
922 regs->uregs[rn] = rnv;
923}
924
9f596e51
JM		 925static void __kprobes
926emulate_rd12rn16rm0rs8_rwflags(struct kprobe *p, struct pt_regs *regs)
927{
928 kprobe_opcode_t insn = p->opcode;
929 unsigned long pc = (unsigned long)p->addr + 8;
930 int rd = (insn >> 12) & 0xf;
931 int rn = (insn >> 16) & 0xf;
932 int rm = insn & 0xf;
933 int rs = (insn >> 8) & 0xf;
934
935 register unsigned long rdv asm("r0") = regs->uregs[rd];
936 register unsigned long rnv asm("r2") = (rn == 15) ? pc
937 : regs->uregs[rn];
938 register unsigned long rmv asm("r3") = (rm == 15) ? pc
939 : regs->uregs[rm];
940 register unsigned long rsv asm("r1") = regs->uregs[rs];
941 unsigned long cpsr = regs->ARM_cpsr;
942
943 __asm__ __volatile__ (
944 "msr cpsr_fs, %[cpsr] \n\t"
945 BLX("%[fn]")
946 "mrs %[cpsr], cpsr \n\t"
947 : "=r" (rdv), [cpsr] "=r" (cpsr)
948 : "0" (rdv), "r" (rnv), "r" (rmv), "r" (rsv),
949 "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
950 : "lr", "memory", "cc"
951 );
952
953 if (rd == 15)
954 alu_write_pc(rdv, regs);
955 else
956 regs->uregs[rd] = rdv;
957 regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
958}
959
35aa1df4
QB		 960/*
961 * For the instruction masking and comparisons in all the "space_*"
962 * functions below, Do _not_ rearrange the order of tests unless
963 * you're very, very sure of what you are doing. For the sake of
964 * efficiency, the masks for some tests sometimes assume other test
965 * have been done prior to them so the number of patterns to test
966 * for an instruction set can be as broad as possible to reduce the
967 * number of tests needed.
968 */
969
9a5c1284
JM		 970static const union decode_item arm_1111_table[] = {
971 /* Unconditional instructions */
35aa1df4 972
9a5c1284
JM		 973 /* memory hint 1111 0100 x001 xxxx xxxx xxxx xxxx xxxx */
974 /* PLDI (immediate) 1111 0100 x101 xxxx xxxx xxxx xxxx xxxx */
975 /* PLDW (immediate) 1111 0101 x001 xxxx xxxx xxxx xxxx xxxx */
976 /* PLD (immediate) 1111 0101 x101 xxxx xxxx xxxx xxxx xxxx */
977 DECODE_SIMULATE (0xfe300000, 0xf4100000, kprobe_simulate_nop),
35aa1df4 978
9a5c1284
JM		 979 /* BLX (immediate) 1111 101x xxxx xxxx xxxx xxxx xxxx xxxx */
980 DECODE_SIMULATE (0xfe000000, 0xfa000000, simulate_blx1),
72c2bab2 981
9a5c1284
JM		 982 /* CPS 1111 0001 0000 xxx0 xxxx xxxx xx0x xxxx */
983 /* SETEND 1111 0001 0000 0001 xxxx xxxx 0000 xxxx */
984 /* SRS 1111 100x x1x0 xxxx xxxx xxxx xxxx xxxx */
985 /* RFE 1111 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
35aa1df4 986
fa1a03b4 987 /* Coprocessor instructions... */
9a5c1284
JM		 988 /* MCRR2 1111 1100 0100 xxxx xxxx xxxx xxxx xxxx */
989 /* MRRC2 1111 1100 0101 xxxx xxxx xxxx xxxx xxxx */
990 /* LDC2 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
991 /* STC2 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
992 /* CDP2 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
993 /* MCR2 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
994 /* MRC2 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
995
996 /* Other unallocated instructions... */
997 DECODE_END
998};
35aa1df4 999
3535a89a
JM		 1000static const union decode_item arm_cccc_000x_table[] = {
1001 /* Data-processing (register) */
1002
1003 /* <op>S PC, ... cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx */
1004 DECODE_REJECT (0x0e10f000, 0x0010f000),
1005
1006 /* MOV IP, SP 1110 0001 1010 0000 1100 0000 0000 1101 */
1007 DECODE_SIMULATE (0xffffffff, 0xe1a0c00d, simulate_mov_ipsp),
1008
1009 /* TST (register) cccc 0001 0001 xxxx xxxx xxxx xxx0 xxxx */
1010 /* TEQ (register) cccc 0001 0011 xxxx xxxx xxxx xxx0 xxxx */
1011 /* CMP (register) cccc 0001 0101 xxxx xxxx xxxx xxx0 xxxx */
1012 /* CMN (register) cccc 0001 0111 xxxx xxxx xxxx xxx0 xxxx */
1013 DECODE_EMULATEX (0x0f900010, 0x01100000, emulate_rd12rn16rm0rs8_rwflags,
1014 REGS(ANY, 0, 0, 0, ANY)),
1015
1016 /* MOV (register) cccc 0001 101x xxxx xxxx xxxx xxx0 xxxx */
1017 /* MVN (register) cccc 0001 111x xxxx xxxx xxxx xxx0 xxxx */
1018 DECODE_EMULATEX (0x0fa00010, 0x01a00000, emulate_rd12rn16rm0rs8_rwflags,
1019 REGS(0, ANY, 0, 0, ANY)),
1020
1021 /* AND (register) cccc 0000 000x xxxx xxxx xxxx xxx0 xxxx */
1022 /* EOR (register) cccc 0000 001x xxxx xxxx xxxx xxx0 xxxx */
1023 /* SUB (register) cccc 0000 010x xxxx xxxx xxxx xxx0 xxxx */
1024 /* RSB (register) cccc 0000 011x xxxx xxxx xxxx xxx0 xxxx */
1025 /* ADD (register) cccc 0000 100x xxxx xxxx xxxx xxx0 xxxx */
1026 /* ADC (register) cccc 0000 101x xxxx xxxx xxxx xxx0 xxxx */
1027 /* SBC (register) cccc 0000 110x xxxx xxxx xxxx xxx0 xxxx */
1028 /* RSC (register) cccc 0000 111x xxxx xxxx xxxx xxx0 xxxx */
1029 /* ORR (register) cccc 0001 100x xxxx xxxx xxxx xxx0 xxxx */
1030 /* BIC (register) cccc 0001 110x xxxx xxxx xxxx xxx0 xxxx */
1031 DECODE_EMULATEX (0x0e000010, 0x00000000, emulate_rd12rn16rm0rs8_rwflags,
1032 REGS(ANY, ANY, 0, 0, ANY)),
1033
1034 /* TST (reg-shift reg) cccc 0001 0001 xxxx xxxx xxxx 0xx1 xxxx */
1035 /* TEQ (reg-shift reg) cccc 0001 0011 xxxx xxxx xxxx 0xx1 xxxx */
1036 /* CMP (reg-shift reg) cccc 0001 0101 xxxx xxxx xxxx 0xx1 xxxx */
1037 /* CMN (reg-shift reg) cccc 0001 0111 xxxx xxxx xxxx 0xx1 xxxx */
1038 DECODE_EMULATEX (0x0f900090, 0x01100010, emulate_rd12rn16rm0rs8_rwflags,
1039 REGS(ANY, 0, NOPC, 0, ANY)),
1040
1041 /* MOV (reg-shift reg) cccc 0001 101x xxxx xxxx xxxx 0xx1 xxxx */
1042 /* MVN (reg-shift reg) cccc 0001 111x xxxx xxxx xxxx 0xx1 xxxx */
1043 DECODE_EMULATEX (0x0fa00090, 0x01a00010, emulate_rd12rn16rm0rs8_rwflags,
1044 REGS(0, ANY, NOPC, 0, ANY)),
1045
1046 /* AND (reg-shift reg) cccc 0000 000x xxxx xxxx xxxx 0xx1 xxxx */
1047 /* EOR (reg-shift reg) cccc 0000 001x xxxx xxxx xxxx 0xx1 xxxx */
1048 /* SUB (reg-shift reg) cccc 0000 010x xxxx xxxx xxxx 0xx1 xxxx */
1049 /* RSB (reg-shift reg) cccc 0000 011x xxxx xxxx xxxx 0xx1 xxxx */
1050 /* ADD (reg-shift reg) cccc 0000 100x xxxx xxxx xxxx 0xx1 xxxx */
1051 /* ADC (reg-shift reg) cccc 0000 101x xxxx xxxx xxxx 0xx1 xxxx */
1052 /* SBC (reg-shift reg) cccc 0000 110x xxxx xxxx xxxx 0xx1 xxxx */
1053 /* RSC (reg-shift reg) cccc 0000 111x xxxx xxxx xxxx 0xx1 xxxx */
1054 /* ORR (reg-shift reg) cccc 0001 100x xxxx xxxx xxxx 0xx1 xxxx */
1055 /* BIC (reg-shift reg) cccc 0001 110x xxxx xxxx xxxx 0xx1 xxxx */
1056 DECODE_EMULATEX (0x0e000090, 0x00000010, emulate_rd12rn16rm0rs8_rwflags,
1057 REGS(ANY, ANY, NOPC, 0, ANY)),
1058
1059 DECODE_END
1060};
1061
35aa1df4
QB		 1062static enum kprobe_insn __kprobes
1063space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1064{
1065 /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx xxx0 xxxx */
1066 if ((insn & 0x0f900010) == 0x01000000) {
1067
51468ea9 1068 /* MRS cpsr : cccc 0001 0000 xxxx xxxx xxxx 0000 xxxx */
c412aba2 1069 if ((insn & 0x0ff000f0) == 0x01000000) {
983ebd93
JM		 1070 if (is_r15(insn, 12))
1071 return INSN_REJECTED; /* Rd is PC */
c412aba2
JM		 1072 asi->insn_handler = simulate_mrs;
1073 return INSN_GOOD_NO_SLOT;
1074 }
35aa1df4
QB		 1075
1076 /* SMLALxy : cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */
1077 if ((insn & 0x0ff00090) == 0x01400080)
cdc25361
JM		 1078 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn,
1079 asi);
35aa1df4
QB		 1080
1081 /* SMULWy : cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */
1082 /* SMULxy : cccc 0001 0110 xxxx xxxx xxxx 1xx0 xxxx */
1083 if ((insn & 0x0ff000b0) == 0x012000a0 ||
1084 (insn & 0x0ff00090) == 0x01600080)
1085 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
1086
1087 /* SMLAxy : cccc 0001 0000 xxxx xxxx xxxx 1xx0 xxxx : Q */
75539aea 1088 /* SMLAWy : cccc 0001 0010 xxxx xxxx xxxx 1x00 xxxx : Q */
f704a6e2
JM		 1089 if ((insn & 0x0ff00090) == 0x01000080 ||
1090 (insn & 0x0ff000b0) == 0x01200080)
1091 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
35aa1df4 1092
f704a6e2
JM		 1093 /* BXJ : cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */
1094 /* MSR : cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */
1095 /* MRS spsr : cccc 0001 0100 xxxx xxxx xxxx 0000 xxxx */
1096
1097 /* Other instruction encodings aren't yet defined */
1098 return INSN_REJECTED;
35aa1df4
QB		 1099 }
1100
1101 /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx 0xx1 xxxx */
1102 else if ((insn & 0x0f900090) == 0x01000010) {
1103
35aa1df4
QB		 1104 /* BLX(2) : cccc 0001 0010 xxxx xxxx xxxx 0011 xxxx */
1105 /* BX : cccc 0001 0010 xxxx xxxx xxxx 0001 xxxx */
1106 if ((insn & 0x0ff000d0) == 0x01200010) {
983ebd93
JM		 1107 if ((insn & 0x0ff000ff) == 0x0120003f)
1108 return INSN_REJECTED; /* BLX pc */
35aa1df4 1109 asi->insn_handler = simulate_blx2bx;
a539f5d4 1110 return INSN_GOOD_NO_SLOT;
35aa1df4
QB		 1111 }
1112
1113 /* CLZ : cccc 0001 0110 xxxx xxxx xxxx 0001 xxxx */
1114 if ((insn & 0x0ff000f0) == 0x01600010)
1115 return prep_emulate_rd12rm0(insn, asi);
1116
1117 /* QADD : cccc 0001 0000 xxxx xxxx xxxx 0101 xxxx :Q */
1118 /* QSUB : cccc 0001 0010 xxxx xxxx xxxx 0101 xxxx :Q */
1119 /* QDADD : cccc 0001 0100 xxxx xxxx xxxx 0101 xxxx :Q */
1120 /* QDSUB : cccc 0001 0110 xxxx xxxx xxxx 0101 xxxx :Q */
f704a6e2
JM		 1121 if ((insn & 0x0f9000f0) == 0x01000050)
1122 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1123
1124 /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
1125 /* SMC : cccc 0001 0110 xxxx xxxx xxxx 0111 xxxx */
1126
1127 /* Other instruction encodings aren't yet defined */
1128 return INSN_REJECTED;
35aa1df4
QB		 1129 }
1130
1131 /* cccc 0000 xxxx xxxx xxxx xxxx xxxx 1001 xxxx */
ba48d407 1132 else if ((insn & 0x0f0000f0) == 0x00000090) {
35aa1df4
QB		 1133
1134 /* MUL : cccc 0000 0000 xxxx xxxx xxxx 1001 xxxx : */
1135 /* MULS : cccc 0000 0001 xxxx xxxx xxxx 1001 xxxx :cc */
1136 /* MLA : cccc 0000 0010 xxxx xxxx xxxx 1001 xxxx : */
1137 /* MLAS : cccc 0000 0011 xxxx xxxx xxxx 1001 xxxx :cc */
1138 /* UMAAL : cccc 0000 0100 xxxx xxxx xxxx 1001 xxxx : */
ba48d407
JM		 1139 /* undef : cccc 0000 0101 xxxx xxxx xxxx 1001 xxxx : */
1140 /* MLS : cccc 0000 0110 xxxx xxxx xxxx 1001 xxxx : */
1141 /* undef : cccc 0000 0111 xxxx xxxx xxxx 1001 xxxx : */
35aa1df4
QB		 1142 /* UMULL : cccc 0000 1000 xxxx xxxx xxxx 1001 xxxx : */
1143 /* UMULLS : cccc 0000 1001 xxxx xxxx xxxx 1001 xxxx :cc */
1144 /* UMLAL : cccc 0000 1010 xxxx xxxx xxxx 1001 xxxx : */
1145 /* UMLALS : cccc 0000 1011 xxxx xxxx xxxx 1001 xxxx :cc */
1146 /* SMULL : cccc 0000 1100 xxxx xxxx xxxx 1001 xxxx : */
1147 /* SMULLS : cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx :cc */
1148 /* SMLAL : cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx : */
1149 /* SMLALS : cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx :cc */
cdc25361 1150 if ((insn & 0x00d00000) == 0x00500000)
ba48d407 1151 return INSN_REJECTED;
cdc25361
JM		 1152 else if ((insn & 0x00e00000) == 0x00000000)
1153 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
1154 else if ((insn & 0x00a00000) == 0x00200000)
1155 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1156 else
1157 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn,
1158 asi);
35aa1df4
QB		 1159 }
1160
1161 /* cccc 000x xxxx xxxx xxxx xxxx xxxx 1xx1 xxxx */
1162 else if ((insn & 0x0e000090) == 0x00000090) {
1163
1164 /* SWP : cccc 0001 0000 xxxx xxxx xxxx 1001 xxxx */
1165 /* SWPB : cccc 0001 0100 xxxx xxxx xxxx 1001 xxxx */
ec58d7f2
JM		 1166 /* ??? : cccc 0001 0x01 xxxx xxxx xxxx 1001 xxxx */
1167 /* ??? : cccc 0001 0x10 xxxx xxxx xxxx 1001 xxxx */
1168 /* ??? : cccc 0001 0x11 xxxx xxxx xxxx 1001 xxxx */
35aa1df4
QB		 1169 /* STREX : cccc 0001 1000 xxxx xxxx xxxx 1001 xxxx */
1170 /* LDREX : cccc 0001 1001 xxxx xxxx xxxx 1001 xxxx */
ec58d7f2
JM		 1171 /* STREXD: cccc 0001 1010 xxxx xxxx xxxx 1001 xxxx */
1172 /* LDREXD: cccc 0001 1011 xxxx xxxx xxxx 1001 xxxx */
1173 /* STREXB: cccc 0001 1100 xxxx xxxx xxxx 1001 xxxx */
1174 /* LDREXB: cccc 0001 1101 xxxx xxxx xxxx 1001 xxxx */
1175 /* STREXH: cccc 0001 1110 xxxx xxxx xxxx 1001 xxxx */
1176 /* LDREXH: cccc 0001 1111 xxxx xxxx xxxx 1001 xxxx */
1177
1178 /* LDRD : cccc 000x xxx0 xxxx xxxx xxxx 1101 xxxx */
1179 /* STRD : cccc 000x xxx0 xxxx xxxx xxxx 1111 xxxx */
35aa1df4
QB		 1180 /* LDRH : cccc 000x xxx1 xxxx xxxx xxxx 1011 xxxx */
1181 /* STRH : cccc 000x xxx0 xxxx xxxx xxxx 1011 xxxx */
1182 /* LDRSB : cccc 000x xxx1 xxxx xxxx xxxx 1101 xxxx */
1183 /* LDRSH : cccc 000x xxx1 xxxx xxxx xxxx 1111 xxxx */
ec58d7f2
JM		 1184 if ((insn & 0x0f0000f0) == 0x01000090) {
1185 if ((insn & 0x0fb000f0) == 0x01000090) {
1186 /* SWP/SWPB */
1187 return prep_emulate_rd12rn16rm0_wflags(insn,
1188 asi);
1189 } else {
1190 /* STREX/LDREX variants and unallocaed space */
1191 return INSN_REJECTED;
1192 }
1193
35aa1df4
QB		 1194 } else if ((insn & 0x0e1000d0) == 0x00000d0) {
1195 /* STRD/LDRD */
54823acc
JM		 1196 if ((insn & 0x0000e000) == 0x0000e000)
1197 return INSN_REJECTED; /* Rd is LR or PC */
1198 if (is_writeback(insn) && is_r15(insn, 16))
1199 return INSN_REJECTED; /* Writeback to PC */
1200
35aa1df4
QB		 1201 insn &= 0xfff00fff;
1202 insn |= 0x00002000; /* Rn = r0, Rd = r2 */
5c6b76fc
JM		 1203 if (!(insn & (1 << 22))) {
1204 /* Register index */
35aa1df4
QB		 1205 insn &= ~0xf;
1206 insn |= 1; /* Rm = r1 */
1207 }
1208 asi->insn[0] = insn;
1209 asi->insn_handler =
1210 (insn & (1 << 5)) ? emulate_strd : emulate_ldrd;
1211 return INSN_GOOD;
1212 }
1213
54823acc
JM		 1214 /* LDRH/STRH/LDRSB/LDRSH */
1215 if (is_r15(insn, 12))
1216 return INSN_REJECTED; /* Rd is PC */
35aa1df4
QB		 1217 return prep_emulate_ldr_str(insn, asi);
1218 }
1219
3535a89a 1220 return kprobe_decode_insn(insn, asi, arm_cccc_000x_table, false);
35aa1df4
QB		 1221}
1222
1223static enum kprobe_insn __kprobes
1224space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1225{
c9836777
JM		 1226 /* MOVW : cccc 0011 0000 xxxx xxxx xxxx xxxx xxxx */
1227 /* MOVT : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx */
1228 if ((insn & 0x0fb00000) == 0x03000000)
1229 return prep_emulate_rd12_modify(insn, asi);
1230
94254930
JM		 1231 /* hints : cccc 0011 0010 0000 xxxx xxxx xxxx xxxx */
1232 if ((insn & 0x0fff0000) == 0x03200000) {
1233 unsigned op2 = insn & 0x000000ff;
1234 if (op2 == 0x01 || op2 == 0x04) {
1235 /* YIELD : cccc 0011 0010 0000 xxxx xxxx 0000 0001 */
1236 /* SEV : cccc 0011 0010 0000 xxxx xxxx 0000 0100 */
1237 asi->insn[0] = insn;
1238 asi->insn_handler = emulate_none;
1239 return INSN_GOOD;
1240 } else if (op2 <= 0x03) {
1241 /* NOP : cccc 0011 0010 0000 xxxx xxxx 0000 0000 */
1242 /* WFE : cccc 0011 0010 0000 xxxx xxxx 0000 0010 */
1243 /* WFI : cccc 0011 0010 0000 xxxx xxxx 0000 0011 */
1244 /*
1245 * We make WFE and WFI true NOPs to avoid stalls due
1246 * to missing events whilst processing the probe.
1247 */
1248 asi->insn_handler = emulate_nop;
1249 return INSN_GOOD_NO_SLOT;
1250 }
1251 /* For DBG and unallocated hints it's safest to reject them */
1252 return INSN_REJECTED;
1253 }
1254
35aa1df4
QB		 1255 /*
1256 * MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx
35aa1df4
QB		 1257 * ALU op with S bit and Rd == 15 :
1258 * cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx
1259 */
ccdf2e1b 1260 if ((insn & 0x0fb00000) == 0x03200000 || /* MSR */
35aa1df4
QB		 1261 (insn & 0x0e10f000) == 0x0210f000) /* ALU s-bit, R15 */
1262 return INSN_REJECTED;
1263
1264 /*
1265 * Data processing: 32-bit Immediate
1266 * ALU op : cccc 001x xxxx xxxx xxxx xxxx xxxx xxxx
1267 * MOV : cccc 0011 101x xxxx xxxx xxxx xxxx xxxx
1268 * *S (bit 20) updates condition codes
1269 * ADC/SBC/RSC reads the C flag
1270 */
896a74e1 1271 insn &= 0xfff00fff; /* Rn = r0 and Rd = r0 */
35aa1df4 1272 asi->insn[0] = insn;
ad111ce4
JM		 1273
1274 if ((insn & 0x0f900000) == 0x03100000) {
1275 /*
1276 * TST : cccc 0011 0001 xxxx xxxx xxxx xxxx xxxx
1277 * TEQ : cccc 0011 0011 xxxx xxxx xxxx xxxx xxxx
1278 * CMP : cccc 0011 0101 xxxx xxxx xxxx xxxx xxxx
1279 * CMN : cccc 0011 0111 xxxx xxxx xxxx xxxx xxxx
1280 */
1281 asi->insn_handler = emulate_alu_tests_imm;
1282 } else {
1283 /* ALU ops which write to Rd */
1284 asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */
35aa1df4 1285 emulate_alu_imm_rwflags : emulate_alu_imm_rflags;
ad111ce4 1286 }
35aa1df4
QB		 1287 return INSN_GOOD;
1288}
1289
1290static enum kprobe_insn __kprobes
1291space_cccc_0110__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1292{
1293 /* SEL : cccc 0110 1000 xxxx xxxx xxxx 1011 xxxx GE: !!! */
1294 if ((insn & 0x0ff000f0) == 0x068000b0) {
983ebd93
JM		 1295 if (is_r15(insn, 12))
1296 return INSN_REJECTED; /* Rd is PC */
35aa1df4
QB		 1297 insn &= 0xfff00ff0; /* Rd = r0, Rn = r0 */
1298 insn |= 0x00000001; /* Rm = r1 */
1299 asi->insn[0] = insn;
1300 asi->insn_handler = emulate_sel;
1301 return INSN_GOOD;
1302 }
1303
1304 /* SSAT : cccc 0110 101x xxxx xxxx xxxx xx01 xxxx :Q */
1305 /* USAT : cccc 0110 111x xxxx xxxx xxxx xx01 xxxx :Q */
1306 /* SSAT16 : cccc 0110 1010 xxxx xxxx xxxx 0011 xxxx :Q */
1307 /* USAT16 : cccc 0110 1110 xxxx xxxx xxxx 0011 xxxx :Q */
1308 if ((insn & 0x0fa00030) == 0x06a00010 ||
1309 (insn & 0x0fb000f0) == 0x06a00030) {
983ebd93
JM		 1310 if (is_r15(insn, 12))
1311 return INSN_REJECTED; /* Rd is PC */
35aa1df4
QB		 1312 insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */
1313 asi->insn[0] = insn;
1314 asi->insn_handler = emulate_sat;
1315 return INSN_GOOD;
1316 }
1317
1318 /* REV : cccc 0110 1011 xxxx xxxx xxxx 0011 xxxx */
1319 /* REV16 : cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx */
0e384ed1 1320 /* RBIT : cccc 0110 1111 xxxx xxxx xxxx 0011 xxxx */
35aa1df4
QB		 1321 /* REVSH : cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx */
1322 if ((insn & 0x0ff00070) == 0x06b00030 ||
0e384ed1 1323 (insn & 0x0ff00070) == 0x06f00030)
35aa1df4
QB		 1324 return prep_emulate_rd12rm0(insn, asi);
1325
780b5c11 1326 /* ??? : cccc 0110 0000 xxxx xxxx xxxx xxx1 xxxx : */
35aa1df4
QB		 1327 /* SADD16 : cccc 0110 0001 xxxx xxxx xxxx 0001 xxxx :GE */
1328 /* SADDSUBX : cccc 0110 0001 xxxx xxxx xxxx 0011 xxxx :GE */
1329 /* SSUBADDX : cccc 0110 0001 xxxx xxxx xxxx 0101 xxxx :GE */
1330 /* SSUB16 : cccc 0110 0001 xxxx xxxx xxxx 0111 xxxx :GE */
1331 /* SADD8 : cccc 0110 0001 xxxx xxxx xxxx 1001 xxxx :GE */
780b5c11
JM		 1332 /* ??? : cccc 0110 0001 xxxx xxxx xxxx 1011 xxxx : */
1333 /* ??? : cccc 0110 0001 xxxx xxxx xxxx 1101 xxxx : */
35aa1df4
QB		 1334 /* SSUB8 : cccc 0110 0001 xxxx xxxx xxxx 1111 xxxx :GE */
1335 /* QADD16 : cccc 0110 0010 xxxx xxxx xxxx 0001 xxxx : */
1336 /* QADDSUBX : cccc 0110 0010 xxxx xxxx xxxx 0011 xxxx : */
1337 /* QSUBADDX : cccc 0110 0010 xxxx xxxx xxxx 0101 xxxx : */
1338 /* QSUB16 : cccc 0110 0010 xxxx xxxx xxxx 0111 xxxx : */
1339 /* QADD8 : cccc 0110 0010 xxxx xxxx xxxx 1001 xxxx : */
780b5c11
JM		 1340 /* ??? : cccc 0110 0010 xxxx xxxx xxxx 1011 xxxx : */
1341 /* ??? : cccc 0110 0010 xxxx xxxx xxxx 1101 xxxx : */
35aa1df4
QB		 1342 /* QSUB8 : cccc 0110 0010 xxxx xxxx xxxx 1111 xxxx : */
1343 /* SHADD16 : cccc 0110 0011 xxxx xxxx xxxx 0001 xxxx : */
1344 /* SHADDSUBX : cccc 0110 0011 xxxx xxxx xxxx 0011 xxxx : */
1345 /* SHSUBADDX : cccc 0110 0011 xxxx xxxx xxxx 0101 xxxx : */
1346 /* SHSUB16 : cccc 0110 0011 xxxx xxxx xxxx 0111 xxxx : */
1347 /* SHADD8 : cccc 0110 0011 xxxx xxxx xxxx 1001 xxxx : */
780b5c11
JM		 1348 /* ??? : cccc 0110 0011 xxxx xxxx xxxx 1011 xxxx : */
1349 /* ??? : cccc 0110 0011 xxxx xxxx xxxx 1101 xxxx : */
35aa1df4 1350 /* SHSUB8 : cccc 0110 0011 xxxx xxxx xxxx 1111 xxxx : */
780b5c11 1351 /* ??? : cccc 0110 0100 xxxx xxxx xxxx xxx1 xxxx : */
35aa1df4
QB		 1352 /* UADD16 : cccc 0110 0101 xxxx xxxx xxxx 0001 xxxx :GE */
1353 /* UADDSUBX : cccc 0110 0101 xxxx xxxx xxxx 0011 xxxx :GE */
1354 /* USUBADDX : cccc 0110 0101 xxxx xxxx xxxx 0101 xxxx :GE */
1355 /* USUB16 : cccc 0110 0101 xxxx xxxx xxxx 0111 xxxx :GE */
1356 /* UADD8 : cccc 0110 0101 xxxx xxxx xxxx 1001 xxxx :GE */
780b5c11
JM		 1357 /* ??? : cccc 0110 0101 xxxx xxxx xxxx 1011 xxxx : */
1358 /* ??? : cccc 0110 0101 xxxx xxxx xxxx 1101 xxxx : */
35aa1df4
QB		 1359 /* USUB8 : cccc 0110 0101 xxxx xxxx xxxx 1111 xxxx :GE */
1360 /* UQADD16 : cccc 0110 0110 xxxx xxxx xxxx 0001 xxxx : */
1361 /* UQADDSUBX : cccc 0110 0110 xxxx xxxx xxxx 0011 xxxx : */
1362 /* UQSUBADDX : cccc 0110 0110 xxxx xxxx xxxx 0101 xxxx : */
1363 /* UQSUB16 : cccc 0110 0110 xxxx xxxx xxxx 0111 xxxx : */
1364 /* UQADD8 : cccc 0110 0110 xxxx xxxx xxxx 1001 xxxx : */
780b5c11
JM		 1365 /* ??? : cccc 0110 0110 xxxx xxxx xxxx 1011 xxxx : */
1366 /* ??? : cccc 0110 0110 xxxx xxxx xxxx 1101 xxxx : */
35aa1df4
QB		 1367 /* UQSUB8 : cccc 0110 0110 xxxx xxxx xxxx 1111 xxxx : */
1368 /* UHADD16 : cccc 0110 0111 xxxx xxxx xxxx 0001 xxxx : */
1369 /* UHADDSUBX : cccc 0110 0111 xxxx xxxx xxxx 0011 xxxx : */
1370 /* UHSUBADDX : cccc 0110 0111 xxxx xxxx xxxx 0101 xxxx : */
1371 /* UHSUB16 : cccc 0110 0111 xxxx xxxx xxxx 0111 xxxx : */
1372 /* UHADD8 : cccc 0110 0111 xxxx xxxx xxxx 1001 xxxx : */
780b5c11
JM		 1373 /* ??? : cccc 0110 0111 xxxx xxxx xxxx 1011 xxxx : */
1374 /* ??? : cccc 0110 0111 xxxx xxxx xxxx 1101 xxxx : */
35aa1df4 1375 /* UHSUB8 : cccc 0110 0111 xxxx xxxx xxxx 1111 xxxx : */
780b5c11
JM		 1376 if ((insn & 0x0f800010) == 0x06000010) {
1377 if ((insn & 0x00300000) == 0x00000000 ||
1378 (insn & 0x000000e0) == 0x000000a0 ||
1379 (insn & 0x000000e0) == 0x000000c0)
1380 return INSN_REJECTED; /* Unallocated space */
1381 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1382 }
1383
35aa1df4
QB		 1384 /* PKHBT : cccc 0110 1000 xxxx xxxx xxxx x001 xxxx : */
1385 /* PKHTB : cccc 0110 1000 xxxx xxxx xxxx x101 xxxx : */
780b5c11
JM		 1386 if ((insn & 0x0ff00030) == 0x06800010)
1387 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1388
35aa1df4 1389 /* SXTAB16 : cccc 0110 1000 xxxx xxxx xxxx 0111 xxxx : */
8dd7cfbe 1390 /* SXTB16 : cccc 0110 1000 1111 xxxx xxxx 0111 xxxx : */
780b5c11 1391 /* ??? : cccc 0110 1001 xxxx xxxx xxxx 0111 xxxx : */
35aa1df4 1392 /* SXTAB : cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx : */
8dd7cfbe 1393 /* SXTB : cccc 0110 1010 1111 xxxx xxxx 0111 xxxx : */
35aa1df4 1394 /* SXTAH : cccc 0110 1011 xxxx xxxx xxxx 0111 xxxx : */
8dd7cfbe 1395 /* SXTH : cccc 0110 1011 1111 xxxx xxxx 0111 xxxx : */
35aa1df4 1396 /* UXTAB16 : cccc 0110 1100 xxxx xxxx xxxx 0111 xxxx : */
8dd7cfbe 1397 /* UXTB16 : cccc 0110 1100 1111 xxxx xxxx 0111 xxxx : */
780b5c11 1398 /* ??? : cccc 0110 1101 xxxx xxxx xxxx 0111 xxxx : */
35aa1df4 1399 /* UXTAB : cccc 0110 1110 xxxx xxxx xxxx 0111 xxxx : */
8dd7cfbe 1400 /* UXTB : cccc 0110 1110 1111 xxxx xxxx 0111 xxxx : */
35aa1df4 1401 /* UXTAH : cccc 0110 1111 xxxx xxxx xxxx 0111 xxxx : */
8dd7cfbe 1402 /* UXTH : cccc 0110 1111 1111 xxxx xxxx 0111 xxxx : */
780b5c11
JM		 1403 if ((insn & 0x0f8000f0) == 0x06800070) {
1404 if ((insn & 0x00300000) == 0x00100000)
1405 return INSN_REJECTED; /* Unallocated space */
8dd7cfbe 1406
cdc25361 1407 if ((insn & 0x000f0000) == 0x000f0000)
8dd7cfbe 1408 return prep_emulate_rd12rm0(insn, asi);
cdc25361 1409 else
8dd7cfbe 1410 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
780b5c11
JM		 1411 }
1412
1413 /* Other instruction encodings aren't yet defined */
1414 return INSN_REJECTED;
35aa1df4
QB		 1415}
1416
1417static enum kprobe_insn __kprobes
1418space_cccc_0111__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1419{
1420 /* Undef : cccc 0111 1111 xxxx xxxx xxxx 1111 xxxx */
1421 if ((insn & 0x0ff000f0) == 0x03f000f0)
1422 return INSN_REJECTED;
1423
35aa1df4
QB		 1424 /* SMLALD : cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */
1425 /* SMLSLD : cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */
1426 if ((insn & 0x0ff00090) == 0x07400010)
1427 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
1428
1429 /* SMLAD : cccc 0111 0000 xxxx xxxx xxxx 00x1 xxxx :Q */
038c3839 1430 /* SMUAD : cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx :Q */
35aa1df4 1431 /* SMLSD : cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx :Q */
038c3839 1432 /* SMUSD : cccc 0111 0000 xxxx 1111 xxxx 01x1 xxxx : */
35aa1df4 1433 /* SMMLA : cccc 0111 0101 xxxx xxxx xxxx 00x1 xxxx : */
038c3839 1434 /* SMMUL : cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx : */
c6e4ae32
JM		 1435 /* USADA8 : cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx : */
1436 /* USAD8 : cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx : */
35aa1df4 1437 if ((insn & 0x0ff00090) == 0x07000010 ||
c6e4ae32
JM		 1438 (insn & 0x0ff000d0) == 0x07500010 ||
1439 (insn & 0x0ff000f0) == 0x07800010) {
038c3839 1440
cdc25361 1441 if ((insn & 0x0000f000) == 0x0000f000)
038c3839 1442 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
cdc25361 1443 else
038c3839 1444 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
038c3839
JM		 1445 }
1446
1447 /* SMMLS : cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx : */
1448 if ((insn & 0x0ff000d0) == 0x075000d0)
35aa1df4
QB		 1449 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1450
20e8155e
JM		 1451 /* SBFX : cccc 0111 101x xxxx xxxx xxxx x101 xxxx : */
1452 /* UBFX : cccc 0111 111x xxxx xxxx xxxx x101 xxxx : */
1453 if ((insn & 0x0fa00070) == 0x07a00050)
1454 return prep_emulate_rd12rm0(insn, asi);
1455
1456 /* BFI : cccc 0111 110x xxxx xxxx xxxx x001 xxxx : */
1457 /* BFC : cccc 0111 110x xxxx xxxx xxxx x001 1111 : */
1458 if ((insn & 0x0fe00070) == 0x07c00010) {
1459
1460 if ((insn & 0x0000000f) == 0x0000000f)
1461 return prep_emulate_rd12_modify(insn, asi);
1462 else
1463 return prep_emulate_rd12rn0_modify(insn, asi);
1464 }
1465
038c3839 1466 return INSN_REJECTED;
35aa1df4
QB		 1467}
1468
1469static enum kprobe_insn __kprobes
1470space_cccc_01xx(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1471{
1472 /* LDR : cccc 01xx x0x1 xxxx xxxx xxxx xxxx xxxx */
1473 /* LDRB : cccc 01xx x1x1 xxxx xxxx xxxx xxxx xxxx */
1474 /* LDRBT : cccc 01x0 x111 xxxx xxxx xxxx xxxx xxxx */
1475 /* LDRT : cccc 01x0 x011 xxxx xxxx xxxx xxxx xxxx */
1476 /* STR : cccc 01xx x0x0 xxxx xxxx xxxx xxxx xxxx */
1477 /* STRB : cccc 01xx x1x0 xxxx xxxx xxxx xxxx xxxx */
1478 /* STRBT : cccc 01x0 x110 xxxx xxxx xxxx xxxx xxxx */
1479 /* STRT : cccc 01x0 x010 xxxx xxxx xxxx xxxx xxxx */
81ff5720
JM		 1480
1481 if ((insn & 0x00500000) == 0x00500000 && is_r15(insn, 12))
1482 return INSN_REJECTED; /* LDRB into PC */
1483
35aa1df4
QB		 1484 return prep_emulate_ldr_str(insn, asi);
1485}
1486
1487static enum kprobe_insn __kprobes
1488space_cccc_100x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1489{
1490 /* LDM(2) : cccc 100x x101 xxxx 0xxx xxxx xxxx xxxx */
1491 /* LDM(3) : cccc 100x x1x1 xxxx 1xxx xxxx xxxx xxxx */
1492 if ((insn & 0x0e708000) == 0x85000000 ||
1493 (insn & 0x0e508000) == 0x85010000)
1494 return INSN_REJECTED;
1495
1496 /* LDM(1) : cccc 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
1497 /* STM(1) : cccc 100x x0x0 xxxx xxxx xxxx xxxx xxxx */
235a4ce7
JM		 1498
1499 /*
1500 * Make the instruction unconditional because the new emulation
1501 * functions don't bother to setup the PSR context.
1502 */
1503 insn = (insn | 0xe0000000) & ~0x10000000;
1504 return kprobe_decode_ldmstm(insn, asi);
35aa1df4
QB		 1505}
1506
1507static enum kprobe_insn __kprobes
1508space_cccc_101x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1509{
1510 /* B : cccc 1010 xxxx xxxx xxxx xxxx xxxx xxxx */
1511 /* BL : cccc 1011 xxxx xxxx xxxx xxxx xxxx xxxx */
35aa1df4 1512 asi->insn_handler = simulate_bbl;
a539f5d4 1513 return INSN_GOOD_NO_SLOT;
35aa1df4
QB		 1514}
1515
1516static enum kprobe_insn __kprobes
ac211c69 1517space_cccc_11xx(kprobe_opcode_t insn, struct arch_specific_insn *asi)
35aa1df4 1518{
ac211c69 1519 /* Coprocessor instructions... */
35aa1df4
QB		 1520 /* MCRR : cccc 1100 0100 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */
1521 /* MRRC : cccc 1100 0101 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */
ac211c69
JM		 1522 /* LDC : cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
1523 /* STC : cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
1524 /* CDP : cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
1525 /* MCR : cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
1526 /* MRC : cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
35aa1df4 1527
ac211c69 1528 /* SVC : cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */
35aa1df4 1529
fa1a03b4 1530 return INSN_REJECTED;
35aa1df4
QB		 1531}
1532
c6a7d97d
JM		 1533static void __kprobes arm_singlestep(struct kprobe *p, struct pt_regs *regs)
1534{
1535 regs->ARM_pc += 4;
1536 p->ainsn.insn_handler(p, regs);
1537}
1538
35aa1df4
QB		 1539/* Return:
1540 * INSN_REJECTED If instruction is one not allowed to kprobe,
1541 * INSN_GOOD If instruction is supported and uses instruction slot,
1542 * INSN_GOOD_NO_SLOT If instruction is supported but doesn't use its slot.
1543 *
1544 * For instructions we don't want to kprobe (INSN_REJECTED return result):
1545 * These are generally ones that modify the processor state making
1546 * them "hard" to simulate such as switches processor modes or
1547 * make accesses in alternate modes. Any of these could be simulated
1548 * if the work was put into it, but low return considering they
1549 * should also be very rare.
1550 */
1551enum kprobe_insn __kprobes
1552arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1553{
c6a7d97d 1554 asi->insn_singlestep = arm_singlestep;
0ab4c02d 1555 asi->insn_check_cc = kprobe_condition_checks[insn>>28];
35aa1df4
QB		 1556 asi->insn[1] = KPROBE_RETURN_INSTRUCTION;
1557
cdc25361 1558 if ((insn & 0xf0000000) == 0xf0000000)
35aa1df4 1559
9a5c1284 1560 return kprobe_decode_insn(insn, asi, arm_1111_table, false);
35aa1df4 1561
cdc25361 1562 else if ((insn & 0x0e000000) == 0x00000000)
35aa1df4
QB		 1563
1564 return space_cccc_000x(insn, asi);
1565
cdc25361 1566 else if ((insn & 0x0e000000) == 0x02000000)
35aa1df4
QB		 1567
1568 return space_cccc_001x(insn, asi);
1569
cdc25361 1570 else if ((insn & 0x0f000010) == 0x06000010)
35aa1df4
QB		 1571
1572 return space_cccc_0110__1(insn, asi);
1573
cdc25361 1574 else if ((insn & 0x0f000010) == 0x07000010)
35aa1df4
QB		 1575
1576 return space_cccc_0111__1(insn, asi);
1577
cdc25361 1578 else if ((insn & 0x0c000000) == 0x04000000)
35aa1df4
QB		 1579
1580 return space_cccc_01xx(insn, asi);
1581
cdc25361 1582 else if ((insn & 0x0e000000) == 0x08000000)
35aa1df4
QB		 1583
1584 return space_cccc_100x(insn, asi);
1585
cdc25361 1586 else if ((insn & 0x0e000000) == 0x0a000000)
35aa1df4
QB		 1587
1588 return space_cccc_101x(insn, asi);
1589
ac211c69 1590 return space_cccc_11xx(insn, asi);
35aa1df4 1591}
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