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Commit | Line | Data |
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1b8873a0 JI |
1 | #undef DEBUG |
2 | ||
3 | /* | |
4 | * ARM performance counter support. | |
5 | * | |
6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | |
43eab878 | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
796d1295 | 8 | * |
1b8873a0 JI |
9 | * This code is based on the sparc64 perf event code, which is in turn based |
10 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace | |
11 | * code. | |
12 | */ | |
13 | #define pr_fmt(fmt) "hw perfevents: " fmt | |
14 | ||
15 | #include <linux/interrupt.h> | |
16 | #include <linux/kernel.h> | |
181193f3 | 17 | #include <linux/module.h> |
1b8873a0 | 18 | #include <linux/perf_event.h> |
49c006b9 | 19 | #include <linux/platform_device.h> |
1b8873a0 JI |
20 | #include <linux/spinlock.h> |
21 | #include <linux/uaccess.h> | |
22 | ||
23 | #include <asm/cputype.h> | |
24 | #include <asm/irq.h> | |
25 | #include <asm/irq_regs.h> | |
26 | #include <asm/pmu.h> | |
27 | #include <asm/stacktrace.h> | |
28 | ||
49c006b9 | 29 | static struct platform_device *pmu_device; |
1b8873a0 JI |
30 | |
31 | /* | |
32 | * Hardware lock to serialize accesses to PMU registers. Needed for the | |
33 | * read/modify/write sequences. | |
34 | */ | |
961ec6da | 35 | static DEFINE_RAW_SPINLOCK(pmu_lock); |
1b8873a0 JI |
36 | |
37 | /* | |
ecf5a893 | 38 | * ARMv6 supports a maximum of 3 events, starting from index 0. If we add |
1b8873a0 JI |
39 | * another platform that supports more, we need to increase this to be the |
40 | * largest of all platforms. | |
796d1295 JP |
41 | * |
42 | * ARMv7 supports up to 32 events: | |
43 | * cycle counter CCNT + 31 events counters CNT0..30. | |
44 | * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters. | |
1b8873a0 | 45 | */ |
ecf5a893 | 46 | #define ARMPMU_MAX_HWEVENTS 32 |
1b8873a0 JI |
47 | |
48 | /* The events for a given CPU. */ | |
49 | struct cpu_hw_events { | |
50 | /* | |
ecf5a893 | 51 | * The events that are active on the CPU for the given index. |
1b8873a0 JI |
52 | */ |
53 | struct perf_event *events[ARMPMU_MAX_HWEVENTS]; | |
54 | ||
55 | /* | |
56 | * A 1 bit for an index indicates that the counter is being used for | |
57 | * an event. A 0 means that the counter can be used. | |
58 | */ | |
59 | unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)]; | |
1b8873a0 | 60 | }; |
4d6b7a77 | 61 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
181193f3 | 62 | |
1b8873a0 | 63 | struct arm_pmu { |
181193f3 | 64 | enum arm_perf_pmu_ids id; |
0b390e21 | 65 | cpumask_t active_irqs; |
62994831 | 66 | const char *name; |
1b8873a0 JI |
67 | irqreturn_t (*handle_irq)(int irq_num, void *dev); |
68 | void (*enable)(struct hw_perf_event *evt, int idx); | |
69 | void (*disable)(struct hw_perf_event *evt, int idx); | |
1b8873a0 JI |
70 | int (*get_event_idx)(struct cpu_hw_events *cpuc, |
71 | struct hw_perf_event *hwc); | |
05d22fde WD |
72 | int (*set_event_filter)(struct hw_perf_event *evt, |
73 | struct perf_event_attr *attr); | |
1b8873a0 JI |
74 | u32 (*read_counter)(int idx); |
75 | void (*write_counter)(int idx, u32 val); | |
76 | void (*start)(void); | |
77 | void (*stop)(void); | |
574b69cb | 78 | void (*reset)(void *); |
84fee97a WD |
79 | const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] |
80 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
81 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
82 | const unsigned (*event_map)[PERF_COUNT_HW_MAX]; | |
83 | u32 raw_event_mask; | |
1b8873a0 | 84 | int num_events; |
03b7898d MR |
85 | atomic_t active_events; |
86 | struct mutex reserve_mutex; | |
1b8873a0 JI |
87 | u64 max_period; |
88 | }; | |
89 | ||
90 | /* Set at runtime when we know what CPU type we are. */ | |
a6c93afe | 91 | static struct arm_pmu *armpmu; |
1b8873a0 | 92 | |
181193f3 WD |
93 | enum arm_perf_pmu_ids |
94 | armpmu_get_pmu_id(void) | |
95 | { | |
96 | int id = -ENODEV; | |
97 | ||
98 | if (armpmu != NULL) | |
99 | id = armpmu->id; | |
100 | ||
101 | return id; | |
102 | } | |
103 | EXPORT_SYMBOL_GPL(armpmu_get_pmu_id); | |
104 | ||
929f5199 WD |
105 | int |
106 | armpmu_get_max_events(void) | |
107 | { | |
108 | int max_events = 0; | |
109 | ||
110 | if (armpmu != NULL) | |
111 | max_events = armpmu->num_events; | |
112 | ||
113 | return max_events; | |
114 | } | |
115 | EXPORT_SYMBOL_GPL(armpmu_get_max_events); | |
116 | ||
3bf101ba MF |
117 | int perf_num_counters(void) |
118 | { | |
119 | return armpmu_get_max_events(); | |
120 | } | |
121 | EXPORT_SYMBOL_GPL(perf_num_counters); | |
122 | ||
1b8873a0 JI |
123 | #define HW_OP_UNSUPPORTED 0xFFFF |
124 | ||
125 | #define C(_x) \ | |
126 | PERF_COUNT_HW_CACHE_##_x | |
127 | ||
128 | #define CACHE_OP_UNSUPPORTED 0xFFFF | |
129 | ||
1b8873a0 JI |
130 | static int |
131 | armpmu_map_cache_event(u64 config) | |
132 | { | |
133 | unsigned int cache_type, cache_op, cache_result, ret; | |
134 | ||
135 | cache_type = (config >> 0) & 0xff; | |
136 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
137 | return -EINVAL; | |
138 | ||
139 | cache_op = (config >> 8) & 0xff; | |
140 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
141 | return -EINVAL; | |
142 | ||
143 | cache_result = (config >> 16) & 0xff; | |
144 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
145 | return -EINVAL; | |
146 | ||
84fee97a | 147 | ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result]; |
1b8873a0 JI |
148 | |
149 | if (ret == CACHE_OP_UNSUPPORTED) | |
150 | return -ENOENT; | |
151 | ||
152 | return ret; | |
153 | } | |
154 | ||
84fee97a WD |
155 | static int |
156 | armpmu_map_event(u64 config) | |
157 | { | |
158 | int mapping = (*armpmu->event_map)[config]; | |
159 | return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping; | |
160 | } | |
161 | ||
162 | static int | |
163 | armpmu_map_raw_event(u64 config) | |
164 | { | |
165 | return (int)(config & armpmu->raw_event_mask); | |
166 | } | |
167 | ||
1b8873a0 JI |
168 | static int |
169 | armpmu_event_set_period(struct perf_event *event, | |
170 | struct hw_perf_event *hwc, | |
171 | int idx) | |
172 | { | |
e7850595 | 173 | s64 left = local64_read(&hwc->period_left); |
1b8873a0 JI |
174 | s64 period = hwc->sample_period; |
175 | int ret = 0; | |
176 | ||
177 | if (unlikely(left <= -period)) { | |
178 | left = period; | |
e7850595 | 179 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
180 | hwc->last_period = period; |
181 | ret = 1; | |
182 | } | |
183 | ||
184 | if (unlikely(left <= 0)) { | |
185 | left += period; | |
e7850595 | 186 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
187 | hwc->last_period = period; |
188 | ret = 1; | |
189 | } | |
190 | ||
191 | if (left > (s64)armpmu->max_period) | |
192 | left = armpmu->max_period; | |
193 | ||
e7850595 | 194 | local64_set(&hwc->prev_count, (u64)-left); |
1b8873a0 JI |
195 | |
196 | armpmu->write_counter(idx, (u64)(-left) & 0xffffffff); | |
197 | ||
198 | perf_event_update_userpage(event); | |
199 | ||
200 | return ret; | |
201 | } | |
202 | ||
203 | static u64 | |
204 | armpmu_event_update(struct perf_event *event, | |
205 | struct hw_perf_event *hwc, | |
a737823d | 206 | int idx, int overflow) |
1b8873a0 | 207 | { |
a737823d | 208 | u64 delta, prev_raw_count, new_raw_count; |
1b8873a0 JI |
209 | |
210 | again: | |
e7850595 | 211 | prev_raw_count = local64_read(&hwc->prev_count); |
1b8873a0 JI |
212 | new_raw_count = armpmu->read_counter(idx); |
213 | ||
e7850595 | 214 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
1b8873a0 JI |
215 | new_raw_count) != prev_raw_count) |
216 | goto again; | |
217 | ||
a737823d WD |
218 | new_raw_count &= armpmu->max_period; |
219 | prev_raw_count &= armpmu->max_period; | |
220 | ||
221 | if (overflow) | |
6759788b | 222 | delta = armpmu->max_period - prev_raw_count + new_raw_count + 1; |
a737823d WD |
223 | else |
224 | delta = new_raw_count - prev_raw_count; | |
1b8873a0 | 225 | |
e7850595 PZ |
226 | local64_add(delta, &event->count); |
227 | local64_sub(delta, &hwc->period_left); | |
1b8873a0 JI |
228 | |
229 | return new_raw_count; | |
230 | } | |
231 | ||
232 | static void | |
a4eaf7f1 | 233 | armpmu_read(struct perf_event *event) |
1b8873a0 | 234 | { |
1b8873a0 | 235 | struct hw_perf_event *hwc = &event->hw; |
1b8873a0 | 236 | |
a4eaf7f1 PZ |
237 | /* Don't read disabled counters! */ |
238 | if (hwc->idx < 0) | |
239 | return; | |
1b8873a0 | 240 | |
a737823d | 241 | armpmu_event_update(event, hwc, hwc->idx, 0); |
1b8873a0 JI |
242 | } |
243 | ||
244 | static void | |
a4eaf7f1 | 245 | armpmu_stop(struct perf_event *event, int flags) |
1b8873a0 JI |
246 | { |
247 | struct hw_perf_event *hwc = &event->hw; | |
248 | ||
a4eaf7f1 PZ |
249 | /* |
250 | * ARM pmu always has to update the counter, so ignore | |
251 | * PERF_EF_UPDATE, see comments in armpmu_start(). | |
252 | */ | |
253 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
254 | armpmu->disable(hwc, hwc->idx); | |
255 | barrier(); /* why? */ | |
a737823d | 256 | armpmu_event_update(event, hwc, hwc->idx, 0); |
a4eaf7f1 PZ |
257 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
258 | } | |
1b8873a0 JI |
259 | } |
260 | ||
261 | static void | |
a4eaf7f1 | 262 | armpmu_start(struct perf_event *event, int flags) |
1b8873a0 JI |
263 | { |
264 | struct hw_perf_event *hwc = &event->hw; | |
265 | ||
a4eaf7f1 PZ |
266 | /* |
267 | * ARM pmu always has to reprogram the period, so ignore | |
268 | * PERF_EF_RELOAD, see the comment below. | |
269 | */ | |
270 | if (flags & PERF_EF_RELOAD) | |
271 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
272 | ||
273 | hwc->state = 0; | |
1b8873a0 JI |
274 | /* |
275 | * Set the period again. Some counters can't be stopped, so when we | |
a4eaf7f1 | 276 | * were stopped we simply disabled the IRQ source and the counter |
1b8873a0 JI |
277 | * may have been left counting. If we don't do this step then we may |
278 | * get an interrupt too soon or *way* too late if the overflow has | |
279 | * happened since disabling. | |
280 | */ | |
281 | armpmu_event_set_period(event, hwc, hwc->idx); | |
282 | armpmu->enable(hwc, hwc->idx); | |
283 | } | |
284 | ||
a4eaf7f1 PZ |
285 | static void |
286 | armpmu_del(struct perf_event *event, int flags) | |
287 | { | |
288 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
289 | struct hw_perf_event *hwc = &event->hw; | |
290 | int idx = hwc->idx; | |
291 | ||
292 | WARN_ON(idx < 0); | |
293 | ||
a4eaf7f1 PZ |
294 | armpmu_stop(event, PERF_EF_UPDATE); |
295 | cpuc->events[idx] = NULL; | |
296 | clear_bit(idx, cpuc->used_mask); | |
297 | ||
298 | perf_event_update_userpage(event); | |
299 | } | |
300 | ||
1b8873a0 | 301 | static int |
a4eaf7f1 | 302 | armpmu_add(struct perf_event *event, int flags) |
1b8873a0 JI |
303 | { |
304 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
305 | struct hw_perf_event *hwc = &event->hw; | |
306 | int idx; | |
307 | int err = 0; | |
308 | ||
33696fc0 | 309 | perf_pmu_disable(event->pmu); |
24cd7f54 | 310 | |
1b8873a0 JI |
311 | /* If we don't have a space for the counter then finish early. */ |
312 | idx = armpmu->get_event_idx(cpuc, hwc); | |
313 | if (idx < 0) { | |
314 | err = idx; | |
315 | goto out; | |
316 | } | |
317 | ||
318 | /* | |
319 | * If there is an event in the counter we are going to use then make | |
320 | * sure it is disabled. | |
321 | */ | |
322 | event->hw.idx = idx; | |
323 | armpmu->disable(hwc, idx); | |
324 | cpuc->events[idx] = event; | |
1b8873a0 | 325 | |
a4eaf7f1 PZ |
326 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
327 | if (flags & PERF_EF_START) | |
328 | armpmu_start(event, PERF_EF_RELOAD); | |
1b8873a0 JI |
329 | |
330 | /* Propagate our changes to the userspace mapping. */ | |
331 | perf_event_update_userpage(event); | |
332 | ||
333 | out: | |
33696fc0 | 334 | perf_pmu_enable(event->pmu); |
1b8873a0 JI |
335 | return err; |
336 | } | |
337 | ||
b0a873eb | 338 | static struct pmu pmu; |
1b8873a0 JI |
339 | |
340 | static int | |
341 | validate_event(struct cpu_hw_events *cpuc, | |
342 | struct perf_event *event) | |
343 | { | |
344 | struct hw_perf_event fake_event = event->hw; | |
7b9f72c6 | 345 | struct pmu *leader_pmu = event->group_leader->pmu; |
1b8873a0 | 346 | |
7b9f72c6 | 347 | if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF) |
65b4711f | 348 | return 1; |
1b8873a0 JI |
349 | |
350 | return armpmu->get_event_idx(cpuc, &fake_event) >= 0; | |
351 | } | |
352 | ||
353 | static int | |
354 | validate_group(struct perf_event *event) | |
355 | { | |
356 | struct perf_event *sibling, *leader = event->group_leader; | |
357 | struct cpu_hw_events fake_pmu; | |
358 | ||
359 | memset(&fake_pmu, 0, sizeof(fake_pmu)); | |
360 | ||
361 | if (!validate_event(&fake_pmu, leader)) | |
362 | return -ENOSPC; | |
363 | ||
364 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { | |
365 | if (!validate_event(&fake_pmu, sibling)) | |
366 | return -ENOSPC; | |
367 | } | |
368 | ||
369 | if (!validate_event(&fake_pmu, event)) | |
370 | return -ENOSPC; | |
371 | ||
372 | return 0; | |
373 | } | |
374 | ||
0e25a5c9 RV |
375 | static irqreturn_t armpmu_platform_irq(int irq, void *dev) |
376 | { | |
377 | struct arm_pmu_platdata *plat = dev_get_platdata(&pmu_device->dev); | |
378 | ||
379 | return plat->handle_irq(irq, dev, armpmu->handle_irq); | |
380 | } | |
381 | ||
0b390e21 WD |
382 | static void |
383 | armpmu_release_hardware(void) | |
384 | { | |
385 | int i, irq, irqs; | |
386 | ||
387 | irqs = min(pmu_device->num_resources, num_possible_cpus()); | |
388 | ||
389 | for (i = 0; i < irqs; ++i) { | |
390 | if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs)) | |
391 | continue; | |
392 | irq = platform_get_irq(pmu_device, i); | |
393 | if (irq >= 0) | |
394 | free_irq(irq, NULL); | |
395 | } | |
396 | ||
397 | armpmu->stop(); | |
398 | release_pmu(ARM_PMU_DEVICE_CPU); | |
399 | } | |
400 | ||
1b8873a0 JI |
401 | static int |
402 | armpmu_reserve_hardware(void) | |
403 | { | |
0e25a5c9 RV |
404 | struct arm_pmu_platdata *plat; |
405 | irq_handler_t handle_irq; | |
b0e89590 | 406 | int i, err, irq, irqs; |
1b8873a0 | 407 | |
b0e89590 WD |
408 | err = reserve_pmu(ARM_PMU_DEVICE_CPU); |
409 | if (err) { | |
1b8873a0 | 410 | pr_warning("unable to reserve pmu\n"); |
b0e89590 | 411 | return err; |
1b8873a0 JI |
412 | } |
413 | ||
0e25a5c9 RV |
414 | plat = dev_get_platdata(&pmu_device->dev); |
415 | if (plat && plat->handle_irq) | |
416 | handle_irq = armpmu_platform_irq; | |
417 | else | |
418 | handle_irq = armpmu->handle_irq; | |
419 | ||
0b390e21 | 420 | irqs = min(pmu_device->num_resources, num_possible_cpus()); |
b0e89590 | 421 | if (irqs < 1) { |
1b8873a0 JI |
422 | pr_err("no irqs for PMUs defined\n"); |
423 | return -ENODEV; | |
424 | } | |
425 | ||
b0e89590 | 426 | for (i = 0; i < irqs; ++i) { |
0b390e21 | 427 | err = 0; |
49c006b9 WD |
428 | irq = platform_get_irq(pmu_device, i); |
429 | if (irq < 0) | |
430 | continue; | |
431 | ||
b0e89590 WD |
432 | /* |
433 | * If we have a single PMU interrupt that we can't shift, | |
434 | * assume that we're running on a uniprocessor machine and | |
0b390e21 | 435 | * continue. Otherwise, continue without this interrupt. |
b0e89590 | 436 | */ |
0b390e21 WD |
437 | if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { |
438 | pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", | |
439 | irq, i); | |
440 | continue; | |
b0e89590 WD |
441 | } |
442 | ||
0e25a5c9 | 443 | err = request_irq(irq, handle_irq, |
ddee87f2 | 444 | IRQF_DISABLED | IRQF_NOBALANCING, |
b0e89590 | 445 | "arm-pmu", NULL); |
1b8873a0 | 446 | if (err) { |
b0e89590 WD |
447 | pr_err("unable to request IRQ%d for ARM PMU counters\n", |
448 | irq); | |
0b390e21 WD |
449 | armpmu_release_hardware(); |
450 | return err; | |
1b8873a0 | 451 | } |
1b8873a0 | 452 | |
0b390e21 | 453 | cpumask_set_cpu(i, &armpmu->active_irqs); |
49c006b9 | 454 | } |
1b8873a0 | 455 | |
0b390e21 | 456 | return 0; |
1b8873a0 JI |
457 | } |
458 | ||
1b8873a0 JI |
459 | static void |
460 | hw_perf_event_destroy(struct perf_event *event) | |
461 | { | |
03b7898d MR |
462 | atomic_t *active_events = &armpmu->active_events; |
463 | struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex; | |
464 | ||
465 | if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) { | |
1b8873a0 | 466 | armpmu_release_hardware(); |
03b7898d | 467 | mutex_unlock(pmu_reserve_mutex); |
1b8873a0 JI |
468 | } |
469 | } | |
470 | ||
05d22fde WD |
471 | static int |
472 | event_requires_mode_exclusion(struct perf_event_attr *attr) | |
473 | { | |
474 | return attr->exclude_idle || attr->exclude_user || | |
475 | attr->exclude_kernel || attr->exclude_hv; | |
476 | } | |
477 | ||
1b8873a0 JI |
478 | static int |
479 | __hw_perf_event_init(struct perf_event *event) | |
480 | { | |
481 | struct hw_perf_event *hwc = &event->hw; | |
482 | int mapping, err; | |
483 | ||
484 | /* Decode the generic type into an ARM event identifier. */ | |
485 | if (PERF_TYPE_HARDWARE == event->attr.type) { | |
84fee97a | 486 | mapping = armpmu_map_event(event->attr.config); |
1b8873a0 JI |
487 | } else if (PERF_TYPE_HW_CACHE == event->attr.type) { |
488 | mapping = armpmu_map_cache_event(event->attr.config); | |
489 | } else if (PERF_TYPE_RAW == event->attr.type) { | |
84fee97a | 490 | mapping = armpmu_map_raw_event(event->attr.config); |
1b8873a0 JI |
491 | } else { |
492 | pr_debug("event type %x not supported\n", event->attr.type); | |
493 | return -EOPNOTSUPP; | |
494 | } | |
495 | ||
496 | if (mapping < 0) { | |
497 | pr_debug("event %x:%llx not supported\n", event->attr.type, | |
498 | event->attr.config); | |
499 | return mapping; | |
500 | } | |
501 | ||
05d22fde WD |
502 | /* |
503 | * We don't assign an index until we actually place the event onto | |
504 | * hardware. Use -1 to signify that we haven't decided where to put it | |
505 | * yet. For SMP systems, each core has it's own PMU so we can't do any | |
506 | * clever allocation or constraints checking at this point. | |
507 | */ | |
508 | hwc->idx = -1; | |
509 | hwc->config_base = 0; | |
510 | hwc->config = 0; | |
511 | hwc->event_base = 0; | |
512 | ||
1b8873a0 JI |
513 | /* |
514 | * Check whether we need to exclude the counter from certain modes. | |
1b8873a0 | 515 | */ |
05d22fde WD |
516 | if ((!armpmu->set_event_filter || |
517 | armpmu->set_event_filter(hwc, &event->attr)) && | |
518 | event_requires_mode_exclusion(&event->attr)) { | |
1b8873a0 JI |
519 | pr_debug("ARM performance counters do not support " |
520 | "mode exclusion\n"); | |
521 | return -EPERM; | |
522 | } | |
523 | ||
524 | /* | |
05d22fde | 525 | * Store the event encoding into the config_base field. |
1b8873a0 | 526 | */ |
05d22fde | 527 | hwc->config_base |= (unsigned long)mapping; |
1b8873a0 JI |
528 | |
529 | if (!hwc->sample_period) { | |
530 | hwc->sample_period = armpmu->max_period; | |
531 | hwc->last_period = hwc->sample_period; | |
e7850595 | 532 | local64_set(&hwc->period_left, hwc->sample_period); |
1b8873a0 JI |
533 | } |
534 | ||
535 | err = 0; | |
536 | if (event->group_leader != event) { | |
537 | err = validate_group(event); | |
538 | if (err) | |
539 | return -EINVAL; | |
540 | } | |
541 | ||
542 | return err; | |
543 | } | |
544 | ||
b0a873eb | 545 | static int armpmu_event_init(struct perf_event *event) |
1b8873a0 JI |
546 | { |
547 | int err = 0; | |
03b7898d | 548 | atomic_t *active_events = &armpmu->active_events; |
1b8873a0 | 549 | |
b0a873eb PZ |
550 | switch (event->attr.type) { |
551 | case PERF_TYPE_RAW: | |
552 | case PERF_TYPE_HARDWARE: | |
553 | case PERF_TYPE_HW_CACHE: | |
554 | break; | |
555 | ||
556 | default: | |
557 | return -ENOENT; | |
558 | } | |
559 | ||
1b8873a0 JI |
560 | event->destroy = hw_perf_event_destroy; |
561 | ||
03b7898d MR |
562 | if (!atomic_inc_not_zero(active_events)) { |
563 | mutex_lock(&armpmu->reserve_mutex); | |
564 | if (atomic_read(active_events) == 0) | |
1b8873a0 | 565 | err = armpmu_reserve_hardware(); |
1b8873a0 JI |
566 | |
567 | if (!err) | |
03b7898d MR |
568 | atomic_inc(active_events); |
569 | mutex_unlock(&armpmu->reserve_mutex); | |
1b8873a0 JI |
570 | } |
571 | ||
572 | if (err) | |
b0a873eb | 573 | return err; |
1b8873a0 JI |
574 | |
575 | err = __hw_perf_event_init(event); | |
576 | if (err) | |
577 | hw_perf_event_destroy(event); | |
578 | ||
b0a873eb | 579 | return err; |
1b8873a0 JI |
580 | } |
581 | ||
a4eaf7f1 | 582 | static void armpmu_enable(struct pmu *pmu) |
1b8873a0 JI |
583 | { |
584 | /* Enable all of the perf events on hardware. */ | |
f4f38430 | 585 | int idx, enabled = 0; |
1b8873a0 JI |
586 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
587 | ||
ecf5a893 | 588 | for (idx = 0; idx < armpmu->num_events; ++idx) { |
1b8873a0 JI |
589 | struct perf_event *event = cpuc->events[idx]; |
590 | ||
591 | if (!event) | |
592 | continue; | |
593 | ||
594 | armpmu->enable(&event->hw, idx); | |
f4f38430 | 595 | enabled = 1; |
1b8873a0 JI |
596 | } |
597 | ||
f4f38430 WD |
598 | if (enabled) |
599 | armpmu->start(); | |
1b8873a0 JI |
600 | } |
601 | ||
a4eaf7f1 | 602 | static void armpmu_disable(struct pmu *pmu) |
1b8873a0 | 603 | { |
48957155 | 604 | armpmu->stop(); |
1b8873a0 JI |
605 | } |
606 | ||
33696fc0 | 607 | static struct pmu pmu = { |
a4eaf7f1 PZ |
608 | .pmu_enable = armpmu_enable, |
609 | .pmu_disable = armpmu_disable, | |
610 | .event_init = armpmu_event_init, | |
611 | .add = armpmu_add, | |
612 | .del = armpmu_del, | |
613 | .start = armpmu_start, | |
614 | .stop = armpmu_stop, | |
615 | .read = armpmu_read, | |
33696fc0 PZ |
616 | }; |
617 | ||
03b7898d MR |
618 | static void __init armpmu_init(struct arm_pmu *armpmu) |
619 | { | |
620 | atomic_set(&armpmu->active_events, 0); | |
621 | mutex_init(&armpmu->reserve_mutex); | |
622 | } | |
623 | ||
43eab878 WD |
624 | /* Include the PMU-specific implementations. */ |
625 | #include "perf_event_xscale.c" | |
626 | #include "perf_event_v6.c" | |
627 | #include "perf_event_v7.c" | |
49e6a32f | 628 | |
574b69cb WD |
629 | /* |
630 | * Ensure the PMU has sane values out of reset. | |
631 | * This requires SMP to be available, so exists as a separate initcall. | |
632 | */ | |
633 | static int __init | |
634 | armpmu_reset(void) | |
635 | { | |
636 | if (armpmu && armpmu->reset) | |
637 | return on_each_cpu(armpmu->reset, NULL, 1); | |
638 | return 0; | |
639 | } | |
640 | arch_initcall(armpmu_reset); | |
641 | ||
b0e89590 WD |
642 | /* |
643 | * PMU platform driver and devicetree bindings. | |
644 | */ | |
645 | static struct of_device_id armpmu_of_device_ids[] = { | |
646 | {.compatible = "arm,cortex-a9-pmu"}, | |
647 | {.compatible = "arm,cortex-a8-pmu"}, | |
648 | {.compatible = "arm,arm1136-pmu"}, | |
649 | {.compatible = "arm,arm1176-pmu"}, | |
650 | {}, | |
651 | }; | |
652 | ||
653 | static struct platform_device_id armpmu_plat_device_ids[] = { | |
654 | {.name = "arm-pmu"}, | |
655 | {}, | |
656 | }; | |
657 | ||
658 | static int __devinit armpmu_device_probe(struct platform_device *pdev) | |
659 | { | |
660 | pmu_device = pdev; | |
661 | return 0; | |
662 | } | |
663 | ||
664 | static struct platform_driver armpmu_driver = { | |
665 | .driver = { | |
666 | .name = "arm-pmu", | |
667 | .of_match_table = armpmu_of_device_ids, | |
668 | }, | |
669 | .probe = armpmu_device_probe, | |
670 | .id_table = armpmu_plat_device_ids, | |
671 | }; | |
672 | ||
673 | static int __init register_pmu_driver(void) | |
674 | { | |
675 | return platform_driver_register(&armpmu_driver); | |
676 | } | |
677 | device_initcall(register_pmu_driver); | |
678 | ||
679 | /* | |
680 | * CPU PMU identification and registration. | |
681 | */ | |
1b8873a0 JI |
682 | static int __init |
683 | init_hw_perf_events(void) | |
684 | { | |
685 | unsigned long cpuid = read_cpuid_id(); | |
686 | unsigned long implementor = (cpuid & 0xFF000000) >> 24; | |
687 | unsigned long part_number = (cpuid & 0xFFF0); | |
688 | ||
49e6a32f | 689 | /* ARM Ltd CPUs. */ |
1b8873a0 JI |
690 | if (0x41 == implementor) { |
691 | switch (part_number) { | |
692 | case 0xB360: /* ARM1136 */ | |
693 | case 0xB560: /* ARM1156 */ | |
694 | case 0xB760: /* ARM1176 */ | |
3cb314ba | 695 | armpmu = armv6pmu_init(); |
1b8873a0 JI |
696 | break; |
697 | case 0xB020: /* ARM11mpcore */ | |
3cb314ba | 698 | armpmu = armv6mpcore_pmu_init(); |
1b8873a0 | 699 | break; |
796d1295 | 700 | case 0xC080: /* Cortex-A8 */ |
3cb314ba | 701 | armpmu = armv7_a8_pmu_init(); |
796d1295 JP |
702 | break; |
703 | case 0xC090: /* Cortex-A9 */ | |
3cb314ba | 704 | armpmu = armv7_a9_pmu_init(); |
796d1295 | 705 | break; |
0c205cbe WD |
706 | case 0xC050: /* Cortex-A5 */ |
707 | armpmu = armv7_a5_pmu_init(); | |
708 | break; | |
14abd038 WD |
709 | case 0xC0F0: /* Cortex-A15 */ |
710 | armpmu = armv7_a15_pmu_init(); | |
711 | break; | |
49e6a32f WD |
712 | } |
713 | /* Intel CPUs [xscale]. */ | |
714 | } else if (0x69 == implementor) { | |
715 | part_number = (cpuid >> 13) & 0x7; | |
716 | switch (part_number) { | |
717 | case 1: | |
3cb314ba | 718 | armpmu = xscale1pmu_init(); |
49e6a32f WD |
719 | break; |
720 | case 2: | |
3cb314ba | 721 | armpmu = xscale2pmu_init(); |
49e6a32f | 722 | break; |
1b8873a0 JI |
723 | } |
724 | } | |
725 | ||
49e6a32f | 726 | if (armpmu) { |
796d1295 | 727 | pr_info("enabled with %s PMU driver, %d counters available\n", |
62994831 | 728 | armpmu->name, armpmu->num_events); |
03b7898d | 729 | armpmu_init(armpmu); |
48957155 | 730 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
49e6a32f WD |
731 | } else { |
732 | pr_info("no hardware support available\n"); | |
49e6a32f | 733 | } |
1b8873a0 JI |
734 | |
735 | return 0; | |
736 | } | |
004417a6 | 737 | early_initcall(init_hw_perf_events); |
1b8873a0 JI |
738 | |
739 | /* | |
740 | * Callchain handling code. | |
741 | */ | |
1b8873a0 JI |
742 | |
743 | /* | |
744 | * The registers we're interested in are at the end of the variable | |
745 | * length saved register structure. The fp points at the end of this | |
746 | * structure so the address of this struct is: | |
747 | * (struct frame_tail *)(xxx->fp)-1 | |
748 | * | |
749 | * This code has been adapted from the ARM OProfile support. | |
750 | */ | |
751 | struct frame_tail { | |
4d6b7a77 WD |
752 | struct frame_tail __user *fp; |
753 | unsigned long sp; | |
754 | unsigned long lr; | |
1b8873a0 JI |
755 | } __attribute__((packed)); |
756 | ||
757 | /* | |
758 | * Get the return address for a single stackframe and return a pointer to the | |
759 | * next frame tail. | |
760 | */ | |
4d6b7a77 WD |
761 | static struct frame_tail __user * |
762 | user_backtrace(struct frame_tail __user *tail, | |
1b8873a0 JI |
763 | struct perf_callchain_entry *entry) |
764 | { | |
765 | struct frame_tail buftail; | |
766 | ||
767 | /* Also check accessibility of one struct frame_tail beyond */ | |
768 | if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) | |
769 | return NULL; | |
770 | if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) | |
771 | return NULL; | |
772 | ||
70791ce9 | 773 | perf_callchain_store(entry, buftail.lr); |
1b8873a0 JI |
774 | |
775 | /* | |
776 | * Frame pointers should strictly progress back up the stack | |
777 | * (towards higher addresses). | |
778 | */ | |
cb06199b | 779 | if (tail + 1 >= buftail.fp) |
1b8873a0 JI |
780 | return NULL; |
781 | ||
782 | return buftail.fp - 1; | |
783 | } | |
784 | ||
56962b44 FW |
785 | void |
786 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 | 787 | { |
4d6b7a77 | 788 | struct frame_tail __user *tail; |
1b8873a0 | 789 | |
1b8873a0 | 790 | |
4d6b7a77 | 791 | tail = (struct frame_tail __user *)regs->ARM_fp - 1; |
1b8873a0 | 792 | |
860ad782 SR |
793 | while ((entry->nr < PERF_MAX_STACK_DEPTH) && |
794 | tail && !((unsigned long)tail & 0x3)) | |
1b8873a0 JI |
795 | tail = user_backtrace(tail, entry); |
796 | } | |
797 | ||
798 | /* | |
799 | * Gets called by walk_stackframe() for every stackframe. This will be called | |
800 | * whist unwinding the stackframe and is like a subroutine return so we use | |
801 | * the PC. | |
802 | */ | |
803 | static int | |
804 | callchain_trace(struct stackframe *fr, | |
805 | void *data) | |
806 | { | |
807 | struct perf_callchain_entry *entry = data; | |
70791ce9 | 808 | perf_callchain_store(entry, fr->pc); |
1b8873a0 JI |
809 | return 0; |
810 | } | |
811 | ||
56962b44 FW |
812 | void |
813 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 JI |
814 | { |
815 | struct stackframe fr; | |
816 | ||
1b8873a0 JI |
817 | fr.fp = regs->ARM_fp; |
818 | fr.sp = regs->ARM_sp; | |
819 | fr.lr = regs->ARM_lr; | |
820 | fr.pc = regs->ARM_pc; | |
821 | walk_stackframe(&fr, callchain_trace, entry); | |
822 | } |