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Commit | Line | Data |
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1b8873a0 JI |
1 | #undef DEBUG |
2 | ||
3 | /* | |
4 | * ARM performance counter support. | |
5 | * | |
6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | |
43eab878 | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
796d1295 | 8 | * |
1b8873a0 JI |
9 | * This code is based on the sparc64 perf event code, which is in turn based |
10 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace | |
11 | * code. | |
12 | */ | |
13 | #define pr_fmt(fmt) "hw perfevents: " fmt | |
14 | ||
1b8873a0 | 15 | #include <linux/kernel.h> |
49c006b9 | 16 | #include <linux/platform_device.h> |
7be2958e | 17 | #include <linux/pm_runtime.h> |
5505b206 | 18 | #include <linux/uaccess.h> |
bbd64559 SB |
19 | #include <linux/irq.h> |
20 | #include <linux/irqdesc.h> | |
1b8873a0 | 21 | |
1b8873a0 JI |
22 | #include <asm/irq_regs.h> |
23 | #include <asm/pmu.h> | |
24 | #include <asm/stacktrace.h> | |
25 | ||
1b8873a0 | 26 | static int |
e1f431b5 MR |
27 | armpmu_map_cache_event(const unsigned (*cache_map) |
28 | [PERF_COUNT_HW_CACHE_MAX] | |
29 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
30 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
31 | u64 config) | |
1b8873a0 JI |
32 | { |
33 | unsigned int cache_type, cache_op, cache_result, ret; | |
34 | ||
35 | cache_type = (config >> 0) & 0xff; | |
36 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
37 | return -EINVAL; | |
38 | ||
39 | cache_op = (config >> 8) & 0xff; | |
40 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
41 | return -EINVAL; | |
42 | ||
43 | cache_result = (config >> 16) & 0xff; | |
44 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
45 | return -EINVAL; | |
46 | ||
e1f431b5 | 47 | ret = (int)(*cache_map)[cache_type][cache_op][cache_result]; |
1b8873a0 JI |
48 | |
49 | if (ret == CACHE_OP_UNSUPPORTED) | |
50 | return -ENOENT; | |
51 | ||
52 | return ret; | |
53 | } | |
54 | ||
84fee97a | 55 | static int |
6dbc0029 | 56 | armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) |
84fee97a | 57 | { |
d9f96635 SB |
58 | int mapping; |
59 | ||
60 | if (config >= PERF_COUNT_HW_MAX) | |
61 | return -EINVAL; | |
62 | ||
63 | mapping = (*event_map)[config]; | |
e1f431b5 | 64 | return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; |
84fee97a WD |
65 | } |
66 | ||
67 | static int | |
e1f431b5 | 68 | armpmu_map_raw_event(u32 raw_event_mask, u64 config) |
84fee97a | 69 | { |
e1f431b5 MR |
70 | return (int)(config & raw_event_mask); |
71 | } | |
72 | ||
6dbc0029 WD |
73 | int |
74 | armpmu_map_event(struct perf_event *event, | |
75 | const unsigned (*event_map)[PERF_COUNT_HW_MAX], | |
76 | const unsigned (*cache_map) | |
77 | [PERF_COUNT_HW_CACHE_MAX] | |
78 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
79 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
80 | u32 raw_event_mask) | |
e1f431b5 MR |
81 | { |
82 | u64 config = event->attr.config; | |
83 | ||
84 | switch (event->attr.type) { | |
85 | case PERF_TYPE_HARDWARE: | |
6dbc0029 | 86 | return armpmu_map_hw_event(event_map, config); |
e1f431b5 MR |
87 | case PERF_TYPE_HW_CACHE: |
88 | return armpmu_map_cache_event(cache_map, config); | |
89 | case PERF_TYPE_RAW: | |
90 | return armpmu_map_raw_event(raw_event_mask, config); | |
91 | } | |
92 | ||
93 | return -ENOENT; | |
84fee97a WD |
94 | } |
95 | ||
ed6f2a52 | 96 | int armpmu_event_set_period(struct perf_event *event) |
1b8873a0 | 97 | { |
8a16b34e | 98 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
ed6f2a52 | 99 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 100 | s64 left = local64_read(&hwc->period_left); |
1b8873a0 JI |
101 | s64 period = hwc->sample_period; |
102 | int ret = 0; | |
103 | ||
104 | if (unlikely(left <= -period)) { | |
105 | left = period; | |
e7850595 | 106 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
107 | hwc->last_period = period; |
108 | ret = 1; | |
109 | } | |
110 | ||
111 | if (unlikely(left <= 0)) { | |
112 | left += period; | |
e7850595 | 113 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
114 | hwc->last_period = period; |
115 | ret = 1; | |
116 | } | |
117 | ||
118 | if (left > (s64)armpmu->max_period) | |
119 | left = armpmu->max_period; | |
120 | ||
e7850595 | 121 | local64_set(&hwc->prev_count, (u64)-left); |
1b8873a0 | 122 | |
ed6f2a52 | 123 | armpmu->write_counter(event, (u64)(-left) & 0xffffffff); |
1b8873a0 JI |
124 | |
125 | perf_event_update_userpage(event); | |
126 | ||
127 | return ret; | |
128 | } | |
129 | ||
ed6f2a52 | 130 | u64 armpmu_event_update(struct perf_event *event) |
1b8873a0 | 131 | { |
8a16b34e | 132 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
ed6f2a52 | 133 | struct hw_perf_event *hwc = &event->hw; |
a737823d | 134 | u64 delta, prev_raw_count, new_raw_count; |
1b8873a0 JI |
135 | |
136 | again: | |
e7850595 | 137 | prev_raw_count = local64_read(&hwc->prev_count); |
ed6f2a52 | 138 | new_raw_count = armpmu->read_counter(event); |
1b8873a0 | 139 | |
e7850595 | 140 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
1b8873a0 JI |
141 | new_raw_count) != prev_raw_count) |
142 | goto again; | |
143 | ||
57273471 | 144 | delta = (new_raw_count - prev_raw_count) & armpmu->max_period; |
1b8873a0 | 145 | |
e7850595 PZ |
146 | local64_add(delta, &event->count); |
147 | local64_sub(delta, &hwc->period_left); | |
1b8873a0 JI |
148 | |
149 | return new_raw_count; | |
150 | } | |
151 | ||
152 | static void | |
a4eaf7f1 | 153 | armpmu_read(struct perf_event *event) |
1b8873a0 | 154 | { |
ed6f2a52 | 155 | armpmu_event_update(event); |
1b8873a0 JI |
156 | } |
157 | ||
158 | static void | |
a4eaf7f1 | 159 | armpmu_stop(struct perf_event *event, int flags) |
1b8873a0 | 160 | { |
8a16b34e | 161 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
162 | struct hw_perf_event *hwc = &event->hw; |
163 | ||
a4eaf7f1 PZ |
164 | /* |
165 | * ARM pmu always has to update the counter, so ignore | |
166 | * PERF_EF_UPDATE, see comments in armpmu_start(). | |
167 | */ | |
168 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
ed6f2a52 SH |
169 | armpmu->disable(event); |
170 | armpmu_event_update(event); | |
a4eaf7f1 PZ |
171 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
172 | } | |
1b8873a0 JI |
173 | } |
174 | ||
ed6f2a52 | 175 | static void armpmu_start(struct perf_event *event, int flags) |
1b8873a0 | 176 | { |
8a16b34e | 177 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
178 | struct hw_perf_event *hwc = &event->hw; |
179 | ||
a4eaf7f1 PZ |
180 | /* |
181 | * ARM pmu always has to reprogram the period, so ignore | |
182 | * PERF_EF_RELOAD, see the comment below. | |
183 | */ | |
184 | if (flags & PERF_EF_RELOAD) | |
185 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
186 | ||
187 | hwc->state = 0; | |
1b8873a0 JI |
188 | /* |
189 | * Set the period again. Some counters can't be stopped, so when we | |
a4eaf7f1 | 190 | * were stopped we simply disabled the IRQ source and the counter |
1b8873a0 JI |
191 | * may have been left counting. If we don't do this step then we may |
192 | * get an interrupt too soon or *way* too late if the overflow has | |
193 | * happened since disabling. | |
194 | */ | |
ed6f2a52 SH |
195 | armpmu_event_set_period(event); |
196 | armpmu->enable(event); | |
1b8873a0 JI |
197 | } |
198 | ||
a4eaf7f1 PZ |
199 | static void |
200 | armpmu_del(struct perf_event *event, int flags) | |
201 | { | |
8a16b34e | 202 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
8be3f9a2 | 203 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
a4eaf7f1 PZ |
204 | struct hw_perf_event *hwc = &event->hw; |
205 | int idx = hwc->idx; | |
206 | ||
a4eaf7f1 | 207 | armpmu_stop(event, PERF_EF_UPDATE); |
8be3f9a2 MR |
208 | hw_events->events[idx] = NULL; |
209 | clear_bit(idx, hw_events->used_mask); | |
eab443ef SB |
210 | if (armpmu->clear_event_idx) |
211 | armpmu->clear_event_idx(hw_events, event); | |
a4eaf7f1 PZ |
212 | |
213 | perf_event_update_userpage(event); | |
214 | } | |
215 | ||
1b8873a0 | 216 | static int |
a4eaf7f1 | 217 | armpmu_add(struct perf_event *event, int flags) |
1b8873a0 | 218 | { |
8a16b34e | 219 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
8be3f9a2 | 220 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
1b8873a0 JI |
221 | struct hw_perf_event *hwc = &event->hw; |
222 | int idx; | |
223 | int err = 0; | |
224 | ||
33696fc0 | 225 | perf_pmu_disable(event->pmu); |
24cd7f54 | 226 | |
1b8873a0 | 227 | /* If we don't have a space for the counter then finish early. */ |
ed6f2a52 | 228 | idx = armpmu->get_event_idx(hw_events, event); |
1b8873a0 JI |
229 | if (idx < 0) { |
230 | err = idx; | |
231 | goto out; | |
232 | } | |
233 | ||
234 | /* | |
235 | * If there is an event in the counter we are going to use then make | |
236 | * sure it is disabled. | |
237 | */ | |
238 | event->hw.idx = idx; | |
ed6f2a52 | 239 | armpmu->disable(event); |
8be3f9a2 | 240 | hw_events->events[idx] = event; |
1b8873a0 | 241 | |
a4eaf7f1 PZ |
242 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
243 | if (flags & PERF_EF_START) | |
244 | armpmu_start(event, PERF_EF_RELOAD); | |
1b8873a0 JI |
245 | |
246 | /* Propagate our changes to the userspace mapping. */ | |
247 | perf_event_update_userpage(event); | |
248 | ||
249 | out: | |
33696fc0 | 250 | perf_pmu_enable(event->pmu); |
1b8873a0 JI |
251 | return err; |
252 | } | |
253 | ||
1b8873a0 | 254 | static int |
8be3f9a2 | 255 | validate_event(struct pmu_hw_events *hw_events, |
1b8873a0 JI |
256 | struct perf_event *event) |
257 | { | |
8a16b34e | 258 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 259 | |
c95eb318 WD |
260 | if (is_software_event(event)) |
261 | return 1; | |
262 | ||
2dfcb802 | 263 | if (event->state < PERF_EVENT_STATE_OFF) |
cb2d8b34 WD |
264 | return 1; |
265 | ||
266 | if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec) | |
65b4711f | 267 | return 1; |
1b8873a0 | 268 | |
ed6f2a52 | 269 | return armpmu->get_event_idx(hw_events, event) >= 0; |
1b8873a0 JI |
270 | } |
271 | ||
272 | static int | |
273 | validate_group(struct perf_event *event) | |
274 | { | |
275 | struct perf_event *sibling, *leader = event->group_leader; | |
8be3f9a2 | 276 | struct pmu_hw_events fake_pmu; |
bce34d14 | 277 | DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS); |
1b8873a0 | 278 | |
bce34d14 WD |
279 | /* |
280 | * Initialise the fake PMU. We only need to populate the | |
281 | * used_mask for the purposes of validation. | |
282 | */ | |
283 | memset(fake_used_mask, 0, sizeof(fake_used_mask)); | |
284 | fake_pmu.used_mask = fake_used_mask; | |
1b8873a0 JI |
285 | |
286 | if (!validate_event(&fake_pmu, leader)) | |
aa2bc1ad | 287 | return -EINVAL; |
1b8873a0 JI |
288 | |
289 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { | |
290 | if (!validate_event(&fake_pmu, sibling)) | |
aa2bc1ad | 291 | return -EINVAL; |
1b8873a0 JI |
292 | } |
293 | ||
294 | if (!validate_event(&fake_pmu, event)) | |
aa2bc1ad | 295 | return -EINVAL; |
1b8873a0 JI |
296 | |
297 | return 0; | |
298 | } | |
299 | ||
051f1b13 | 300 | static irqreturn_t armpmu_dispatch_irq(int irq, void *dev) |
0e25a5c9 | 301 | { |
bbd64559 SB |
302 | struct arm_pmu *armpmu; |
303 | struct platform_device *plat_device; | |
304 | struct arm_pmu_platdata *plat; | |
5f5092e7 WD |
305 | int ret; |
306 | u64 start_clock, finish_clock; | |
bbd64559 SB |
307 | |
308 | if (irq_is_percpu(irq)) | |
309 | dev = *(void **)dev; | |
310 | armpmu = dev; | |
311 | plat_device = armpmu->plat_device; | |
312 | plat = dev_get_platdata(&plat_device->dev); | |
0e25a5c9 | 313 | |
5f5092e7 | 314 | start_clock = sched_clock(); |
051f1b13 | 315 | if (plat && plat->handle_irq) |
5f5092e7 | 316 | ret = plat->handle_irq(irq, dev, armpmu->handle_irq); |
051f1b13 | 317 | else |
5f5092e7 WD |
318 | ret = armpmu->handle_irq(irq, dev); |
319 | finish_clock = sched_clock(); | |
320 | ||
321 | perf_sample_event_took(finish_clock - start_clock); | |
322 | return ret; | |
0e25a5c9 RV |
323 | } |
324 | ||
0b390e21 | 325 | static void |
8a16b34e | 326 | armpmu_release_hardware(struct arm_pmu *armpmu) |
0b390e21 | 327 | { |
ed6f2a52 | 328 | armpmu->free_irq(armpmu); |
051f1b13 | 329 | pm_runtime_put_sync(&armpmu->plat_device->dev); |
0b390e21 WD |
330 | } |
331 | ||
1b8873a0 | 332 | static int |
8a16b34e | 333 | armpmu_reserve_hardware(struct arm_pmu *armpmu) |
1b8873a0 | 334 | { |
051f1b13 | 335 | int err; |
a9356a04 | 336 | struct platform_device *pmu_device = armpmu->plat_device; |
1b8873a0 | 337 | |
e5a21327 WD |
338 | if (!pmu_device) |
339 | return -ENODEV; | |
340 | ||
7be2958e | 341 | pm_runtime_get_sync(&pmu_device->dev); |
ed6f2a52 | 342 | err = armpmu->request_irq(armpmu, armpmu_dispatch_irq); |
051f1b13 SH |
343 | if (err) { |
344 | armpmu_release_hardware(armpmu); | |
345 | return err; | |
49c006b9 | 346 | } |
1b8873a0 | 347 | |
0b390e21 | 348 | return 0; |
1b8873a0 JI |
349 | } |
350 | ||
1b8873a0 JI |
351 | static void |
352 | hw_perf_event_destroy(struct perf_event *event) | |
353 | { | |
8a16b34e | 354 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
03b7898d MR |
355 | atomic_t *active_events = &armpmu->active_events; |
356 | struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex; | |
357 | ||
358 | if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) { | |
8a16b34e | 359 | armpmu_release_hardware(armpmu); |
03b7898d | 360 | mutex_unlock(pmu_reserve_mutex); |
1b8873a0 JI |
361 | } |
362 | } | |
363 | ||
05d22fde WD |
364 | static int |
365 | event_requires_mode_exclusion(struct perf_event_attr *attr) | |
366 | { | |
367 | return attr->exclude_idle || attr->exclude_user || | |
368 | attr->exclude_kernel || attr->exclude_hv; | |
369 | } | |
370 | ||
1b8873a0 JI |
371 | static int |
372 | __hw_perf_event_init(struct perf_event *event) | |
373 | { | |
8a16b34e | 374 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 375 | struct hw_perf_event *hwc = &event->hw; |
9dcbf466 | 376 | int mapping; |
1b8873a0 | 377 | |
e1f431b5 | 378 | mapping = armpmu->map_event(event); |
1b8873a0 JI |
379 | |
380 | if (mapping < 0) { | |
381 | pr_debug("event %x:%llx not supported\n", event->attr.type, | |
382 | event->attr.config); | |
383 | return mapping; | |
384 | } | |
385 | ||
05d22fde WD |
386 | /* |
387 | * We don't assign an index until we actually place the event onto | |
388 | * hardware. Use -1 to signify that we haven't decided where to put it | |
389 | * yet. For SMP systems, each core has it's own PMU so we can't do any | |
390 | * clever allocation or constraints checking at this point. | |
391 | */ | |
392 | hwc->idx = -1; | |
393 | hwc->config_base = 0; | |
394 | hwc->config = 0; | |
395 | hwc->event_base = 0; | |
396 | ||
1b8873a0 JI |
397 | /* |
398 | * Check whether we need to exclude the counter from certain modes. | |
1b8873a0 | 399 | */ |
05d22fde WD |
400 | if ((!armpmu->set_event_filter || |
401 | armpmu->set_event_filter(hwc, &event->attr)) && | |
402 | event_requires_mode_exclusion(&event->attr)) { | |
1b8873a0 JI |
403 | pr_debug("ARM performance counters do not support " |
404 | "mode exclusion\n"); | |
fdeb8e35 | 405 | return -EOPNOTSUPP; |
1b8873a0 JI |
406 | } |
407 | ||
408 | /* | |
05d22fde | 409 | * Store the event encoding into the config_base field. |
1b8873a0 | 410 | */ |
05d22fde | 411 | hwc->config_base |= (unsigned long)mapping; |
1b8873a0 JI |
412 | |
413 | if (!hwc->sample_period) { | |
57273471 WD |
414 | /* |
415 | * For non-sampling runs, limit the sample_period to half | |
416 | * of the counter width. That way, the new counter value | |
417 | * is far less likely to overtake the previous one unless | |
418 | * you have some serious IRQ latency issues. | |
419 | */ | |
420 | hwc->sample_period = armpmu->max_period >> 1; | |
1b8873a0 | 421 | hwc->last_period = hwc->sample_period; |
e7850595 | 422 | local64_set(&hwc->period_left, hwc->sample_period); |
1b8873a0 JI |
423 | } |
424 | ||
1b8873a0 | 425 | if (event->group_leader != event) { |
e595ede6 | 426 | if (validate_group(event) != 0) |
1b8873a0 JI |
427 | return -EINVAL; |
428 | } | |
429 | ||
9dcbf466 | 430 | return 0; |
1b8873a0 JI |
431 | } |
432 | ||
b0a873eb | 433 | static int armpmu_event_init(struct perf_event *event) |
1b8873a0 | 434 | { |
8a16b34e | 435 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 436 | int err = 0; |
03b7898d | 437 | atomic_t *active_events = &armpmu->active_events; |
1b8873a0 | 438 | |
2481c5fa SE |
439 | /* does not support taken branch sampling */ |
440 | if (has_branch_stack(event)) | |
441 | return -EOPNOTSUPP; | |
442 | ||
e1f431b5 | 443 | if (armpmu->map_event(event) == -ENOENT) |
b0a873eb | 444 | return -ENOENT; |
b0a873eb | 445 | |
1b8873a0 JI |
446 | event->destroy = hw_perf_event_destroy; |
447 | ||
03b7898d MR |
448 | if (!atomic_inc_not_zero(active_events)) { |
449 | mutex_lock(&armpmu->reserve_mutex); | |
450 | if (atomic_read(active_events) == 0) | |
8a16b34e | 451 | err = armpmu_reserve_hardware(armpmu); |
1b8873a0 JI |
452 | |
453 | if (!err) | |
03b7898d MR |
454 | atomic_inc(active_events); |
455 | mutex_unlock(&armpmu->reserve_mutex); | |
1b8873a0 JI |
456 | } |
457 | ||
458 | if (err) | |
b0a873eb | 459 | return err; |
1b8873a0 JI |
460 | |
461 | err = __hw_perf_event_init(event); | |
462 | if (err) | |
463 | hw_perf_event_destroy(event); | |
464 | ||
b0a873eb | 465 | return err; |
1b8873a0 JI |
466 | } |
467 | ||
a4eaf7f1 | 468 | static void armpmu_enable(struct pmu *pmu) |
1b8873a0 | 469 | { |
8be3f9a2 | 470 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
8be3f9a2 | 471 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
7325eaec | 472 | int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events); |
1b8873a0 | 473 | |
f4f38430 | 474 | if (enabled) |
ed6f2a52 | 475 | armpmu->start(armpmu); |
1b8873a0 JI |
476 | } |
477 | ||
a4eaf7f1 | 478 | static void armpmu_disable(struct pmu *pmu) |
1b8873a0 | 479 | { |
8a16b34e | 480 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
ed6f2a52 | 481 | armpmu->stop(armpmu); |
1b8873a0 JI |
482 | } |
483 | ||
7be2958e JH |
484 | #ifdef CONFIG_PM_RUNTIME |
485 | static int armpmu_runtime_resume(struct device *dev) | |
486 | { | |
487 | struct arm_pmu_platdata *plat = dev_get_platdata(dev); | |
488 | ||
489 | if (plat && plat->runtime_resume) | |
490 | return plat->runtime_resume(dev); | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
495 | static int armpmu_runtime_suspend(struct device *dev) | |
496 | { | |
497 | struct arm_pmu_platdata *plat = dev_get_platdata(dev); | |
498 | ||
499 | if (plat && plat->runtime_suspend) | |
500 | return plat->runtime_suspend(dev); | |
501 | ||
502 | return 0; | |
503 | } | |
504 | #endif | |
505 | ||
6dbc0029 WD |
506 | const struct dev_pm_ops armpmu_dev_pm_ops = { |
507 | SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL) | |
508 | }; | |
509 | ||
44d6b1fc | 510 | static void armpmu_init(struct arm_pmu *armpmu) |
03b7898d MR |
511 | { |
512 | atomic_set(&armpmu->active_events, 0); | |
513 | mutex_init(&armpmu->reserve_mutex); | |
8a16b34e MR |
514 | |
515 | armpmu->pmu = (struct pmu) { | |
516 | .pmu_enable = armpmu_enable, | |
517 | .pmu_disable = armpmu_disable, | |
518 | .event_init = armpmu_event_init, | |
519 | .add = armpmu_add, | |
520 | .del = armpmu_del, | |
521 | .start = armpmu_start, | |
522 | .stop = armpmu_stop, | |
523 | .read = armpmu_read, | |
524 | }; | |
525 | } | |
526 | ||
0305230a | 527 | int armpmu_register(struct arm_pmu *armpmu, int type) |
8a16b34e MR |
528 | { |
529 | armpmu_init(armpmu); | |
2ac29a14 | 530 | pm_runtime_enable(&armpmu->plat_device->dev); |
04236f9f WD |
531 | pr_info("enabled with %s PMU driver, %d counters available\n", |
532 | armpmu->name, armpmu->num_events); | |
0305230a | 533 | return perf_pmu_register(&armpmu->pmu, armpmu->name, type); |
03b7898d MR |
534 | } |
535 | ||
1b8873a0 JI |
536 | /* |
537 | * Callchain handling code. | |
538 | */ | |
1b8873a0 JI |
539 | |
540 | /* | |
541 | * The registers we're interested in are at the end of the variable | |
542 | * length saved register structure. The fp points at the end of this | |
543 | * structure so the address of this struct is: | |
544 | * (struct frame_tail *)(xxx->fp)-1 | |
545 | * | |
546 | * This code has been adapted from the ARM OProfile support. | |
547 | */ | |
548 | struct frame_tail { | |
4d6b7a77 WD |
549 | struct frame_tail __user *fp; |
550 | unsigned long sp; | |
551 | unsigned long lr; | |
1b8873a0 JI |
552 | } __attribute__((packed)); |
553 | ||
554 | /* | |
555 | * Get the return address for a single stackframe and return a pointer to the | |
556 | * next frame tail. | |
557 | */ | |
4d6b7a77 WD |
558 | static struct frame_tail __user * |
559 | user_backtrace(struct frame_tail __user *tail, | |
1b8873a0 JI |
560 | struct perf_callchain_entry *entry) |
561 | { | |
562 | struct frame_tail buftail; | |
563 | ||
564 | /* Also check accessibility of one struct frame_tail beyond */ | |
565 | if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) | |
566 | return NULL; | |
567 | if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) | |
568 | return NULL; | |
569 | ||
70791ce9 | 570 | perf_callchain_store(entry, buftail.lr); |
1b8873a0 JI |
571 | |
572 | /* | |
573 | * Frame pointers should strictly progress back up the stack | |
574 | * (towards higher addresses). | |
575 | */ | |
cb06199b | 576 | if (tail + 1 >= buftail.fp) |
1b8873a0 JI |
577 | return NULL; |
578 | ||
579 | return buftail.fp - 1; | |
580 | } | |
581 | ||
56962b44 FW |
582 | void |
583 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 | 584 | { |
4d6b7a77 | 585 | struct frame_tail __user *tail; |
1b8873a0 | 586 | |
e50c5418 MZ |
587 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
588 | /* We don't support guest os callchain now */ | |
589 | return; | |
590 | } | |
1b8873a0 | 591 | |
c5f927a6 | 592 | perf_callchain_store(entry, regs->ARM_pc); |
4d6b7a77 | 593 | tail = (struct frame_tail __user *)regs->ARM_fp - 1; |
1b8873a0 | 594 | |
860ad782 SR |
595 | while ((entry->nr < PERF_MAX_STACK_DEPTH) && |
596 | tail && !((unsigned long)tail & 0x3)) | |
1b8873a0 JI |
597 | tail = user_backtrace(tail, entry); |
598 | } | |
599 | ||
600 | /* | |
601 | * Gets called by walk_stackframe() for every stackframe. This will be called | |
602 | * whist unwinding the stackframe and is like a subroutine return so we use | |
603 | * the PC. | |
604 | */ | |
605 | static int | |
606 | callchain_trace(struct stackframe *fr, | |
607 | void *data) | |
608 | { | |
609 | struct perf_callchain_entry *entry = data; | |
70791ce9 | 610 | perf_callchain_store(entry, fr->pc); |
1b8873a0 JI |
611 | return 0; |
612 | } | |
613 | ||
56962b44 FW |
614 | void |
615 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 JI |
616 | { |
617 | struct stackframe fr; | |
618 | ||
e50c5418 MZ |
619 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
620 | /* We don't support guest os callchain now */ | |
621 | return; | |
622 | } | |
623 | ||
1b8873a0 JI |
624 | fr.fp = regs->ARM_fp; |
625 | fr.sp = regs->ARM_sp; | |
626 | fr.lr = regs->ARM_lr; | |
627 | fr.pc = regs->ARM_pc; | |
628 | walk_stackframe(&fr, callchain_trace, entry); | |
629 | } | |
e50c5418 MZ |
630 | |
631 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
632 | { | |
633 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) | |
634 | return perf_guest_cbs->get_guest_ip(); | |
635 | ||
636 | return instruction_pointer(regs); | |
637 | } | |
638 | ||
639 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
640 | { | |
641 | int misc = 0; | |
642 | ||
643 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { | |
644 | if (perf_guest_cbs->is_user_mode()) | |
645 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
646 | else | |
647 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
648 | } else { | |
649 | if (user_mode(regs)) | |
650 | misc |= PERF_RECORD_MISC_USER; | |
651 | else | |
652 | misc |= PERF_RECORD_MISC_KERNEL; | |
653 | } | |
654 | ||
655 | return misc; | |
656 | } |