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Commit | Line | Data |
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1b8873a0 JI |
1 | #undef DEBUG |
2 | ||
3 | /* | |
4 | * ARM performance counter support. | |
5 | * | |
6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | |
43eab878 | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
796d1295 | 8 | * |
1b8873a0 JI |
9 | * This code is based on the sparc64 perf event code, which is in turn based |
10 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace | |
11 | * code. | |
12 | */ | |
13 | #define pr_fmt(fmt) "hw perfevents: " fmt | |
14 | ||
15 | #include <linux/interrupt.h> | |
16 | #include <linux/kernel.h> | |
181193f3 | 17 | #include <linux/module.h> |
1b8873a0 | 18 | #include <linux/perf_event.h> |
49c006b9 | 19 | #include <linux/platform_device.h> |
1b8873a0 JI |
20 | #include <linux/spinlock.h> |
21 | #include <linux/uaccess.h> | |
22 | ||
23 | #include <asm/cputype.h> | |
24 | #include <asm/irq.h> | |
25 | #include <asm/irq_regs.h> | |
26 | #include <asm/pmu.h> | |
27 | #include <asm/stacktrace.h> | |
28 | ||
1b8873a0 | 29 | /* |
ecf5a893 | 30 | * ARMv6 supports a maximum of 3 events, starting from index 0. If we add |
1b8873a0 JI |
31 | * another platform that supports more, we need to increase this to be the |
32 | * largest of all platforms. | |
796d1295 JP |
33 | * |
34 | * ARMv7 supports up to 32 events: | |
35 | * cycle counter CCNT + 31 events counters CNT0..30. | |
36 | * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters. | |
1b8873a0 | 37 | */ |
ecf5a893 | 38 | #define ARMPMU_MAX_HWEVENTS 32 |
1b8873a0 JI |
39 | |
40 | /* The events for a given CPU. */ | |
41 | struct cpu_hw_events { | |
42 | /* | |
ecf5a893 | 43 | * The events that are active on the CPU for the given index. |
1b8873a0 JI |
44 | */ |
45 | struct perf_event *events[ARMPMU_MAX_HWEVENTS]; | |
46 | ||
47 | /* | |
48 | * A 1 bit for an index indicates that the counter is being used for | |
49 | * an event. A 0 means that the counter can be used. | |
50 | */ | |
51 | unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)]; | |
0f78d2d5 MR |
52 | |
53 | /* | |
54 | * Hardware lock to serialize accesses to PMU registers. Needed for the | |
55 | * read/modify/write sequences. | |
56 | */ | |
57 | raw_spinlock_t pmu_lock; | |
1b8873a0 | 58 | }; |
4d6b7a77 | 59 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
181193f3 | 60 | |
1b8873a0 | 61 | struct arm_pmu { |
181193f3 | 62 | enum arm_perf_pmu_ids id; |
7ae18a57 | 63 | enum arm_pmu_type type; |
0b390e21 | 64 | cpumask_t active_irqs; |
62994831 | 65 | const char *name; |
1b8873a0 JI |
66 | irqreturn_t (*handle_irq)(int irq_num, void *dev); |
67 | void (*enable)(struct hw_perf_event *evt, int idx); | |
68 | void (*disable)(struct hw_perf_event *evt, int idx); | |
1b8873a0 JI |
69 | int (*get_event_idx)(struct cpu_hw_events *cpuc, |
70 | struct hw_perf_event *hwc); | |
05d22fde WD |
71 | int (*set_event_filter)(struct hw_perf_event *evt, |
72 | struct perf_event_attr *attr); | |
1b8873a0 JI |
73 | u32 (*read_counter)(int idx); |
74 | void (*write_counter)(int idx, u32 val); | |
75 | void (*start)(void); | |
76 | void (*stop)(void); | |
574b69cb | 77 | void (*reset)(void *); |
84fee97a WD |
78 | const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] |
79 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
80 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
81 | const unsigned (*event_map)[PERF_COUNT_HW_MAX]; | |
82 | u32 raw_event_mask; | |
1b8873a0 | 83 | int num_events; |
03b7898d MR |
84 | atomic_t active_events; |
85 | struct mutex reserve_mutex; | |
1b8873a0 | 86 | u64 max_period; |
a9356a04 | 87 | struct platform_device *plat_device; |
92f701e1 | 88 | struct cpu_hw_events *(*get_hw_events)(void); |
1b8873a0 JI |
89 | }; |
90 | ||
91 | /* Set at runtime when we know what CPU type we are. */ | |
a6c93afe | 92 | static struct arm_pmu *armpmu; |
1b8873a0 | 93 | |
181193f3 WD |
94 | enum arm_perf_pmu_ids |
95 | armpmu_get_pmu_id(void) | |
96 | { | |
97 | int id = -ENODEV; | |
98 | ||
99 | if (armpmu != NULL) | |
100 | id = armpmu->id; | |
101 | ||
102 | return id; | |
103 | } | |
104 | EXPORT_SYMBOL_GPL(armpmu_get_pmu_id); | |
105 | ||
929f5199 WD |
106 | int |
107 | armpmu_get_max_events(void) | |
108 | { | |
109 | int max_events = 0; | |
110 | ||
111 | if (armpmu != NULL) | |
112 | max_events = armpmu->num_events; | |
113 | ||
114 | return max_events; | |
115 | } | |
116 | EXPORT_SYMBOL_GPL(armpmu_get_max_events); | |
117 | ||
3bf101ba MF |
118 | int perf_num_counters(void) |
119 | { | |
120 | return armpmu_get_max_events(); | |
121 | } | |
122 | EXPORT_SYMBOL_GPL(perf_num_counters); | |
123 | ||
1b8873a0 JI |
124 | #define HW_OP_UNSUPPORTED 0xFFFF |
125 | ||
126 | #define C(_x) \ | |
127 | PERF_COUNT_HW_CACHE_##_x | |
128 | ||
129 | #define CACHE_OP_UNSUPPORTED 0xFFFF | |
130 | ||
1b8873a0 JI |
131 | static int |
132 | armpmu_map_cache_event(u64 config) | |
133 | { | |
134 | unsigned int cache_type, cache_op, cache_result, ret; | |
135 | ||
136 | cache_type = (config >> 0) & 0xff; | |
137 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
138 | return -EINVAL; | |
139 | ||
140 | cache_op = (config >> 8) & 0xff; | |
141 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
142 | return -EINVAL; | |
143 | ||
144 | cache_result = (config >> 16) & 0xff; | |
145 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
146 | return -EINVAL; | |
147 | ||
84fee97a | 148 | ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result]; |
1b8873a0 JI |
149 | |
150 | if (ret == CACHE_OP_UNSUPPORTED) | |
151 | return -ENOENT; | |
152 | ||
153 | return ret; | |
154 | } | |
155 | ||
84fee97a WD |
156 | static int |
157 | armpmu_map_event(u64 config) | |
158 | { | |
159 | int mapping = (*armpmu->event_map)[config]; | |
160 | return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping; | |
161 | } | |
162 | ||
163 | static int | |
164 | armpmu_map_raw_event(u64 config) | |
165 | { | |
166 | return (int)(config & armpmu->raw_event_mask); | |
167 | } | |
168 | ||
1b8873a0 JI |
169 | static int |
170 | armpmu_event_set_period(struct perf_event *event, | |
171 | struct hw_perf_event *hwc, | |
172 | int idx) | |
173 | { | |
e7850595 | 174 | s64 left = local64_read(&hwc->period_left); |
1b8873a0 JI |
175 | s64 period = hwc->sample_period; |
176 | int ret = 0; | |
177 | ||
178 | if (unlikely(left <= -period)) { | |
179 | left = period; | |
e7850595 | 180 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
181 | hwc->last_period = period; |
182 | ret = 1; | |
183 | } | |
184 | ||
185 | if (unlikely(left <= 0)) { | |
186 | left += period; | |
e7850595 | 187 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
188 | hwc->last_period = period; |
189 | ret = 1; | |
190 | } | |
191 | ||
192 | if (left > (s64)armpmu->max_period) | |
193 | left = armpmu->max_period; | |
194 | ||
e7850595 | 195 | local64_set(&hwc->prev_count, (u64)-left); |
1b8873a0 JI |
196 | |
197 | armpmu->write_counter(idx, (u64)(-left) & 0xffffffff); | |
198 | ||
199 | perf_event_update_userpage(event); | |
200 | ||
201 | return ret; | |
202 | } | |
203 | ||
204 | static u64 | |
205 | armpmu_event_update(struct perf_event *event, | |
206 | struct hw_perf_event *hwc, | |
a737823d | 207 | int idx, int overflow) |
1b8873a0 | 208 | { |
a737823d | 209 | u64 delta, prev_raw_count, new_raw_count; |
1b8873a0 JI |
210 | |
211 | again: | |
e7850595 | 212 | prev_raw_count = local64_read(&hwc->prev_count); |
1b8873a0 JI |
213 | new_raw_count = armpmu->read_counter(idx); |
214 | ||
e7850595 | 215 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
1b8873a0 JI |
216 | new_raw_count) != prev_raw_count) |
217 | goto again; | |
218 | ||
a737823d WD |
219 | new_raw_count &= armpmu->max_period; |
220 | prev_raw_count &= armpmu->max_period; | |
221 | ||
222 | if (overflow) | |
6759788b | 223 | delta = armpmu->max_period - prev_raw_count + new_raw_count + 1; |
a737823d WD |
224 | else |
225 | delta = new_raw_count - prev_raw_count; | |
1b8873a0 | 226 | |
e7850595 PZ |
227 | local64_add(delta, &event->count); |
228 | local64_sub(delta, &hwc->period_left); | |
1b8873a0 JI |
229 | |
230 | return new_raw_count; | |
231 | } | |
232 | ||
233 | static void | |
a4eaf7f1 | 234 | armpmu_read(struct perf_event *event) |
1b8873a0 | 235 | { |
1b8873a0 | 236 | struct hw_perf_event *hwc = &event->hw; |
1b8873a0 | 237 | |
a4eaf7f1 PZ |
238 | /* Don't read disabled counters! */ |
239 | if (hwc->idx < 0) | |
240 | return; | |
1b8873a0 | 241 | |
a737823d | 242 | armpmu_event_update(event, hwc, hwc->idx, 0); |
1b8873a0 JI |
243 | } |
244 | ||
245 | static void | |
a4eaf7f1 | 246 | armpmu_stop(struct perf_event *event, int flags) |
1b8873a0 JI |
247 | { |
248 | struct hw_perf_event *hwc = &event->hw; | |
249 | ||
a4eaf7f1 PZ |
250 | /* |
251 | * ARM pmu always has to update the counter, so ignore | |
252 | * PERF_EF_UPDATE, see comments in armpmu_start(). | |
253 | */ | |
254 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
255 | armpmu->disable(hwc, hwc->idx); | |
256 | barrier(); /* why? */ | |
a737823d | 257 | armpmu_event_update(event, hwc, hwc->idx, 0); |
a4eaf7f1 PZ |
258 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
259 | } | |
1b8873a0 JI |
260 | } |
261 | ||
262 | static void | |
a4eaf7f1 | 263 | armpmu_start(struct perf_event *event, int flags) |
1b8873a0 JI |
264 | { |
265 | struct hw_perf_event *hwc = &event->hw; | |
266 | ||
a4eaf7f1 PZ |
267 | /* |
268 | * ARM pmu always has to reprogram the period, so ignore | |
269 | * PERF_EF_RELOAD, see the comment below. | |
270 | */ | |
271 | if (flags & PERF_EF_RELOAD) | |
272 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
273 | ||
274 | hwc->state = 0; | |
1b8873a0 JI |
275 | /* |
276 | * Set the period again. Some counters can't be stopped, so when we | |
a4eaf7f1 | 277 | * were stopped we simply disabled the IRQ source and the counter |
1b8873a0 JI |
278 | * may have been left counting. If we don't do this step then we may |
279 | * get an interrupt too soon or *way* too late if the overflow has | |
280 | * happened since disabling. | |
281 | */ | |
282 | armpmu_event_set_period(event, hwc, hwc->idx); | |
283 | armpmu->enable(hwc, hwc->idx); | |
284 | } | |
285 | ||
a4eaf7f1 PZ |
286 | static void |
287 | armpmu_del(struct perf_event *event, int flags) | |
288 | { | |
92f701e1 | 289 | struct cpu_hw_events *cpuc = armpmu->get_hw_events(); |
a4eaf7f1 PZ |
290 | struct hw_perf_event *hwc = &event->hw; |
291 | int idx = hwc->idx; | |
292 | ||
293 | WARN_ON(idx < 0); | |
294 | ||
a4eaf7f1 PZ |
295 | armpmu_stop(event, PERF_EF_UPDATE); |
296 | cpuc->events[idx] = NULL; | |
297 | clear_bit(idx, cpuc->used_mask); | |
298 | ||
299 | perf_event_update_userpage(event); | |
300 | } | |
301 | ||
1b8873a0 | 302 | static int |
a4eaf7f1 | 303 | armpmu_add(struct perf_event *event, int flags) |
1b8873a0 | 304 | { |
92f701e1 | 305 | struct cpu_hw_events *cpuc = armpmu->get_hw_events(); |
1b8873a0 JI |
306 | struct hw_perf_event *hwc = &event->hw; |
307 | int idx; | |
308 | int err = 0; | |
309 | ||
33696fc0 | 310 | perf_pmu_disable(event->pmu); |
24cd7f54 | 311 | |
1b8873a0 JI |
312 | /* If we don't have a space for the counter then finish early. */ |
313 | idx = armpmu->get_event_idx(cpuc, hwc); | |
314 | if (idx < 0) { | |
315 | err = idx; | |
316 | goto out; | |
317 | } | |
318 | ||
319 | /* | |
320 | * If there is an event in the counter we are going to use then make | |
321 | * sure it is disabled. | |
322 | */ | |
323 | event->hw.idx = idx; | |
324 | armpmu->disable(hwc, idx); | |
325 | cpuc->events[idx] = event; | |
1b8873a0 | 326 | |
a4eaf7f1 PZ |
327 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
328 | if (flags & PERF_EF_START) | |
329 | armpmu_start(event, PERF_EF_RELOAD); | |
1b8873a0 JI |
330 | |
331 | /* Propagate our changes to the userspace mapping. */ | |
332 | perf_event_update_userpage(event); | |
333 | ||
334 | out: | |
33696fc0 | 335 | perf_pmu_enable(event->pmu); |
1b8873a0 JI |
336 | return err; |
337 | } | |
338 | ||
b0a873eb | 339 | static struct pmu pmu; |
1b8873a0 JI |
340 | |
341 | static int | |
342 | validate_event(struct cpu_hw_events *cpuc, | |
343 | struct perf_event *event) | |
344 | { | |
345 | struct hw_perf_event fake_event = event->hw; | |
7b9f72c6 | 346 | struct pmu *leader_pmu = event->group_leader->pmu; |
1b8873a0 | 347 | |
7b9f72c6 | 348 | if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF) |
65b4711f | 349 | return 1; |
1b8873a0 JI |
350 | |
351 | return armpmu->get_event_idx(cpuc, &fake_event) >= 0; | |
352 | } | |
353 | ||
354 | static int | |
355 | validate_group(struct perf_event *event) | |
356 | { | |
357 | struct perf_event *sibling, *leader = event->group_leader; | |
358 | struct cpu_hw_events fake_pmu; | |
359 | ||
360 | memset(&fake_pmu, 0, sizeof(fake_pmu)); | |
361 | ||
362 | if (!validate_event(&fake_pmu, leader)) | |
363 | return -ENOSPC; | |
364 | ||
365 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { | |
366 | if (!validate_event(&fake_pmu, sibling)) | |
367 | return -ENOSPC; | |
368 | } | |
369 | ||
370 | if (!validate_event(&fake_pmu, event)) | |
371 | return -ENOSPC; | |
372 | ||
373 | return 0; | |
374 | } | |
375 | ||
0e25a5c9 RV |
376 | static irqreturn_t armpmu_platform_irq(int irq, void *dev) |
377 | { | |
a9356a04 MR |
378 | struct platform_device *plat_device = armpmu->plat_device; |
379 | struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev); | |
0e25a5c9 RV |
380 | |
381 | return plat->handle_irq(irq, dev, armpmu->handle_irq); | |
382 | } | |
383 | ||
0b390e21 WD |
384 | static void |
385 | armpmu_release_hardware(void) | |
386 | { | |
387 | int i, irq, irqs; | |
a9356a04 | 388 | struct platform_device *pmu_device = armpmu->plat_device; |
0b390e21 WD |
389 | |
390 | irqs = min(pmu_device->num_resources, num_possible_cpus()); | |
391 | ||
392 | for (i = 0; i < irqs; ++i) { | |
393 | if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs)) | |
394 | continue; | |
395 | irq = platform_get_irq(pmu_device, i); | |
396 | if (irq >= 0) | |
397 | free_irq(irq, NULL); | |
398 | } | |
399 | ||
7ae18a57 | 400 | release_pmu(armpmu->type); |
0b390e21 WD |
401 | } |
402 | ||
1b8873a0 JI |
403 | static int |
404 | armpmu_reserve_hardware(void) | |
405 | { | |
0e25a5c9 RV |
406 | struct arm_pmu_platdata *plat; |
407 | irq_handler_t handle_irq; | |
b0e89590 | 408 | int i, err, irq, irqs; |
a9356a04 | 409 | struct platform_device *pmu_device = armpmu->plat_device; |
1b8873a0 | 410 | |
7ae18a57 | 411 | err = reserve_pmu(armpmu->type); |
b0e89590 | 412 | if (err) { |
1b8873a0 | 413 | pr_warning("unable to reserve pmu\n"); |
b0e89590 | 414 | return err; |
1b8873a0 JI |
415 | } |
416 | ||
0e25a5c9 RV |
417 | plat = dev_get_platdata(&pmu_device->dev); |
418 | if (plat && plat->handle_irq) | |
419 | handle_irq = armpmu_platform_irq; | |
420 | else | |
421 | handle_irq = armpmu->handle_irq; | |
422 | ||
0b390e21 | 423 | irqs = min(pmu_device->num_resources, num_possible_cpus()); |
b0e89590 | 424 | if (irqs < 1) { |
1b8873a0 JI |
425 | pr_err("no irqs for PMUs defined\n"); |
426 | return -ENODEV; | |
427 | } | |
428 | ||
b0e89590 | 429 | for (i = 0; i < irqs; ++i) { |
0b390e21 | 430 | err = 0; |
49c006b9 WD |
431 | irq = platform_get_irq(pmu_device, i); |
432 | if (irq < 0) | |
433 | continue; | |
434 | ||
b0e89590 WD |
435 | /* |
436 | * If we have a single PMU interrupt that we can't shift, | |
437 | * assume that we're running on a uniprocessor machine and | |
0b390e21 | 438 | * continue. Otherwise, continue without this interrupt. |
b0e89590 | 439 | */ |
0b390e21 WD |
440 | if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { |
441 | pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", | |
442 | irq, i); | |
443 | continue; | |
b0e89590 WD |
444 | } |
445 | ||
0e25a5c9 | 446 | err = request_irq(irq, handle_irq, |
ddee87f2 | 447 | IRQF_DISABLED | IRQF_NOBALANCING, |
b0e89590 | 448 | "arm-pmu", NULL); |
1b8873a0 | 449 | if (err) { |
b0e89590 WD |
450 | pr_err("unable to request IRQ%d for ARM PMU counters\n", |
451 | irq); | |
0b390e21 WD |
452 | armpmu_release_hardware(); |
453 | return err; | |
1b8873a0 | 454 | } |
1b8873a0 | 455 | |
0b390e21 | 456 | cpumask_set_cpu(i, &armpmu->active_irqs); |
49c006b9 | 457 | } |
1b8873a0 | 458 | |
0b390e21 | 459 | return 0; |
1b8873a0 JI |
460 | } |
461 | ||
1b8873a0 JI |
462 | static void |
463 | hw_perf_event_destroy(struct perf_event *event) | |
464 | { | |
03b7898d MR |
465 | atomic_t *active_events = &armpmu->active_events; |
466 | struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex; | |
467 | ||
468 | if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) { | |
1b8873a0 | 469 | armpmu_release_hardware(); |
03b7898d | 470 | mutex_unlock(pmu_reserve_mutex); |
1b8873a0 JI |
471 | } |
472 | } | |
473 | ||
05d22fde WD |
474 | static int |
475 | event_requires_mode_exclusion(struct perf_event_attr *attr) | |
476 | { | |
477 | return attr->exclude_idle || attr->exclude_user || | |
478 | attr->exclude_kernel || attr->exclude_hv; | |
479 | } | |
480 | ||
1b8873a0 JI |
481 | static int |
482 | __hw_perf_event_init(struct perf_event *event) | |
483 | { | |
484 | struct hw_perf_event *hwc = &event->hw; | |
485 | int mapping, err; | |
486 | ||
487 | /* Decode the generic type into an ARM event identifier. */ | |
488 | if (PERF_TYPE_HARDWARE == event->attr.type) { | |
84fee97a | 489 | mapping = armpmu_map_event(event->attr.config); |
1b8873a0 JI |
490 | } else if (PERF_TYPE_HW_CACHE == event->attr.type) { |
491 | mapping = armpmu_map_cache_event(event->attr.config); | |
492 | } else if (PERF_TYPE_RAW == event->attr.type) { | |
84fee97a | 493 | mapping = armpmu_map_raw_event(event->attr.config); |
1b8873a0 JI |
494 | } else { |
495 | pr_debug("event type %x not supported\n", event->attr.type); | |
496 | return -EOPNOTSUPP; | |
497 | } | |
498 | ||
499 | if (mapping < 0) { | |
500 | pr_debug("event %x:%llx not supported\n", event->attr.type, | |
501 | event->attr.config); | |
502 | return mapping; | |
503 | } | |
504 | ||
05d22fde WD |
505 | /* |
506 | * We don't assign an index until we actually place the event onto | |
507 | * hardware. Use -1 to signify that we haven't decided where to put it | |
508 | * yet. For SMP systems, each core has it's own PMU so we can't do any | |
509 | * clever allocation or constraints checking at this point. | |
510 | */ | |
511 | hwc->idx = -1; | |
512 | hwc->config_base = 0; | |
513 | hwc->config = 0; | |
514 | hwc->event_base = 0; | |
515 | ||
1b8873a0 JI |
516 | /* |
517 | * Check whether we need to exclude the counter from certain modes. | |
1b8873a0 | 518 | */ |
05d22fde WD |
519 | if ((!armpmu->set_event_filter || |
520 | armpmu->set_event_filter(hwc, &event->attr)) && | |
521 | event_requires_mode_exclusion(&event->attr)) { | |
1b8873a0 JI |
522 | pr_debug("ARM performance counters do not support " |
523 | "mode exclusion\n"); | |
524 | return -EPERM; | |
525 | } | |
526 | ||
527 | /* | |
05d22fde | 528 | * Store the event encoding into the config_base field. |
1b8873a0 | 529 | */ |
05d22fde | 530 | hwc->config_base |= (unsigned long)mapping; |
1b8873a0 JI |
531 | |
532 | if (!hwc->sample_period) { | |
533 | hwc->sample_period = armpmu->max_period; | |
534 | hwc->last_period = hwc->sample_period; | |
e7850595 | 535 | local64_set(&hwc->period_left, hwc->sample_period); |
1b8873a0 JI |
536 | } |
537 | ||
538 | err = 0; | |
539 | if (event->group_leader != event) { | |
540 | err = validate_group(event); | |
541 | if (err) | |
542 | return -EINVAL; | |
543 | } | |
544 | ||
545 | return err; | |
546 | } | |
547 | ||
b0a873eb | 548 | static int armpmu_event_init(struct perf_event *event) |
1b8873a0 JI |
549 | { |
550 | int err = 0; | |
03b7898d | 551 | atomic_t *active_events = &armpmu->active_events; |
1b8873a0 | 552 | |
b0a873eb PZ |
553 | switch (event->attr.type) { |
554 | case PERF_TYPE_RAW: | |
555 | case PERF_TYPE_HARDWARE: | |
556 | case PERF_TYPE_HW_CACHE: | |
557 | break; | |
558 | ||
559 | default: | |
560 | return -ENOENT; | |
561 | } | |
562 | ||
1b8873a0 JI |
563 | event->destroy = hw_perf_event_destroy; |
564 | ||
03b7898d MR |
565 | if (!atomic_inc_not_zero(active_events)) { |
566 | mutex_lock(&armpmu->reserve_mutex); | |
567 | if (atomic_read(active_events) == 0) | |
1b8873a0 | 568 | err = armpmu_reserve_hardware(); |
1b8873a0 JI |
569 | |
570 | if (!err) | |
03b7898d MR |
571 | atomic_inc(active_events); |
572 | mutex_unlock(&armpmu->reserve_mutex); | |
1b8873a0 JI |
573 | } |
574 | ||
575 | if (err) | |
b0a873eb | 576 | return err; |
1b8873a0 JI |
577 | |
578 | err = __hw_perf_event_init(event); | |
579 | if (err) | |
580 | hw_perf_event_destroy(event); | |
581 | ||
b0a873eb | 582 | return err; |
1b8873a0 JI |
583 | } |
584 | ||
a4eaf7f1 | 585 | static void armpmu_enable(struct pmu *pmu) |
1b8873a0 JI |
586 | { |
587 | /* Enable all of the perf events on hardware. */ | |
f4f38430 | 588 | int idx, enabled = 0; |
92f701e1 | 589 | struct cpu_hw_events *cpuc = armpmu->get_hw_events(); |
1b8873a0 | 590 | |
ecf5a893 | 591 | for (idx = 0; idx < armpmu->num_events; ++idx) { |
1b8873a0 JI |
592 | struct perf_event *event = cpuc->events[idx]; |
593 | ||
594 | if (!event) | |
595 | continue; | |
596 | ||
597 | armpmu->enable(&event->hw, idx); | |
f4f38430 | 598 | enabled = 1; |
1b8873a0 JI |
599 | } |
600 | ||
f4f38430 WD |
601 | if (enabled) |
602 | armpmu->start(); | |
1b8873a0 JI |
603 | } |
604 | ||
a4eaf7f1 | 605 | static void armpmu_disable(struct pmu *pmu) |
1b8873a0 | 606 | { |
48957155 | 607 | armpmu->stop(); |
1b8873a0 JI |
608 | } |
609 | ||
33696fc0 | 610 | static struct pmu pmu = { |
a4eaf7f1 PZ |
611 | .pmu_enable = armpmu_enable, |
612 | .pmu_disable = armpmu_disable, | |
613 | .event_init = armpmu_event_init, | |
614 | .add = armpmu_add, | |
615 | .del = armpmu_del, | |
616 | .start = armpmu_start, | |
617 | .stop = armpmu_stop, | |
618 | .read = armpmu_read, | |
33696fc0 PZ |
619 | }; |
620 | ||
03b7898d MR |
621 | static void __init armpmu_init(struct arm_pmu *armpmu) |
622 | { | |
623 | atomic_set(&armpmu->active_events, 0); | |
624 | mutex_init(&armpmu->reserve_mutex); | |
625 | } | |
626 | ||
43eab878 WD |
627 | /* Include the PMU-specific implementations. */ |
628 | #include "perf_event_xscale.c" | |
629 | #include "perf_event_v6.c" | |
630 | #include "perf_event_v7.c" | |
49e6a32f | 631 | |
574b69cb WD |
632 | /* |
633 | * Ensure the PMU has sane values out of reset. | |
634 | * This requires SMP to be available, so exists as a separate initcall. | |
635 | */ | |
636 | static int __init | |
637 | armpmu_reset(void) | |
638 | { | |
639 | if (armpmu && armpmu->reset) | |
640 | return on_each_cpu(armpmu->reset, NULL, 1); | |
641 | return 0; | |
642 | } | |
643 | arch_initcall(armpmu_reset); | |
644 | ||
b0e89590 WD |
645 | /* |
646 | * PMU platform driver and devicetree bindings. | |
647 | */ | |
648 | static struct of_device_id armpmu_of_device_ids[] = { | |
649 | {.compatible = "arm,cortex-a9-pmu"}, | |
650 | {.compatible = "arm,cortex-a8-pmu"}, | |
651 | {.compatible = "arm,arm1136-pmu"}, | |
652 | {.compatible = "arm,arm1176-pmu"}, | |
653 | {}, | |
654 | }; | |
655 | ||
656 | static struct platform_device_id armpmu_plat_device_ids[] = { | |
657 | {.name = "arm-pmu"}, | |
658 | {}, | |
659 | }; | |
660 | ||
661 | static int __devinit armpmu_device_probe(struct platform_device *pdev) | |
662 | { | |
a9356a04 | 663 | armpmu->plat_device = pdev; |
b0e89590 WD |
664 | return 0; |
665 | } | |
666 | ||
667 | static struct platform_driver armpmu_driver = { | |
668 | .driver = { | |
669 | .name = "arm-pmu", | |
670 | .of_match_table = armpmu_of_device_ids, | |
671 | }, | |
672 | .probe = armpmu_device_probe, | |
673 | .id_table = armpmu_plat_device_ids, | |
674 | }; | |
675 | ||
676 | static int __init register_pmu_driver(void) | |
677 | { | |
678 | return platform_driver_register(&armpmu_driver); | |
679 | } | |
680 | device_initcall(register_pmu_driver); | |
681 | ||
92f701e1 MR |
682 | static struct cpu_hw_events *armpmu_get_cpu_events(void) |
683 | { | |
684 | return &__get_cpu_var(cpu_hw_events); | |
685 | } | |
686 | ||
687 | static void __init cpu_pmu_init(struct arm_pmu *armpmu) | |
688 | { | |
0f78d2d5 MR |
689 | int cpu; |
690 | for_each_possible_cpu(cpu) { | |
691 | struct cpu_hw_events *events = &per_cpu(cpu_hw_events, cpu); | |
692 | raw_spin_lock_init(&events->pmu_lock); | |
693 | } | |
92f701e1 | 694 | armpmu->get_hw_events = armpmu_get_cpu_events; |
7ae18a57 | 695 | armpmu->type = ARM_PMU_DEVICE_CPU; |
92f701e1 MR |
696 | } |
697 | ||
b0e89590 WD |
698 | /* |
699 | * CPU PMU identification and registration. | |
700 | */ | |
1b8873a0 JI |
701 | static int __init |
702 | init_hw_perf_events(void) | |
703 | { | |
704 | unsigned long cpuid = read_cpuid_id(); | |
705 | unsigned long implementor = (cpuid & 0xFF000000) >> 24; | |
706 | unsigned long part_number = (cpuid & 0xFFF0); | |
707 | ||
49e6a32f | 708 | /* ARM Ltd CPUs. */ |
1b8873a0 JI |
709 | if (0x41 == implementor) { |
710 | switch (part_number) { | |
711 | case 0xB360: /* ARM1136 */ | |
712 | case 0xB560: /* ARM1156 */ | |
713 | case 0xB760: /* ARM1176 */ | |
3cb314ba | 714 | armpmu = armv6pmu_init(); |
1b8873a0 JI |
715 | break; |
716 | case 0xB020: /* ARM11mpcore */ | |
3cb314ba | 717 | armpmu = armv6mpcore_pmu_init(); |
1b8873a0 | 718 | break; |
796d1295 | 719 | case 0xC080: /* Cortex-A8 */ |
3cb314ba | 720 | armpmu = armv7_a8_pmu_init(); |
796d1295 JP |
721 | break; |
722 | case 0xC090: /* Cortex-A9 */ | |
3cb314ba | 723 | armpmu = armv7_a9_pmu_init(); |
796d1295 | 724 | break; |
0c205cbe WD |
725 | case 0xC050: /* Cortex-A5 */ |
726 | armpmu = armv7_a5_pmu_init(); | |
727 | break; | |
14abd038 WD |
728 | case 0xC0F0: /* Cortex-A15 */ |
729 | armpmu = armv7_a15_pmu_init(); | |
730 | break; | |
49e6a32f WD |
731 | } |
732 | /* Intel CPUs [xscale]. */ | |
733 | } else if (0x69 == implementor) { | |
734 | part_number = (cpuid >> 13) & 0x7; | |
735 | switch (part_number) { | |
736 | case 1: | |
3cb314ba | 737 | armpmu = xscale1pmu_init(); |
49e6a32f WD |
738 | break; |
739 | case 2: | |
3cb314ba | 740 | armpmu = xscale2pmu_init(); |
49e6a32f | 741 | break; |
1b8873a0 JI |
742 | } |
743 | } | |
744 | ||
49e6a32f | 745 | if (armpmu) { |
796d1295 | 746 | pr_info("enabled with %s PMU driver, %d counters available\n", |
62994831 | 747 | armpmu->name, armpmu->num_events); |
92f701e1 | 748 | cpu_pmu_init(armpmu); |
03b7898d | 749 | armpmu_init(armpmu); |
48957155 | 750 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
49e6a32f WD |
751 | } else { |
752 | pr_info("no hardware support available\n"); | |
49e6a32f | 753 | } |
1b8873a0 JI |
754 | |
755 | return 0; | |
756 | } | |
004417a6 | 757 | early_initcall(init_hw_perf_events); |
1b8873a0 JI |
758 | |
759 | /* | |
760 | * Callchain handling code. | |
761 | */ | |
1b8873a0 JI |
762 | |
763 | /* | |
764 | * The registers we're interested in are at the end of the variable | |
765 | * length saved register structure. The fp points at the end of this | |
766 | * structure so the address of this struct is: | |
767 | * (struct frame_tail *)(xxx->fp)-1 | |
768 | * | |
769 | * This code has been adapted from the ARM OProfile support. | |
770 | */ | |
771 | struct frame_tail { | |
4d6b7a77 WD |
772 | struct frame_tail __user *fp; |
773 | unsigned long sp; | |
774 | unsigned long lr; | |
1b8873a0 JI |
775 | } __attribute__((packed)); |
776 | ||
777 | /* | |
778 | * Get the return address for a single stackframe and return a pointer to the | |
779 | * next frame tail. | |
780 | */ | |
4d6b7a77 WD |
781 | static struct frame_tail __user * |
782 | user_backtrace(struct frame_tail __user *tail, | |
1b8873a0 JI |
783 | struct perf_callchain_entry *entry) |
784 | { | |
785 | struct frame_tail buftail; | |
786 | ||
787 | /* Also check accessibility of one struct frame_tail beyond */ | |
788 | if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) | |
789 | return NULL; | |
790 | if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) | |
791 | return NULL; | |
792 | ||
70791ce9 | 793 | perf_callchain_store(entry, buftail.lr); |
1b8873a0 JI |
794 | |
795 | /* | |
796 | * Frame pointers should strictly progress back up the stack | |
797 | * (towards higher addresses). | |
798 | */ | |
cb06199b | 799 | if (tail + 1 >= buftail.fp) |
1b8873a0 JI |
800 | return NULL; |
801 | ||
802 | return buftail.fp - 1; | |
803 | } | |
804 | ||
56962b44 FW |
805 | void |
806 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 | 807 | { |
4d6b7a77 | 808 | struct frame_tail __user *tail; |
1b8873a0 | 809 | |
1b8873a0 | 810 | |
4d6b7a77 | 811 | tail = (struct frame_tail __user *)regs->ARM_fp - 1; |
1b8873a0 | 812 | |
860ad782 SR |
813 | while ((entry->nr < PERF_MAX_STACK_DEPTH) && |
814 | tail && !((unsigned long)tail & 0x3)) | |
1b8873a0 JI |
815 | tail = user_backtrace(tail, entry); |
816 | } | |
817 | ||
818 | /* | |
819 | * Gets called by walk_stackframe() for every stackframe. This will be called | |
820 | * whist unwinding the stackframe and is like a subroutine return so we use | |
821 | * the PC. | |
822 | */ | |
823 | static int | |
824 | callchain_trace(struct stackframe *fr, | |
825 | void *data) | |
826 | { | |
827 | struct perf_callchain_entry *entry = data; | |
70791ce9 | 828 | perf_callchain_store(entry, fr->pc); |
1b8873a0 JI |
829 | return 0; |
830 | } | |
831 | ||
56962b44 FW |
832 | void |
833 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 JI |
834 | { |
835 | struct stackframe fr; | |
836 | ||
1b8873a0 JI |
837 | fr.fp = regs->ARM_fp; |
838 | fr.sp = regs->ARM_sp; | |
839 | fr.lr = regs->ARM_lr; | |
840 | fr.pc = regs->ARM_pc; | |
841 | walk_stackframe(&fr, callchain_trace, entry); | |
842 | } |