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Commit | Line | Data |
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1b8873a0 JI |
1 | #undef DEBUG |
2 | ||
3 | /* | |
4 | * ARM performance counter support. | |
5 | * | |
6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | |
43eab878 | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
796d1295 | 8 | * |
1b8873a0 JI |
9 | * This code is based on the sparc64 perf event code, which is in turn based |
10 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace | |
11 | * code. | |
12 | */ | |
13 | #define pr_fmt(fmt) "hw perfevents: " fmt | |
14 | ||
15 | #include <linux/interrupt.h> | |
16 | #include <linux/kernel.h> | |
181193f3 | 17 | #include <linux/module.h> |
1b8873a0 | 18 | #include <linux/perf_event.h> |
49c006b9 | 19 | #include <linux/platform_device.h> |
1b8873a0 JI |
20 | #include <linux/spinlock.h> |
21 | #include <linux/uaccess.h> | |
22 | ||
23 | #include <asm/cputype.h> | |
24 | #include <asm/irq.h> | |
25 | #include <asm/irq_regs.h> | |
26 | #include <asm/pmu.h> | |
27 | #include <asm/stacktrace.h> | |
28 | ||
49c006b9 | 29 | static struct platform_device *pmu_device; |
1b8873a0 JI |
30 | |
31 | /* | |
32 | * Hardware lock to serialize accesses to PMU registers. Needed for the | |
33 | * read/modify/write sequences. | |
34 | */ | |
961ec6da | 35 | static DEFINE_RAW_SPINLOCK(pmu_lock); |
1b8873a0 JI |
36 | |
37 | /* | |
38 | * ARMv6 supports a maximum of 3 events, starting from index 1. If we add | |
39 | * another platform that supports more, we need to increase this to be the | |
40 | * largest of all platforms. | |
796d1295 JP |
41 | * |
42 | * ARMv7 supports up to 32 events: | |
43 | * cycle counter CCNT + 31 events counters CNT0..30. | |
44 | * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters. | |
1b8873a0 | 45 | */ |
796d1295 | 46 | #define ARMPMU_MAX_HWEVENTS 33 |
1b8873a0 JI |
47 | |
48 | /* The events for a given CPU. */ | |
49 | struct cpu_hw_events { | |
50 | /* | |
51 | * The events that are active on the CPU for the given index. Index 0 | |
52 | * is reserved. | |
53 | */ | |
54 | struct perf_event *events[ARMPMU_MAX_HWEVENTS]; | |
55 | ||
56 | /* | |
57 | * A 1 bit for an index indicates that the counter is being used for | |
58 | * an event. A 0 means that the counter can be used. | |
59 | */ | |
60 | unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)]; | |
61 | ||
62 | /* | |
63 | * A 1 bit for an index indicates that the counter is actively being | |
64 | * used. | |
65 | */ | |
66 | unsigned long active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)]; | |
67 | }; | |
4d6b7a77 | 68 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
181193f3 | 69 | |
1b8873a0 | 70 | struct arm_pmu { |
181193f3 | 71 | enum arm_perf_pmu_ids id; |
62994831 | 72 | const char *name; |
1b8873a0 JI |
73 | irqreturn_t (*handle_irq)(int irq_num, void *dev); |
74 | void (*enable)(struct hw_perf_event *evt, int idx); | |
75 | void (*disable)(struct hw_perf_event *evt, int idx); | |
1b8873a0 JI |
76 | int (*get_event_idx)(struct cpu_hw_events *cpuc, |
77 | struct hw_perf_event *hwc); | |
78 | u32 (*read_counter)(int idx); | |
79 | void (*write_counter)(int idx, u32 val); | |
80 | void (*start)(void); | |
81 | void (*stop)(void); | |
574b69cb | 82 | void (*reset)(void *); |
84fee97a WD |
83 | const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] |
84 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
85 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
86 | const unsigned (*event_map)[PERF_COUNT_HW_MAX]; | |
87 | u32 raw_event_mask; | |
1b8873a0 JI |
88 | int num_events; |
89 | u64 max_period; | |
90 | }; | |
91 | ||
92 | /* Set at runtime when we know what CPU type we are. */ | |
a6c93afe | 93 | static struct arm_pmu *armpmu; |
1b8873a0 | 94 | |
181193f3 WD |
95 | enum arm_perf_pmu_ids |
96 | armpmu_get_pmu_id(void) | |
97 | { | |
98 | int id = -ENODEV; | |
99 | ||
100 | if (armpmu != NULL) | |
101 | id = armpmu->id; | |
102 | ||
103 | return id; | |
104 | } | |
105 | EXPORT_SYMBOL_GPL(armpmu_get_pmu_id); | |
106 | ||
929f5199 WD |
107 | int |
108 | armpmu_get_max_events(void) | |
109 | { | |
110 | int max_events = 0; | |
111 | ||
112 | if (armpmu != NULL) | |
113 | max_events = armpmu->num_events; | |
114 | ||
115 | return max_events; | |
116 | } | |
117 | EXPORT_SYMBOL_GPL(armpmu_get_max_events); | |
118 | ||
3bf101ba MF |
119 | int perf_num_counters(void) |
120 | { | |
121 | return armpmu_get_max_events(); | |
122 | } | |
123 | EXPORT_SYMBOL_GPL(perf_num_counters); | |
124 | ||
1b8873a0 JI |
125 | #define HW_OP_UNSUPPORTED 0xFFFF |
126 | ||
127 | #define C(_x) \ | |
128 | PERF_COUNT_HW_CACHE_##_x | |
129 | ||
130 | #define CACHE_OP_UNSUPPORTED 0xFFFF | |
131 | ||
1b8873a0 JI |
132 | static int |
133 | armpmu_map_cache_event(u64 config) | |
134 | { | |
135 | unsigned int cache_type, cache_op, cache_result, ret; | |
136 | ||
137 | cache_type = (config >> 0) & 0xff; | |
138 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
139 | return -EINVAL; | |
140 | ||
141 | cache_op = (config >> 8) & 0xff; | |
142 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
143 | return -EINVAL; | |
144 | ||
145 | cache_result = (config >> 16) & 0xff; | |
146 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
147 | return -EINVAL; | |
148 | ||
84fee97a | 149 | ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result]; |
1b8873a0 JI |
150 | |
151 | if (ret == CACHE_OP_UNSUPPORTED) | |
152 | return -ENOENT; | |
153 | ||
154 | return ret; | |
155 | } | |
156 | ||
84fee97a WD |
157 | static int |
158 | armpmu_map_event(u64 config) | |
159 | { | |
160 | int mapping = (*armpmu->event_map)[config]; | |
161 | return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping; | |
162 | } | |
163 | ||
164 | static int | |
165 | armpmu_map_raw_event(u64 config) | |
166 | { | |
167 | return (int)(config & armpmu->raw_event_mask); | |
168 | } | |
169 | ||
1b8873a0 JI |
170 | static int |
171 | armpmu_event_set_period(struct perf_event *event, | |
172 | struct hw_perf_event *hwc, | |
173 | int idx) | |
174 | { | |
e7850595 | 175 | s64 left = local64_read(&hwc->period_left); |
1b8873a0 JI |
176 | s64 period = hwc->sample_period; |
177 | int ret = 0; | |
178 | ||
179 | if (unlikely(left <= -period)) { | |
180 | left = period; | |
e7850595 | 181 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
182 | hwc->last_period = period; |
183 | ret = 1; | |
184 | } | |
185 | ||
186 | if (unlikely(left <= 0)) { | |
187 | left += period; | |
e7850595 | 188 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
189 | hwc->last_period = period; |
190 | ret = 1; | |
191 | } | |
192 | ||
193 | if (left > (s64)armpmu->max_period) | |
194 | left = armpmu->max_period; | |
195 | ||
e7850595 | 196 | local64_set(&hwc->prev_count, (u64)-left); |
1b8873a0 JI |
197 | |
198 | armpmu->write_counter(idx, (u64)(-left) & 0xffffffff); | |
199 | ||
200 | perf_event_update_userpage(event); | |
201 | ||
202 | return ret; | |
203 | } | |
204 | ||
205 | static u64 | |
206 | armpmu_event_update(struct perf_event *event, | |
207 | struct hw_perf_event *hwc, | |
a737823d | 208 | int idx, int overflow) |
1b8873a0 | 209 | { |
a737823d | 210 | u64 delta, prev_raw_count, new_raw_count; |
1b8873a0 JI |
211 | |
212 | again: | |
e7850595 | 213 | prev_raw_count = local64_read(&hwc->prev_count); |
1b8873a0 JI |
214 | new_raw_count = armpmu->read_counter(idx); |
215 | ||
e7850595 | 216 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
1b8873a0 JI |
217 | new_raw_count) != prev_raw_count) |
218 | goto again; | |
219 | ||
a737823d WD |
220 | new_raw_count &= armpmu->max_period; |
221 | prev_raw_count &= armpmu->max_period; | |
222 | ||
223 | if (overflow) | |
6759788b | 224 | delta = armpmu->max_period - prev_raw_count + new_raw_count + 1; |
a737823d WD |
225 | else |
226 | delta = new_raw_count - prev_raw_count; | |
1b8873a0 | 227 | |
e7850595 PZ |
228 | local64_add(delta, &event->count); |
229 | local64_sub(delta, &hwc->period_left); | |
1b8873a0 JI |
230 | |
231 | return new_raw_count; | |
232 | } | |
233 | ||
234 | static void | |
a4eaf7f1 | 235 | armpmu_read(struct perf_event *event) |
1b8873a0 | 236 | { |
1b8873a0 | 237 | struct hw_perf_event *hwc = &event->hw; |
1b8873a0 | 238 | |
a4eaf7f1 PZ |
239 | /* Don't read disabled counters! */ |
240 | if (hwc->idx < 0) | |
241 | return; | |
1b8873a0 | 242 | |
a737823d | 243 | armpmu_event_update(event, hwc, hwc->idx, 0); |
1b8873a0 JI |
244 | } |
245 | ||
246 | static void | |
a4eaf7f1 | 247 | armpmu_stop(struct perf_event *event, int flags) |
1b8873a0 JI |
248 | { |
249 | struct hw_perf_event *hwc = &event->hw; | |
250 | ||
a4eaf7f1 | 251 | if (!armpmu) |
1b8873a0 JI |
252 | return; |
253 | ||
a4eaf7f1 PZ |
254 | /* |
255 | * ARM pmu always has to update the counter, so ignore | |
256 | * PERF_EF_UPDATE, see comments in armpmu_start(). | |
257 | */ | |
258 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
259 | armpmu->disable(hwc, hwc->idx); | |
260 | barrier(); /* why? */ | |
a737823d | 261 | armpmu_event_update(event, hwc, hwc->idx, 0); |
a4eaf7f1 PZ |
262 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
263 | } | |
1b8873a0 JI |
264 | } |
265 | ||
266 | static void | |
a4eaf7f1 | 267 | armpmu_start(struct perf_event *event, int flags) |
1b8873a0 JI |
268 | { |
269 | struct hw_perf_event *hwc = &event->hw; | |
270 | ||
a4eaf7f1 PZ |
271 | if (!armpmu) |
272 | return; | |
273 | ||
274 | /* | |
275 | * ARM pmu always has to reprogram the period, so ignore | |
276 | * PERF_EF_RELOAD, see the comment below. | |
277 | */ | |
278 | if (flags & PERF_EF_RELOAD) | |
279 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
280 | ||
281 | hwc->state = 0; | |
1b8873a0 JI |
282 | /* |
283 | * Set the period again. Some counters can't be stopped, so when we | |
a4eaf7f1 | 284 | * were stopped we simply disabled the IRQ source and the counter |
1b8873a0 JI |
285 | * may have been left counting. If we don't do this step then we may |
286 | * get an interrupt too soon or *way* too late if the overflow has | |
287 | * happened since disabling. | |
288 | */ | |
289 | armpmu_event_set_period(event, hwc, hwc->idx); | |
290 | armpmu->enable(hwc, hwc->idx); | |
291 | } | |
292 | ||
a4eaf7f1 PZ |
293 | static void |
294 | armpmu_del(struct perf_event *event, int flags) | |
295 | { | |
296 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
297 | struct hw_perf_event *hwc = &event->hw; | |
298 | int idx = hwc->idx; | |
299 | ||
300 | WARN_ON(idx < 0); | |
301 | ||
302 | clear_bit(idx, cpuc->active_mask); | |
303 | armpmu_stop(event, PERF_EF_UPDATE); | |
304 | cpuc->events[idx] = NULL; | |
305 | clear_bit(idx, cpuc->used_mask); | |
306 | ||
307 | perf_event_update_userpage(event); | |
308 | } | |
309 | ||
1b8873a0 | 310 | static int |
a4eaf7f1 | 311 | armpmu_add(struct perf_event *event, int flags) |
1b8873a0 JI |
312 | { |
313 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
314 | struct hw_perf_event *hwc = &event->hw; | |
315 | int idx; | |
316 | int err = 0; | |
317 | ||
33696fc0 | 318 | perf_pmu_disable(event->pmu); |
24cd7f54 | 319 | |
1b8873a0 JI |
320 | /* If we don't have a space for the counter then finish early. */ |
321 | idx = armpmu->get_event_idx(cpuc, hwc); | |
322 | if (idx < 0) { | |
323 | err = idx; | |
324 | goto out; | |
325 | } | |
326 | ||
327 | /* | |
328 | * If there is an event in the counter we are going to use then make | |
329 | * sure it is disabled. | |
330 | */ | |
331 | event->hw.idx = idx; | |
332 | armpmu->disable(hwc, idx); | |
333 | cpuc->events[idx] = event; | |
334 | set_bit(idx, cpuc->active_mask); | |
335 | ||
a4eaf7f1 PZ |
336 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
337 | if (flags & PERF_EF_START) | |
338 | armpmu_start(event, PERF_EF_RELOAD); | |
1b8873a0 JI |
339 | |
340 | /* Propagate our changes to the userspace mapping. */ | |
341 | perf_event_update_userpage(event); | |
342 | ||
343 | out: | |
33696fc0 | 344 | perf_pmu_enable(event->pmu); |
1b8873a0 JI |
345 | return err; |
346 | } | |
347 | ||
b0a873eb | 348 | static struct pmu pmu; |
1b8873a0 JI |
349 | |
350 | static int | |
351 | validate_event(struct cpu_hw_events *cpuc, | |
352 | struct perf_event *event) | |
353 | { | |
354 | struct hw_perf_event fake_event = event->hw; | |
355 | ||
65b4711f WD |
356 | if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF) |
357 | return 1; | |
1b8873a0 JI |
358 | |
359 | return armpmu->get_event_idx(cpuc, &fake_event) >= 0; | |
360 | } | |
361 | ||
362 | static int | |
363 | validate_group(struct perf_event *event) | |
364 | { | |
365 | struct perf_event *sibling, *leader = event->group_leader; | |
366 | struct cpu_hw_events fake_pmu; | |
367 | ||
368 | memset(&fake_pmu, 0, sizeof(fake_pmu)); | |
369 | ||
370 | if (!validate_event(&fake_pmu, leader)) | |
371 | return -ENOSPC; | |
372 | ||
373 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { | |
374 | if (!validate_event(&fake_pmu, sibling)) | |
375 | return -ENOSPC; | |
376 | } | |
377 | ||
378 | if (!validate_event(&fake_pmu, event)) | |
379 | return -ENOSPC; | |
380 | ||
381 | return 0; | |
382 | } | |
383 | ||
0e25a5c9 RV |
384 | static irqreturn_t armpmu_platform_irq(int irq, void *dev) |
385 | { | |
386 | struct arm_pmu_platdata *plat = dev_get_platdata(&pmu_device->dev); | |
387 | ||
388 | return plat->handle_irq(irq, dev, armpmu->handle_irq); | |
389 | } | |
390 | ||
1b8873a0 JI |
391 | static int |
392 | armpmu_reserve_hardware(void) | |
393 | { | |
0e25a5c9 RV |
394 | struct arm_pmu_platdata *plat; |
395 | irq_handler_t handle_irq; | |
b0e89590 | 396 | int i, err, irq, irqs; |
1b8873a0 | 397 | |
b0e89590 WD |
398 | err = reserve_pmu(ARM_PMU_DEVICE_CPU); |
399 | if (err) { | |
1b8873a0 | 400 | pr_warning("unable to reserve pmu\n"); |
b0e89590 | 401 | return err; |
1b8873a0 JI |
402 | } |
403 | ||
b0e89590 | 404 | irqs = pmu_device->num_resources; |
1b8873a0 | 405 | |
0e25a5c9 RV |
406 | plat = dev_get_platdata(&pmu_device->dev); |
407 | if (plat && plat->handle_irq) | |
408 | handle_irq = armpmu_platform_irq; | |
409 | else | |
410 | handle_irq = armpmu->handle_irq; | |
411 | ||
b0e89590 | 412 | if (irqs < 1) { |
1b8873a0 JI |
413 | pr_err("no irqs for PMUs defined\n"); |
414 | return -ENODEV; | |
415 | } | |
416 | ||
b0e89590 | 417 | for (i = 0; i < irqs; ++i) { |
49c006b9 WD |
418 | irq = platform_get_irq(pmu_device, i); |
419 | if (irq < 0) | |
420 | continue; | |
421 | ||
b0e89590 WD |
422 | /* |
423 | * If we have a single PMU interrupt that we can't shift, | |
424 | * assume that we're running on a uniprocessor machine and | |
425 | * continue. | |
426 | */ | |
427 | err = irq_set_affinity(irq, cpumask_of(i)); | |
428 | if (err && irqs > 1) { | |
429 | pr_err("unable to set irq affinity (irq=%d, cpu=%u)\n", | |
430 | irq, i); | |
431 | break; | |
432 | } | |
433 | ||
0e25a5c9 | 434 | err = request_irq(irq, handle_irq, |
ddee87f2 | 435 | IRQF_DISABLED | IRQF_NOBALANCING, |
b0e89590 | 436 | "arm-pmu", NULL); |
1b8873a0 | 437 | if (err) { |
b0e89590 WD |
438 | pr_err("unable to request IRQ%d for ARM PMU counters\n", |
439 | irq); | |
1b8873a0 JI |
440 | break; |
441 | } | |
442 | } | |
443 | ||
444 | if (err) { | |
49c006b9 WD |
445 | for (i = i - 1; i >= 0; --i) { |
446 | irq = platform_get_irq(pmu_device, i); | |
447 | if (irq >= 0) | |
448 | free_irq(irq, NULL); | |
449 | } | |
f12482c9 | 450 | release_pmu(ARM_PMU_DEVICE_CPU); |
1b8873a0 JI |
451 | } |
452 | ||
453 | return err; | |
454 | } | |
455 | ||
456 | static void | |
457 | armpmu_release_hardware(void) | |
458 | { | |
49c006b9 | 459 | int i, irq; |
1b8873a0 | 460 | |
49c006b9 WD |
461 | for (i = pmu_device->num_resources - 1; i >= 0; --i) { |
462 | irq = platform_get_irq(pmu_device, i); | |
463 | if (irq >= 0) | |
464 | free_irq(irq, NULL); | |
465 | } | |
1b8873a0 JI |
466 | armpmu->stop(); |
467 | ||
f12482c9 | 468 | release_pmu(ARM_PMU_DEVICE_CPU); |
1b8873a0 JI |
469 | } |
470 | ||
471 | static atomic_t active_events = ATOMIC_INIT(0); | |
472 | static DEFINE_MUTEX(pmu_reserve_mutex); | |
473 | ||
474 | static void | |
475 | hw_perf_event_destroy(struct perf_event *event) | |
476 | { | |
477 | if (atomic_dec_and_mutex_lock(&active_events, &pmu_reserve_mutex)) { | |
478 | armpmu_release_hardware(); | |
479 | mutex_unlock(&pmu_reserve_mutex); | |
480 | } | |
481 | } | |
482 | ||
483 | static int | |
484 | __hw_perf_event_init(struct perf_event *event) | |
485 | { | |
486 | struct hw_perf_event *hwc = &event->hw; | |
487 | int mapping, err; | |
488 | ||
489 | /* Decode the generic type into an ARM event identifier. */ | |
490 | if (PERF_TYPE_HARDWARE == event->attr.type) { | |
84fee97a | 491 | mapping = armpmu_map_event(event->attr.config); |
1b8873a0 JI |
492 | } else if (PERF_TYPE_HW_CACHE == event->attr.type) { |
493 | mapping = armpmu_map_cache_event(event->attr.config); | |
494 | } else if (PERF_TYPE_RAW == event->attr.type) { | |
84fee97a | 495 | mapping = armpmu_map_raw_event(event->attr.config); |
1b8873a0 JI |
496 | } else { |
497 | pr_debug("event type %x not supported\n", event->attr.type); | |
498 | return -EOPNOTSUPP; | |
499 | } | |
500 | ||
501 | if (mapping < 0) { | |
502 | pr_debug("event %x:%llx not supported\n", event->attr.type, | |
503 | event->attr.config); | |
504 | return mapping; | |
505 | } | |
506 | ||
507 | /* | |
508 | * Check whether we need to exclude the counter from certain modes. | |
509 | * The ARM performance counters are on all of the time so if someone | |
510 | * has asked us for some excludes then we have to fail. | |
511 | */ | |
512 | if (event->attr.exclude_kernel || event->attr.exclude_user || | |
513 | event->attr.exclude_hv || event->attr.exclude_idle) { | |
514 | pr_debug("ARM performance counters do not support " | |
515 | "mode exclusion\n"); | |
516 | return -EPERM; | |
517 | } | |
518 | ||
519 | /* | |
520 | * We don't assign an index until we actually place the event onto | |
521 | * hardware. Use -1 to signify that we haven't decided where to put it | |
522 | * yet. For SMP systems, each core has it's own PMU so we can't do any | |
523 | * clever allocation or constraints checking at this point. | |
524 | */ | |
525 | hwc->idx = -1; | |
526 | ||
527 | /* | |
528 | * Store the event encoding into the config_base field. config and | |
529 | * event_base are unused as the only 2 things we need to know are | |
530 | * the event mapping and the counter to use. The counter to use is | |
531 | * also the indx and the config_base is the event type. | |
532 | */ | |
533 | hwc->config_base = (unsigned long)mapping; | |
534 | hwc->config = 0; | |
535 | hwc->event_base = 0; | |
536 | ||
537 | if (!hwc->sample_period) { | |
538 | hwc->sample_period = armpmu->max_period; | |
539 | hwc->last_period = hwc->sample_period; | |
e7850595 | 540 | local64_set(&hwc->period_left, hwc->sample_period); |
1b8873a0 JI |
541 | } |
542 | ||
543 | err = 0; | |
544 | if (event->group_leader != event) { | |
545 | err = validate_group(event); | |
546 | if (err) | |
547 | return -EINVAL; | |
548 | } | |
549 | ||
550 | return err; | |
551 | } | |
552 | ||
b0a873eb | 553 | static int armpmu_event_init(struct perf_event *event) |
1b8873a0 JI |
554 | { |
555 | int err = 0; | |
556 | ||
b0a873eb PZ |
557 | switch (event->attr.type) { |
558 | case PERF_TYPE_RAW: | |
559 | case PERF_TYPE_HARDWARE: | |
560 | case PERF_TYPE_HW_CACHE: | |
561 | break; | |
562 | ||
563 | default: | |
564 | return -ENOENT; | |
565 | } | |
566 | ||
1b8873a0 | 567 | if (!armpmu) |
b0a873eb | 568 | return -ENODEV; |
1b8873a0 JI |
569 | |
570 | event->destroy = hw_perf_event_destroy; | |
571 | ||
572 | if (!atomic_inc_not_zero(&active_events)) { | |
1b8873a0 JI |
573 | mutex_lock(&pmu_reserve_mutex); |
574 | if (atomic_read(&active_events) == 0) { | |
575 | err = armpmu_reserve_hardware(); | |
576 | } | |
577 | ||
578 | if (!err) | |
579 | atomic_inc(&active_events); | |
580 | mutex_unlock(&pmu_reserve_mutex); | |
581 | } | |
582 | ||
583 | if (err) | |
b0a873eb | 584 | return err; |
1b8873a0 JI |
585 | |
586 | err = __hw_perf_event_init(event); | |
587 | if (err) | |
588 | hw_perf_event_destroy(event); | |
589 | ||
b0a873eb | 590 | return err; |
1b8873a0 JI |
591 | } |
592 | ||
a4eaf7f1 | 593 | static void armpmu_enable(struct pmu *pmu) |
1b8873a0 JI |
594 | { |
595 | /* Enable all of the perf events on hardware. */ | |
f4f38430 | 596 | int idx, enabled = 0; |
1b8873a0 JI |
597 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
598 | ||
599 | if (!armpmu) | |
600 | return; | |
601 | ||
602 | for (idx = 0; idx <= armpmu->num_events; ++idx) { | |
603 | struct perf_event *event = cpuc->events[idx]; | |
604 | ||
605 | if (!event) | |
606 | continue; | |
607 | ||
608 | armpmu->enable(&event->hw, idx); | |
f4f38430 | 609 | enabled = 1; |
1b8873a0 JI |
610 | } |
611 | ||
f4f38430 WD |
612 | if (enabled) |
613 | armpmu->start(); | |
1b8873a0 JI |
614 | } |
615 | ||
a4eaf7f1 | 616 | static void armpmu_disable(struct pmu *pmu) |
1b8873a0 JI |
617 | { |
618 | if (armpmu) | |
619 | armpmu->stop(); | |
620 | } | |
621 | ||
33696fc0 | 622 | static struct pmu pmu = { |
a4eaf7f1 PZ |
623 | .pmu_enable = armpmu_enable, |
624 | .pmu_disable = armpmu_disable, | |
625 | .event_init = armpmu_event_init, | |
626 | .add = armpmu_add, | |
627 | .del = armpmu_del, | |
628 | .start = armpmu_start, | |
629 | .stop = armpmu_stop, | |
630 | .read = armpmu_read, | |
33696fc0 PZ |
631 | }; |
632 | ||
43eab878 WD |
633 | /* Include the PMU-specific implementations. */ |
634 | #include "perf_event_xscale.c" | |
635 | #include "perf_event_v6.c" | |
636 | #include "perf_event_v7.c" | |
49e6a32f | 637 | |
574b69cb WD |
638 | /* |
639 | * Ensure the PMU has sane values out of reset. | |
640 | * This requires SMP to be available, so exists as a separate initcall. | |
641 | */ | |
642 | static int __init | |
643 | armpmu_reset(void) | |
644 | { | |
645 | if (armpmu && armpmu->reset) | |
646 | return on_each_cpu(armpmu->reset, NULL, 1); | |
647 | return 0; | |
648 | } | |
649 | arch_initcall(armpmu_reset); | |
650 | ||
b0e89590 WD |
651 | /* |
652 | * PMU platform driver and devicetree bindings. | |
653 | */ | |
654 | static struct of_device_id armpmu_of_device_ids[] = { | |
655 | {.compatible = "arm,cortex-a9-pmu"}, | |
656 | {.compatible = "arm,cortex-a8-pmu"}, | |
657 | {.compatible = "arm,arm1136-pmu"}, | |
658 | {.compatible = "arm,arm1176-pmu"}, | |
659 | {}, | |
660 | }; | |
661 | ||
662 | static struct platform_device_id armpmu_plat_device_ids[] = { | |
663 | {.name = "arm-pmu"}, | |
664 | {}, | |
665 | }; | |
666 | ||
667 | static int __devinit armpmu_device_probe(struct platform_device *pdev) | |
668 | { | |
669 | pmu_device = pdev; | |
670 | return 0; | |
671 | } | |
672 | ||
673 | static struct platform_driver armpmu_driver = { | |
674 | .driver = { | |
675 | .name = "arm-pmu", | |
676 | .of_match_table = armpmu_of_device_ids, | |
677 | }, | |
678 | .probe = armpmu_device_probe, | |
679 | .id_table = armpmu_plat_device_ids, | |
680 | }; | |
681 | ||
682 | static int __init register_pmu_driver(void) | |
683 | { | |
684 | return platform_driver_register(&armpmu_driver); | |
685 | } | |
686 | device_initcall(register_pmu_driver); | |
687 | ||
688 | /* | |
689 | * CPU PMU identification and registration. | |
690 | */ | |
1b8873a0 JI |
691 | static int __init |
692 | init_hw_perf_events(void) | |
693 | { | |
694 | unsigned long cpuid = read_cpuid_id(); | |
695 | unsigned long implementor = (cpuid & 0xFF000000) >> 24; | |
696 | unsigned long part_number = (cpuid & 0xFFF0); | |
697 | ||
49e6a32f | 698 | /* ARM Ltd CPUs. */ |
1b8873a0 JI |
699 | if (0x41 == implementor) { |
700 | switch (part_number) { | |
701 | case 0xB360: /* ARM1136 */ | |
702 | case 0xB560: /* ARM1156 */ | |
703 | case 0xB760: /* ARM1176 */ | |
3cb314ba | 704 | armpmu = armv6pmu_init(); |
1b8873a0 JI |
705 | break; |
706 | case 0xB020: /* ARM11mpcore */ | |
3cb314ba | 707 | armpmu = armv6mpcore_pmu_init(); |
1b8873a0 | 708 | break; |
796d1295 | 709 | case 0xC080: /* Cortex-A8 */ |
3cb314ba | 710 | armpmu = armv7_a8_pmu_init(); |
796d1295 JP |
711 | break; |
712 | case 0xC090: /* Cortex-A9 */ | |
3cb314ba | 713 | armpmu = armv7_a9_pmu_init(); |
796d1295 | 714 | break; |
0c205cbe WD |
715 | case 0xC050: /* Cortex-A5 */ |
716 | armpmu = armv7_a5_pmu_init(); | |
717 | break; | |
14abd038 WD |
718 | case 0xC0F0: /* Cortex-A15 */ |
719 | armpmu = armv7_a15_pmu_init(); | |
720 | break; | |
49e6a32f WD |
721 | } |
722 | /* Intel CPUs [xscale]. */ | |
723 | } else if (0x69 == implementor) { | |
724 | part_number = (cpuid >> 13) & 0x7; | |
725 | switch (part_number) { | |
726 | case 1: | |
3cb314ba | 727 | armpmu = xscale1pmu_init(); |
49e6a32f WD |
728 | break; |
729 | case 2: | |
3cb314ba | 730 | armpmu = xscale2pmu_init(); |
49e6a32f | 731 | break; |
1b8873a0 JI |
732 | } |
733 | } | |
734 | ||
49e6a32f | 735 | if (armpmu) { |
796d1295 | 736 | pr_info("enabled with %s PMU driver, %d counters available\n", |
62994831 | 737 | armpmu->name, armpmu->num_events); |
49e6a32f WD |
738 | } else { |
739 | pr_info("no hardware support available\n"); | |
49e6a32f | 740 | } |
1b8873a0 | 741 | |
2e80a82a | 742 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
b0a873eb | 743 | |
1b8873a0 JI |
744 | return 0; |
745 | } | |
004417a6 | 746 | early_initcall(init_hw_perf_events); |
1b8873a0 JI |
747 | |
748 | /* | |
749 | * Callchain handling code. | |
750 | */ | |
1b8873a0 JI |
751 | |
752 | /* | |
753 | * The registers we're interested in are at the end of the variable | |
754 | * length saved register structure. The fp points at the end of this | |
755 | * structure so the address of this struct is: | |
756 | * (struct frame_tail *)(xxx->fp)-1 | |
757 | * | |
758 | * This code has been adapted from the ARM OProfile support. | |
759 | */ | |
760 | struct frame_tail { | |
4d6b7a77 WD |
761 | struct frame_tail __user *fp; |
762 | unsigned long sp; | |
763 | unsigned long lr; | |
1b8873a0 JI |
764 | } __attribute__((packed)); |
765 | ||
766 | /* | |
767 | * Get the return address for a single stackframe and return a pointer to the | |
768 | * next frame tail. | |
769 | */ | |
4d6b7a77 WD |
770 | static struct frame_tail __user * |
771 | user_backtrace(struct frame_tail __user *tail, | |
1b8873a0 JI |
772 | struct perf_callchain_entry *entry) |
773 | { | |
774 | struct frame_tail buftail; | |
775 | ||
776 | /* Also check accessibility of one struct frame_tail beyond */ | |
777 | if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) | |
778 | return NULL; | |
779 | if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) | |
780 | return NULL; | |
781 | ||
70791ce9 | 782 | perf_callchain_store(entry, buftail.lr); |
1b8873a0 JI |
783 | |
784 | /* | |
785 | * Frame pointers should strictly progress back up the stack | |
786 | * (towards higher addresses). | |
787 | */ | |
cb06199b | 788 | if (tail + 1 >= buftail.fp) |
1b8873a0 JI |
789 | return NULL; |
790 | ||
791 | return buftail.fp - 1; | |
792 | } | |
793 | ||
56962b44 FW |
794 | void |
795 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 | 796 | { |
4d6b7a77 | 797 | struct frame_tail __user *tail; |
1b8873a0 | 798 | |
1b8873a0 | 799 | |
4d6b7a77 | 800 | tail = (struct frame_tail __user *)regs->ARM_fp - 1; |
1b8873a0 | 801 | |
860ad782 SR |
802 | while ((entry->nr < PERF_MAX_STACK_DEPTH) && |
803 | tail && !((unsigned long)tail & 0x3)) | |
1b8873a0 JI |
804 | tail = user_backtrace(tail, entry); |
805 | } | |
806 | ||
807 | /* | |
808 | * Gets called by walk_stackframe() for every stackframe. This will be called | |
809 | * whist unwinding the stackframe and is like a subroutine return so we use | |
810 | * the PC. | |
811 | */ | |
812 | static int | |
813 | callchain_trace(struct stackframe *fr, | |
814 | void *data) | |
815 | { | |
816 | struct perf_callchain_entry *entry = data; | |
70791ce9 | 817 | perf_callchain_store(entry, fr->pc); |
1b8873a0 JI |
818 | return 0; |
819 | } | |
820 | ||
56962b44 FW |
821 | void |
822 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 JI |
823 | { |
824 | struct stackframe fr; | |
825 | ||
1b8873a0 JI |
826 | fr.fp = regs->ARM_fp; |
827 | fr.sp = regs->ARM_sp; | |
828 | fr.lr = regs->ARM_lr; | |
829 | fr.pc = regs->ARM_pc; | |
830 | walk_stackframe(&fr, callchain_trace, entry); | |
831 | } |