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Commit | Line | Data |
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5505b206 WD |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License version 2 as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program; if not, write to the Free Software | |
13 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
14 | * | |
15 | * Copyright (C) 2012 ARM Limited | |
16 | * | |
17 | * Author: Will Deacon <will.deacon@arm.com> | |
18 | */ | |
19 | #define pr_fmt(fmt) "CPU PMU: " fmt | |
20 | ||
21 | #include <linux/bitmap.h> | |
22 | #include <linux/export.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/of.h> | |
25 | #include <linux/platform_device.h> | |
513c99ce | 26 | #include <linux/slab.h> |
5505b206 | 27 | #include <linux/spinlock.h> |
bbd64559 SB |
28 | #include <linux/irq.h> |
29 | #include <linux/irqdesc.h> | |
5505b206 WD |
30 | |
31 | #include <asm/cputype.h> | |
32 | #include <asm/irq_regs.h> | |
33 | #include <asm/pmu.h> | |
34 | ||
35 | /* Set at runtime when we know what CPU type we are. */ | |
7a2a24cb | 36 | static struct arm_pmu *__oprofile_cpu_pmu; |
5505b206 | 37 | |
5505b206 WD |
38 | /* |
39 | * Despite the names, these two functions are CPU-specific and are used | |
40 | * by the OProfile/perf code. | |
41 | */ | |
42 | const char *perf_pmu_name(void) | |
43 | { | |
7a2a24cb | 44 | if (!__oprofile_cpu_pmu) |
5505b206 WD |
45 | return NULL; |
46 | ||
7a2a24cb | 47 | return __oprofile_cpu_pmu->name; |
5505b206 WD |
48 | } |
49 | EXPORT_SYMBOL_GPL(perf_pmu_name); | |
50 | ||
51 | int perf_num_counters(void) | |
52 | { | |
53 | int max_events = 0; | |
54 | ||
7a2a24cb MR |
55 | if (__oprofile_cpu_pmu != NULL) |
56 | max_events = __oprofile_cpu_pmu->num_events; | |
5505b206 WD |
57 | |
58 | return max_events; | |
59 | } | |
60 | EXPORT_SYMBOL_GPL(perf_num_counters); | |
61 | ||
62 | /* Include the PMU-specific implementations. */ | |
5505b206 WD |
63 | #include "perf_event_v6.c" |
64 | #include "perf_event_v7.c" | |
65 | ||
bbd64559 SB |
66 | static void cpu_pmu_enable_percpu_irq(void *data) |
67 | { | |
505013bc | 68 | int irq = *(int *)data; |
bbd64559 SB |
69 | |
70 | enable_percpu_irq(irq, IRQ_TYPE_NONE); | |
bbd64559 SB |
71 | } |
72 | ||
73 | static void cpu_pmu_disable_percpu_irq(void *data) | |
74 | { | |
505013bc | 75 | int irq = *(int *)data; |
bbd64559 | 76 | |
bbd64559 SB |
77 | disable_percpu_irq(irq); |
78 | } | |
79 | ||
ed6f2a52 | 80 | static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu) |
051f1b13 SH |
81 | { |
82 | int i, irq, irqs; | |
83 | struct platform_device *pmu_device = cpu_pmu->plat_device; | |
5ebd9200 | 84 | struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events; |
051f1b13 SH |
85 | |
86 | irqs = min(pmu_device->num_resources, num_possible_cpus()); | |
87 | ||
bbd64559 SB |
88 | irq = platform_get_irq(pmu_device, 0); |
89 | if (irq >= 0 && irq_is_percpu(irq)) { | |
505013bc | 90 | on_each_cpu(cpu_pmu_disable_percpu_irq, &irq, 1); |
5ebd9200 | 91 | free_percpu_irq(irq, &hw_events->percpu_pmu); |
bbd64559 SB |
92 | } else { |
93 | for (i = 0; i < irqs; ++i) { | |
9fd85eb5 WD |
94 | int cpu = i; |
95 | ||
96 | if (cpu_pmu->irq_affinity) | |
97 | cpu = cpu_pmu->irq_affinity[i]; | |
98 | ||
99 | if (!cpumask_test_and_clear_cpu(cpu, &cpu_pmu->active_irqs)) | |
bbd64559 SB |
100 | continue; |
101 | irq = platform_get_irq(pmu_device, i); | |
102 | if (irq >= 0) | |
9fd85eb5 | 103 | free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, cpu)); |
bbd64559 | 104 | } |
051f1b13 SH |
105 | } |
106 | } | |
107 | ||
ed6f2a52 | 108 | static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler) |
051f1b13 SH |
109 | { |
110 | int i, err, irq, irqs; | |
111 | struct platform_device *pmu_device = cpu_pmu->plat_device; | |
5ebd9200 | 112 | struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events; |
051f1b13 SH |
113 | |
114 | if (!pmu_device) | |
115 | return -ENODEV; | |
116 | ||
117 | irqs = min(pmu_device->num_resources, num_possible_cpus()); | |
118 | if (irqs < 1) { | |
52a5566e | 119 | pr_warn_once("perf/ARM: No irqs for PMU defined, sampling events not supported\n"); |
edcb4d3c | 120 | return 0; |
051f1b13 SH |
121 | } |
122 | ||
bbd64559 SB |
123 | irq = platform_get_irq(pmu_device, 0); |
124 | if (irq >= 0 && irq_is_percpu(irq)) { | |
5ebd9200 MR |
125 | err = request_percpu_irq(irq, handler, "arm-pmu", |
126 | &hw_events->percpu_pmu); | |
051f1b13 SH |
127 | if (err) { |
128 | pr_err("unable to request IRQ%d for ARM PMU counters\n", | |
129 | irq); | |
130 | return err; | |
131 | } | |
505013bc | 132 | on_each_cpu(cpu_pmu_enable_percpu_irq, &irq, 1); |
bbd64559 SB |
133 | } else { |
134 | for (i = 0; i < irqs; ++i) { | |
9fd85eb5 WD |
135 | int cpu = i; |
136 | ||
bbd64559 SB |
137 | err = 0; |
138 | irq = platform_get_irq(pmu_device, i); | |
139 | if (irq < 0) | |
140 | continue; | |
141 | ||
9fd85eb5 WD |
142 | if (cpu_pmu->irq_affinity) |
143 | cpu = cpu_pmu->irq_affinity[i]; | |
144 | ||
bbd64559 SB |
145 | /* |
146 | * If we have a single PMU interrupt that we can't shift, | |
147 | * assume that we're running on a uniprocessor machine and | |
148 | * continue. Otherwise, continue without this interrupt. | |
149 | */ | |
9fd85eb5 | 150 | if (irq_set_affinity(irq, cpumask_of(cpu)) && irqs > 1) { |
8b521cb2 | 151 | pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n", |
9fd85eb5 | 152 | irq, cpu); |
bbd64559 SB |
153 | continue; |
154 | } | |
155 | ||
156 | err = request_irq(irq, handler, | |
157 | IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu", | |
9fd85eb5 | 158 | per_cpu_ptr(&hw_events->percpu_pmu, cpu)); |
bbd64559 SB |
159 | if (err) { |
160 | pr_err("unable to request IRQ%d for ARM PMU counters\n", | |
161 | irq); | |
162 | return err; | |
163 | } | |
164 | ||
9fd85eb5 | 165 | cpumask_set_cpu(cpu, &cpu_pmu->active_irqs); |
bbd64559 | 166 | } |
051f1b13 SH |
167 | } |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
af66abfe MR |
172 | /* |
173 | * PMU hardware loses all context when a CPU goes offline. | |
174 | * When a CPU is hotplugged back in, since some hardware registers are | |
175 | * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading | |
176 | * junk values out of them. | |
177 | */ | |
178 | static int cpu_pmu_notify(struct notifier_block *b, unsigned long action, | |
179 | void *hcpu) | |
180 | { | |
cc88116d | 181 | int cpu = (unsigned long)hcpu; |
af66abfe MR |
182 | struct arm_pmu *pmu = container_of(b, struct arm_pmu, hotplug_nb); |
183 | ||
184 | if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING) | |
185 | return NOTIFY_DONE; | |
186 | ||
cc88116d MR |
187 | if (!cpumask_test_cpu(cpu, &pmu->supported_cpus)) |
188 | return NOTIFY_DONE; | |
189 | ||
af66abfe MR |
190 | if (pmu->reset) |
191 | pmu->reset(pmu); | |
192 | else | |
193 | return NOTIFY_DONE; | |
194 | ||
195 | return NOTIFY_OK; | |
196 | } | |
197 | ||
abdf655a | 198 | static int cpu_pmu_init(struct arm_pmu *cpu_pmu) |
5505b206 | 199 | { |
af66abfe | 200 | int err; |
5505b206 | 201 | int cpu; |
abdf655a MR |
202 | struct pmu_hw_events __percpu *cpu_hw_events; |
203 | ||
204 | cpu_hw_events = alloc_percpu(struct pmu_hw_events); | |
205 | if (!cpu_hw_events) | |
206 | return -ENOMEM; | |
207 | ||
af66abfe MR |
208 | cpu_pmu->hotplug_nb.notifier_call = cpu_pmu_notify; |
209 | err = register_cpu_notifier(&cpu_pmu->hotplug_nb); | |
210 | if (err) | |
211 | goto out_hw_events; | |
212 | ||
5505b206 | 213 | for_each_possible_cpu(cpu) { |
abdf655a | 214 | struct pmu_hw_events *events = per_cpu_ptr(cpu_hw_events, cpu); |
5505b206 | 215 | raw_spin_lock_init(&events->pmu_lock); |
5ebd9200 | 216 | events->percpu_pmu = cpu_pmu; |
5505b206 | 217 | } |
051f1b13 | 218 | |
abdf655a | 219 | cpu_pmu->hw_events = cpu_hw_events; |
051f1b13 SH |
220 | cpu_pmu->request_irq = cpu_pmu_request_irq; |
221 | cpu_pmu->free_irq = cpu_pmu_free_irq; | |
5505b206 WD |
222 | |
223 | /* Ensure the PMU has sane values out of reset. */ | |
1764c591 | 224 | if (cpu_pmu->reset) |
cc88116d MR |
225 | on_each_cpu_mask(&cpu_pmu->supported_cpus, cpu_pmu->reset, |
226 | cpu_pmu, 1); | |
edcb4d3c VW |
227 | |
228 | /* If no interrupts available, set the corresponding capability flag */ | |
229 | if (!platform_get_irq(cpu_pmu->plat_device, 0)) | |
230 | cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; | |
abdf655a MR |
231 | |
232 | return 0; | |
af66abfe MR |
233 | |
234 | out_hw_events: | |
235 | free_percpu(cpu_hw_events); | |
236 | return err; | |
abdf655a MR |
237 | } |
238 | ||
239 | static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu) | |
240 | { | |
af66abfe | 241 | unregister_cpu_notifier(&cpu_pmu->hotplug_nb); |
abdf655a | 242 | free_percpu(cpu_pmu->hw_events); |
5505b206 WD |
243 | } |
244 | ||
5505b206 WD |
245 | /* |
246 | * PMU platform driver and devicetree bindings. | |
247 | */ | |
444d2d33 | 248 | static const struct of_device_id cpu_pmu_of_device_ids[] = { |
03eff46c | 249 | {.compatible = "arm,cortex-a17-pmu", .data = armv7_a17_pmu_init}, |
5505b206 | 250 | {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init}, |
8e781f65 | 251 | {.compatible = "arm,cortex-a12-pmu", .data = armv7_a12_pmu_init}, |
5505b206 WD |
252 | {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init}, |
253 | {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init}, | |
254 | {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init}, | |
255 | {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init}, | |
256 | {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init}, | |
3d1ff755 MR |
257 | {.compatible = "arm,arm1176-pmu", .data = armv6_1176_pmu_init}, |
258 | {.compatible = "arm,arm1136-pmu", .data = armv6_1136_pmu_init}, | |
2a3391cd | 259 | {.compatible = "qcom,krait-pmu", .data = krait_pmu_init}, |
341e42c4 SB |
260 | {.compatible = "qcom,scorpion-pmu", .data = scorpion_pmu_init}, |
261 | {.compatible = "qcom,scorpion-mp-pmu", .data = scorpion_mp_pmu_init}, | |
5505b206 WD |
262 | {}, |
263 | }; | |
264 | ||
351a102d | 265 | static struct platform_device_id cpu_pmu_plat_device_ids[] = { |
5505b206 | 266 | {.name = "arm-pmu"}, |
253d8c3d MR |
267 | {.name = "armv6-pmu"}, |
268 | {.name = "armv7-pmu"}, | |
5505b206 WD |
269 | {}, |
270 | }; | |
271 | ||
548a86ca MR |
272 | static const struct pmu_probe_info pmu_probe_table[] = { |
273 | ARM_PMU_PROBE(ARM_CPU_PART_ARM1136, armv6_1136_pmu_init), | |
274 | ARM_PMU_PROBE(ARM_CPU_PART_ARM1156, armv6_1156_pmu_init), | |
275 | ARM_PMU_PROBE(ARM_CPU_PART_ARM1176, armv6_1176_pmu_init), | |
276 | ARM_PMU_PROBE(ARM_CPU_PART_ARM11MPCORE, armv6mpcore_pmu_init), | |
277 | ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A8, armv7_a8_pmu_init), | |
278 | ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A9, armv7_a9_pmu_init), | |
548a86ca MR |
279 | { /* sentinel value */ } |
280 | }; | |
281 | ||
5505b206 WD |
282 | /* |
283 | * CPU PMU identification and probing. | |
284 | */ | |
cfdad299 MR |
285 | static int probe_current_pmu(struct arm_pmu *pmu, |
286 | const struct pmu_probe_info *info) | |
5505b206 | 287 | { |
5505b206 | 288 | int cpu = get_cpu(); |
548a86ca | 289 | unsigned int cpuid = read_cpuid_id(); |
513c99ce | 290 | int ret = -ENODEV; |
5505b206 WD |
291 | |
292 | pr_info("probing PMU on CPU %d\n", cpu); | |
293 | ||
cfdad299 | 294 | for (; info->init != NULL; info++) { |
548a86ca MR |
295 | if ((cpuid & info->mask) != info->cpuid) |
296 | continue; | |
297 | ret = info->init(pmu); | |
af040ffc | 298 | break; |
5505b206 WD |
299 | } |
300 | ||
301 | put_cpu(); | |
513c99ce | 302 | return ret; |
5505b206 WD |
303 | } |
304 | ||
64d0d394 | 305 | static int of_pmu_irq_cfg(struct arm_pmu *pmu) |
9fd85eb5 WD |
306 | { |
307 | int i; | |
64d0d394 | 308 | struct platform_device *pdev = pmu->plat_device; |
9fd85eb5 WD |
309 | int *irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL); |
310 | ||
311 | if (!irqs) | |
312 | return -ENOMEM; | |
313 | ||
314 | for (i = 0; i < pdev->num_resources; ++i) { | |
315 | struct device_node *dn; | |
316 | int cpu; | |
317 | ||
318 | dn = of_parse_phandle(pdev->dev.of_node, "interrupt-affinity", | |
319 | i); | |
320 | if (!dn) { | |
321 | pr_warn("Failed to parse %s/interrupt-affinity[%d]\n", | |
322 | of_node_full_name(dn), i); | |
323 | break; | |
324 | } | |
325 | ||
326 | for_each_possible_cpu(cpu) | |
327 | if (arch_find_n_match_cpu_physical_id(dn, cpu, NULL)) | |
328 | break; | |
329 | ||
330 | of_node_put(dn); | |
331 | if (cpu >= nr_cpu_ids) { | |
332 | pr_warn("Failed to find logical CPU for %s\n", | |
333 | dn->name); | |
334 | break; | |
335 | } | |
336 | ||
337 | irqs[i] = cpu; | |
cc88116d | 338 | cpumask_set_cpu(cpu, &pmu->supported_cpus); |
9fd85eb5 WD |
339 | } |
340 | ||
cc88116d | 341 | if (i == pdev->num_resources) { |
64d0d394 | 342 | pmu->irq_affinity = irqs; |
cc88116d | 343 | } else { |
9fd85eb5 | 344 | kfree(irqs); |
cc88116d MR |
345 | cpumask_setall(&pmu->supported_cpus); |
346 | } | |
9fd85eb5 WD |
347 | |
348 | return 0; | |
349 | } | |
350 | ||
cfdad299 MR |
351 | int arm_pmu_device_probe(struct platform_device *pdev, |
352 | const struct of_device_id *of_table, | |
353 | const struct pmu_probe_info *probe_table) | |
5505b206 WD |
354 | { |
355 | const struct of_device_id *of_id; | |
261521f1 | 356 | const int (*init_fn)(struct arm_pmu *); |
5505b206 | 357 | struct device_node *node = pdev->dev.of_node; |
513c99ce SH |
358 | struct arm_pmu *pmu; |
359 | int ret = -ENODEV; | |
5505b206 | 360 | |
513c99ce SH |
361 | pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL); |
362 | if (!pmu) { | |
0f2a2101 | 363 | pr_info("failed to allocate PMU device!\n"); |
513c99ce SH |
364 | return -ENOMEM; |
365 | } | |
366 | ||
7a2a24cb MR |
367 | if (!__oprofile_cpu_pmu) |
368 | __oprofile_cpu_pmu = pmu; | |
369 | ||
370 | pmu->plat_device = pdev; | |
3a3967ed | 371 | |
cfdad299 | 372 | if (node && (of_id = of_match_node(of_table, pdev->dev.of_node))) { |
5505b206 | 373 | init_fn = of_id->data; |
9fd85eb5 | 374 | |
64d0d394 | 375 | ret = of_pmu_irq_cfg(pmu); |
9fd85eb5 WD |
376 | if (!ret) |
377 | ret = init_fn(pmu); | |
5505b206 | 378 | } else { |
cfdad299 | 379 | ret = probe_current_pmu(pmu, probe_table); |
cc88116d | 380 | cpumask_setall(&pmu->supported_cpus); |
5505b206 WD |
381 | } |
382 | ||
513c99ce | 383 | if (ret) { |
0f2a2101 | 384 | pr_info("failed to probe PMU!\n"); |
76b8a0e4 | 385 | goto out_free; |
513c99ce | 386 | } |
5505b206 | 387 | |
7a2a24cb | 388 | ret = cpu_pmu_init(pmu); |
abdf655a MR |
389 | if (ret) |
390 | goto out_free; | |
391 | ||
7a2a24cb | 392 | ret = armpmu_register(pmu, -1); |
abdf655a MR |
393 | if (ret) |
394 | goto out_destroy; | |
5505b206 | 395 | |
abdf655a | 396 | return 0; |
76b8a0e4 | 397 | |
abdf655a | 398 | out_destroy: |
7a2a24cb | 399 | cpu_pmu_destroy(pmu); |
76b8a0e4 | 400 | out_free: |
0f2a2101 | 401 | pr_info("failed to register PMU devices!\n"); |
76b8a0e4 MR |
402 | kfree(pmu); |
403 | return ret; | |
5505b206 WD |
404 | } |
405 | ||
cfdad299 MR |
406 | static int cpu_pmu_device_probe(struct platform_device *pdev) |
407 | { | |
408 | return arm_pmu_device_probe(pdev, cpu_pmu_of_device_ids, | |
409 | pmu_probe_table); | |
410 | } | |
411 | ||
5505b206 WD |
412 | static struct platform_driver cpu_pmu_driver = { |
413 | .driver = { | |
414 | .name = "arm-pmu", | |
5505b206 WD |
415 | .of_match_table = cpu_pmu_of_device_ids, |
416 | }, | |
417 | .probe = cpu_pmu_device_probe, | |
418 | .id_table = cpu_pmu_plat_device_ids, | |
419 | }; | |
420 | ||
421 | static int __init register_pmu_driver(void) | |
422 | { | |
af66abfe | 423 | return platform_driver_register(&cpu_pmu_driver); |
5505b206 WD |
424 | } |
425 | device_initcall(register_pmu_driver); |