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f6b0fa02 | 1 | #include <linux/linkage.h> |
941aefac | 2 | #include <linux/threads.h> |
f6b0fa02 RK |
3 | #include <asm/asm-offsets.h> |
4 | #include <asm/assembler.h> | |
5 | #include <asm/glue-cache.h> | |
6 | #include <asm/glue-proc.h> | |
7 | #include <asm/system.h> | |
8 | .text | |
9 | ||
10 | /* | |
11 | * Save CPU state for a suspend | |
12 | * r1 = v:p offset | |
3799bbe5 | 13 | * r2 = suspend function arg0 |
e8856a87 RK |
14 | * r3 = suspend function |
15 | * Note: does not return until system resumes | |
f6b0fa02 | 16 | */ |
2c74a0ce | 17 | ENTRY(__cpu_suspend) |
e8856a87 | 18 | stmfd sp!, {r4 - r11, lr} |
f6b0fa02 RK |
19 | #ifdef MULTI_CPU |
20 | ldr r10, =processor | |
8111eaa6 | 21 | ldr r5, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state |
f6b0fa02 | 22 | ldr ip, [r10, #CPU_DO_RESUME] @ virtual resume function |
941aefac | 23 | #else |
8111eaa6 | 24 | ldr r5, =cpu_suspend_size |
6b5f6ab0 | 25 | ldr ip, =cpu_do_resume |
3fd431bd | 26 | #endif |
8111eaa6 RK |
27 | mov r6, sp @ current virtual SP |
28 | sub sp, sp, r5 @ allocate CPU state on stack | |
f6b0fa02 | 29 | mov r0, sp @ save pointer |
6b5f6ab0 | 30 | add ip, ip, r1 @ convert resume fn to phys |
8111eaa6 RK |
31 | stmfd sp!, {r1, r6, ip} @ save v:p, virt SP, phys resume fn |
32 | ldr r5, =sleep_save_sp | |
33 | add r6, sp, r1 @ convert SP to phys | |
e8856a87 | 34 | stmfd sp!, {r2, r3} @ save suspend func arg and pointer |
941aefac RK |
35 | #ifdef CONFIG_SMP |
36 | ALT_SMP(mrc p15, 0, lr, c0, c0, 5) | |
37 | ALT_UP(mov lr, #0) | |
38 | and lr, lr, #15 | |
8111eaa6 | 39 | str r6, [r5, lr, lsl #2] @ save phys SP |
941aefac | 40 | #else |
8111eaa6 | 41 | str r6, [r5] @ save phys SP |
941aefac | 42 | #endif |
3fd431bd RK |
43 | #ifdef MULTI_CPU |
44 | mov lr, pc | |
45 | ldr pc, [r10, #CPU_DO_SUSPEND] @ save CPU state | |
46 | #else | |
f6b0fa02 RK |
47 | bl cpu_do_suspend |
48 | #endif | |
49 | ||
50 | @ flush data cache | |
51 | #ifdef MULTI_CACHE | |
52 | ldr r10, =cpu_cache | |
3799bbe5 | 53 | mov lr, pc |
f6b0fa02 RK |
54 | ldr pc, [r10, #CACHE_FLUSH_KERN_ALL] |
55 | #else | |
3799bbe5 | 56 | bl __cpuc_flush_kern_all |
f6b0fa02 | 57 | #endif |
3799bbe5 | 58 | ldmfd sp!, {r0, pc} @ call suspend fn |
2c74a0ce | 59 | ENDPROC(__cpu_suspend) |
f6b0fa02 RK |
60 | .ltorg |
61 | ||
62 | /* | |
63 | * r0 = control register value | |
64 | * r1 = v:p offset (preserved by cpu_do_resume) | |
65 | * r2 = phys page table base | |
66 | * r3 = L1 section flags | |
67 | */ | |
68 | ENTRY(cpu_resume_mmu) | |
69 | adr r4, cpu_resume_turn_mmu_on | |
70 | mov r4, r4, lsr #20 | |
71 | orr r3, r3, r4, lsl #20 | |
72 | ldr r5, [r2, r4, lsl #2] @ save old mapping | |
73 | str r3, [r2, r4, lsl #2] @ setup 1:1 mapping for mmu code | |
74 | sub r2, r2, r1 | |
75 | ldr r3, =cpu_resume_after_mmu | |
76 | bic r1, r0, #CR_C @ ensure D-cache is disabled | |
77 | b cpu_resume_turn_mmu_on | |
78 | ENDPROC(cpu_resume_mmu) | |
79 | .ltorg | |
80 | .align 5 | |
81 | cpu_resume_turn_mmu_on: | |
82 | mcr p15, 0, r1, c1, c0, 0 @ turn on MMU, I-cache, etc | |
83 | mrc p15, 0, r1, c0, c0, 0 @ read id reg | |
84 | mov r1, r1 | |
85 | mov r1, r1 | |
86 | mov pc, r3 @ jump to virtual address | |
87 | ENDPROC(cpu_resume_turn_mmu_on) | |
88 | cpu_resume_after_mmu: | |
89 | str r5, [r2, r4, lsl #2] @ restore old mapping | |
90 | mcr p15, 0, r0, c1, c0, 0 @ turn on D-cache | |
14cd8fd5 | 91 | bl cpu_init @ restore the und/abt/irq banked regs |
5fa94c81 | 92 | ldmfd sp!, {r4 - r11, pc} |
f6b0fa02 RK |
93 | ENDPROC(cpu_resume_after_mmu) |
94 | ||
95 | /* | |
96 | * Note: Yes, part of the following code is located into the .data section. | |
97 | * This is to allow sleep_save_sp to be accessed with a relative load | |
98 | * while we can't rely on any MMU translation. We could have put | |
99 | * sleep_save_sp in the .text section as well, but some setups might | |
100 | * insist on it to be truly read-only. | |
101 | */ | |
102 | .data | |
103 | .align | |
104 | ENTRY(cpu_resume) | |
941aefac RK |
105 | #ifdef CONFIG_SMP |
106 | adr r0, sleep_save_sp | |
107 | ALT_SMP(mrc p15, 0, r1, c0, c0, 5) | |
108 | ALT_UP(mov r1, #0) | |
109 | and r1, r1, #15 | |
110 | ldr r0, [r0, r1, lsl #2] @ stack phys addr | |
111 | #else | |
f6b0fa02 | 112 | ldr r0, sleep_save_sp @ stack phys addr |
941aefac | 113 | #endif |
fb4fe87d | 114 | setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off |
2fefbcd5 RK |
115 | @ load v:p, stack, resume fn |
116 | ARM( ldmia r0!, {r1, sp, pc} ) | |
117 | THUMB( ldmia r0!, {r1, r2, r3} ) | |
fb4fe87d | 118 | THUMB( mov sp, r2 ) |
2fefbcd5 | 119 | THUMB( bx r3 ) |
f6b0fa02 RK |
120 | ENDPROC(cpu_resume) |
121 | ||
122 | sleep_save_sp: | |
941aefac RK |
123 | .rept CONFIG_NR_CPUS |
124 | .long 0 @ preserve stack phys ptr here | |
125 | .endr |