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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/smp.c | |
3 | * | |
4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
c97d4869 | 10 | #include <linux/module.h> |
1da177e4 LT |
11 | #include <linux/delay.h> |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
68e21be2 | 14 | #include <linux/sched/mm.h> |
ef8bd77f | 15 | #include <linux/sched/hotplug.h> |
68db0cf1 | 16 | #include <linux/sched/task_stack.h> |
1da177e4 LT |
17 | #include <linux/interrupt.h> |
18 | #include <linux/cache.h> | |
19 | #include <linux/profile.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/mm.h> | |
4e950f6f | 22 | #include <linux/err.h> |
1da177e4 | 23 | #include <linux/cpu.h> |
1da177e4 | 24 | #include <linux/seq_file.h> |
c97d4869 | 25 | #include <linux/irq.h> |
96f0e003 | 26 | #include <linux/nmi.h> |
bc28248e RK |
27 | #include <linux/percpu.h> |
28 | #include <linux/clockchips.h> | |
3c030bea | 29 | #include <linux/completion.h> |
ec971ea5 | 30 | #include <linux/cpufreq.h> |
bf18525f | 31 | #include <linux/irq_work.h> |
1da177e4 | 32 | |
60063497 | 33 | #include <linux/atomic.h> |
abcee5fb | 34 | #include <asm/smp.h> |
1da177e4 LT |
35 | #include <asm/cacheflush.h> |
36 | #include <asm/cpu.h> | |
42578c82 | 37 | #include <asm/cputype.h> |
5a567d78 | 38 | #include <asm/exception.h> |
8903826d | 39 | #include <asm/idmap.h> |
c9018aab | 40 | #include <asm/topology.h> |
e65f38ed RK |
41 | #include <asm/mmu_context.h> |
42 | #include <asm/pgtable.h> | |
43 | #include <asm/pgalloc.h> | |
1da177e4 | 44 | #include <asm/processor.h> |
37b05b63 | 45 | #include <asm/sections.h> |
1da177e4 LT |
46 | #include <asm/tlbflush.h> |
47 | #include <asm/ptrace.h> | |
d6257288 | 48 | #include <asm/smp_plat.h> |
4588c34d | 49 | #include <asm/virt.h> |
abcee5fb | 50 | #include <asm/mach/arch.h> |
eb08375e | 51 | #include <asm/mpu.h> |
1da177e4 | 52 | |
365ec7b1 NP |
53 | #define CREATE_TRACE_POINTS |
54 | #include <trace/events/ipi.h> | |
55 | ||
e65f38ed RK |
56 | /* |
57 | * as from 2.5, kernels no longer have an init_tasks structure | |
58 | * so we need some other way of telling a new secondary core | |
59 | * where to place its SVC stack | |
60 | */ | |
61 | struct secondary_data secondary_data; | |
62 | ||
28e8e29c MZ |
63 | /* |
64 | * control for which core is the next to come out of the secondary | |
65 | * boot "holding pen" | |
66 | */ | |
8bd26e3a | 67 | volatile int pen_release = -1; |
28e8e29c | 68 | |
1da177e4 | 69 | enum ipi_msg_type { |
559a5939 SB |
70 | IPI_WAKEUP, |
71 | IPI_TIMER, | |
1da177e4 LT |
72 | IPI_RESCHEDULE, |
73 | IPI_CALL_FUNC, | |
74 | IPI_CPU_STOP, | |
bf18525f | 75 | IPI_IRQ_WORK, |
5135d875 | 76 | IPI_COMPLETION, |
e7273ff4 MZ |
77 | IPI_CPU_BACKTRACE, |
78 | /* | |
79 | * SGI8-15 can be reserved by secure firmware, and thus may | |
80 | * not be usable by the kernel. Please keep the above limited | |
81 | * to at most 8 entries. | |
82 | */ | |
1da177e4 LT |
83 | }; |
84 | ||
149c2415 RK |
85 | static DECLARE_COMPLETION(cpu_running); |
86 | ||
7619751f | 87 | static struct smp_operations smp_ops __ro_after_init; |
abcee5fb | 88 | |
4caa9dda | 89 | void __init smp_set_ops(const struct smp_operations *ops) |
abcee5fb MZ |
90 | { |
91 | if (ops) | |
92 | smp_ops = *ops; | |
93 | }; | |
94 | ||
4756dcbf CC |
95 | static unsigned long get_arch_pgd(pgd_t *pgd) |
96 | { | |
b2c3e38a RK |
97 | #ifdef CONFIG_ARM_LPAE |
98 | return __phys_to_pfn(virt_to_phys(pgd)); | |
99 | #else | |
100 | return virt_to_phys(pgd); | |
101 | #endif | |
4756dcbf CC |
102 | } |
103 | ||
8bd26e3a | 104 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
1da177e4 | 105 | { |
1da177e4 LT |
106 | int ret; |
107 | ||
084bb5bc GU |
108 | if (!smp_ops.smp_boot_secondary) |
109 | return -ENOSYS; | |
110 | ||
e65f38ed RK |
111 | /* |
112 | * We need to tell the secondary core where to find | |
113 | * its stack and the page tables. | |
114 | */ | |
32d39a93 | 115 | secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; |
eb08375e JA |
116 | #ifdef CONFIG_ARM_MPU |
117 | secondary_data.mpu_rgn_szr = mpu_rgn_info.rgns[MPU_RAM_REGION].drsr; | |
118 | #endif | |
119 | ||
c4a1f032 | 120 | #ifdef CONFIG_MMU |
b2c3e38a | 121 | secondary_data.pgdir = virt_to_phys(idmap_pgd); |
4756dcbf | 122 | secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir); |
c4a1f032 | 123 | #endif |
efcfc46e | 124 | sync_cache_w(&secondary_data); |
e65f38ed | 125 | |
1da177e4 LT |
126 | /* |
127 | * Now bring the CPU into our world. | |
128 | */ | |
084bb5bc | 129 | ret = smp_ops.smp_boot_secondary(cpu, idle); |
e65f38ed | 130 | if (ret == 0) { |
e65f38ed RK |
131 | /* |
132 | * CPU was successfully started, wait for it | |
133 | * to come online or time out. | |
134 | */ | |
149c2415 RK |
135 | wait_for_completion_timeout(&cpu_running, |
136 | msecs_to_jiffies(1000)); | |
e65f38ed | 137 | |
58613cd1 RK |
138 | if (!cpu_online(cpu)) { |
139 | pr_crit("CPU%u: failed to come online\n", cpu); | |
e65f38ed | 140 | ret = -EIO; |
58613cd1 RK |
141 | } |
142 | } else { | |
143 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
e65f38ed RK |
144 | } |
145 | ||
e65f38ed | 146 | |
eb08375e | 147 | memset(&secondary_data, 0, sizeof(secondary_data)); |
1da177e4 LT |
148 | return ret; |
149 | } | |
150 | ||
abcee5fb | 151 | /* platform specific SMP operations */ |
ac6c7998 | 152 | void __init smp_init_cpus(void) |
abcee5fb MZ |
153 | { |
154 | if (smp_ops.smp_init_cpus) | |
155 | smp_ops.smp_init_cpus(); | |
156 | } | |
157 | ||
fee3fd4f GU |
158 | int platform_can_secondary_boot(void) |
159 | { | |
160 | return !!smp_ops.smp_boot_secondary; | |
161 | } | |
162 | ||
2103f6cb SW |
163 | int platform_can_cpu_hotplug(void) |
164 | { | |
165 | #ifdef CONFIG_HOTPLUG_CPU | |
166 | if (smp_ops.cpu_kill) | |
167 | return 1; | |
168 | #endif | |
169 | ||
170 | return 0; | |
171 | } | |
172 | ||
a054a811 | 173 | #ifdef CONFIG_HOTPLUG_CPU |
ac6c7998 | 174 | static int platform_cpu_kill(unsigned int cpu) |
abcee5fb MZ |
175 | { |
176 | if (smp_ops.cpu_kill) | |
177 | return smp_ops.cpu_kill(cpu); | |
178 | return 1; | |
179 | } | |
180 | ||
ac6c7998 | 181 | static int platform_cpu_disable(unsigned int cpu) |
abcee5fb MZ |
182 | { |
183 | if (smp_ops.cpu_disable) | |
184 | return smp_ops.cpu_disable(cpu); | |
185 | ||
787047ee SB |
186 | return 0; |
187 | } | |
188 | ||
189 | int platform_can_hotplug_cpu(unsigned int cpu) | |
190 | { | |
191 | /* cpu_die must be specified to support hotplug */ | |
192 | if (!smp_ops.cpu_die) | |
193 | return 0; | |
194 | ||
195 | if (smp_ops.cpu_can_disable) | |
196 | return smp_ops.cpu_can_disable(cpu); | |
197 | ||
abcee5fb MZ |
198 | /* |
199 | * By default, allow disabling all CPUs except the first one, | |
200 | * since this is special on a lot of platforms, e.g. because | |
201 | * of clock tick interrupts. | |
202 | */ | |
787047ee | 203 | return cpu != 0; |
abcee5fb | 204 | } |
787047ee | 205 | |
a054a811 RK |
206 | /* |
207 | * __cpu_disable runs on the processor to be shutdown. | |
208 | */ | |
8bd26e3a | 209 | int __cpu_disable(void) |
a054a811 RK |
210 | { |
211 | unsigned int cpu = smp_processor_id(); | |
a054a811 RK |
212 | int ret; |
213 | ||
8e2a43f5 | 214 | ret = platform_cpu_disable(cpu); |
a054a811 RK |
215 | if (ret) |
216 | return ret; | |
217 | ||
218 | /* | |
219 | * Take this CPU offline. Once we clear this, we can't return, | |
220 | * and we must not schedule until we're ready to give up the cpu. | |
221 | */ | |
e03cdade | 222 | set_cpu_online(cpu, false); |
a054a811 RK |
223 | |
224 | /* | |
225 | * OK - migrate IRQs away from this CPU | |
226 | */ | |
227 | migrate_irqs(); | |
228 | ||
229 | /* | |
230 | * Flush user cache and TLB mappings, and then remove this CPU | |
231 | * from the vm mask set of all processes. | |
e6b866e9 LP |
232 | * |
233 | * Caches are flushed to the Level of Unification Inner Shareable | |
234 | * to write-back dirty lines to unified caches shared by all CPUs. | |
a054a811 | 235 | */ |
e6b866e9 | 236 | flush_cache_louis(); |
a054a811 RK |
237 | local_flush_tlb_all(); |
238 | ||
3eaa73bd | 239 | clear_tasks_mm_cpumask(cpu); |
a054a811 RK |
240 | |
241 | return 0; | |
242 | } | |
243 | ||
3c030bea RK |
244 | static DECLARE_COMPLETION(cpu_died); |
245 | ||
a054a811 RK |
246 | /* |
247 | * called on the thread which is asking for a CPU to be shutdown - | |
248 | * waits until shutdown has completed, or it is timed out. | |
249 | */ | |
8bd26e3a | 250 | void __cpu_die(unsigned int cpu) |
a054a811 | 251 | { |
3c030bea RK |
252 | if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) { |
253 | pr_err("CPU%u: cpu didn't die\n", cpu); | |
254 | return; | |
255 | } | |
035e7875 | 256 | pr_debug("CPU%u: shutdown\n", cpu); |
3c030bea | 257 | |
51acdfd1 RK |
258 | /* |
259 | * platform_cpu_kill() is generally expected to do the powering off | |
260 | * and/or cutting of clocks to the dying CPU. Optionally, this may | |
261 | * be done by the CPU which is dying in preference to supporting | |
262 | * this call, but that means there is _no_ synchronisation between | |
263 | * the requesting CPU and the dying CPU actually losing power. | |
264 | */ | |
a054a811 | 265 | if (!platform_cpu_kill(cpu)) |
4ed89f22 | 266 | pr_err("CPU%u: unable to kill\n", cpu); |
a054a811 RK |
267 | } |
268 | ||
269 | /* | |
270 | * Called from the idle thread for the CPU which has been shutdown. | |
271 | * | |
272 | * Note that we disable IRQs here, but do not re-enable them | |
273 | * before returning to the caller. This is also the behaviour | |
274 | * of the other hotplug-cpu capable cores, so presumably coming | |
275 | * out of idle fixes this. | |
276 | */ | |
9205b797 | 277 | void arch_cpu_idle_dead(void) |
a054a811 RK |
278 | { |
279 | unsigned int cpu = smp_processor_id(); | |
280 | ||
a054a811 RK |
281 | idle_task_exit(); |
282 | ||
f36d3401 | 283 | local_irq_disable(); |
f36d3401 | 284 | |
51acdfd1 RK |
285 | /* |
286 | * Flush the data out of the L1 cache for this CPU. This must be | |
287 | * before the completion to ensure that data is safely written out | |
288 | * before platform_cpu_kill() gets called - which may disable | |
289 | * *this* CPU and power down its cache. | |
290 | */ | |
291 | flush_cache_louis(); | |
292 | ||
293 | /* | |
294 | * Tell __cpu_die() that this CPU is now safe to dispose of. Once | |
295 | * this returns, power and/or clocks can be removed at any point | |
296 | * from this CPU and its cache by platform_cpu_kill(). | |
297 | */ | |
aa033810 | 298 | complete(&cpu_died); |
3c030bea | 299 | |
a054a811 | 300 | /* |
51acdfd1 RK |
301 | * Ensure that the cache lines associated with that completion are |
302 | * written out. This covers the case where _this_ CPU is doing the | |
303 | * powering down, to ensure that the completion is visible to the | |
304 | * CPU waiting for this one. | |
305 | */ | |
306 | flush_cache_louis(); | |
307 | ||
308 | /* | |
309 | * The actual CPU shutdown procedure is at least platform (if not | |
310 | * CPU) specific. This may remove power, or it may simply spin. | |
311 | * | |
312 | * Platforms are generally expected *NOT* to return from this call, | |
313 | * although there are some which do because they have no way to | |
314 | * power down the CPU. These platforms are the _only_ reason we | |
315 | * have a return path which uses the fragment of assembly below. | |
316 | * | |
317 | * The return path should not be used for platforms which can | |
318 | * power off the CPU. | |
a054a811 | 319 | */ |
0a301110 RK |
320 | if (smp_ops.cpu_die) |
321 | smp_ops.cpu_die(cpu); | |
a054a811 | 322 | |
668bc386 RK |
323 | pr_warn("CPU%u: smp_ops.cpu_die() returned, trying to resuscitate\n", |
324 | cpu); | |
325 | ||
a054a811 RK |
326 | /* |
327 | * Do not return to the idle loop - jump back to the secondary | |
328 | * cpu initialisation. There's some initialisation which needs | |
329 | * to be repeated to undo the effects of taking the CPU offline. | |
330 | */ | |
331 | __asm__("mov sp, %0\n" | |
faabfa08 | 332 | " mov fp, #0\n" |
a054a811 RK |
333 | " b secondary_start_kernel" |
334 | : | |
32d39a93 | 335 | : "r" (task_stack_page(current) + THREAD_SIZE - 8)); |
a054a811 RK |
336 | } |
337 | #endif /* CONFIG_HOTPLUG_CPU */ | |
338 | ||
05c74a6c RK |
339 | /* |
340 | * Called by both boot and secondaries to move global data into | |
341 | * per-processor storage. | |
342 | */ | |
8bd26e3a | 343 | static void smp_store_cpu_info(unsigned int cpuid) |
05c74a6c RK |
344 | { |
345 | struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid); | |
346 | ||
347 | cpu_info->loops_per_jiffy = loops_per_jiffy; | |
e8d432c9 | 348 | cpu_info->cpuid = read_cpuid_id(); |
c9018aab VG |
349 | |
350 | store_cpu_topology(cpuid); | |
05c74a6c RK |
351 | } |
352 | ||
e65f38ed RK |
353 | /* |
354 | * This is the secondary CPU boot entry. We're using this CPUs | |
355 | * idle thread stack, but a set of temporary page tables. | |
356 | */ | |
8bd26e3a | 357 | asmlinkage void secondary_start_kernel(void) |
e65f38ed RK |
358 | { |
359 | struct mm_struct *mm = &init_mm; | |
5f40b909 WD |
360 | unsigned int cpu; |
361 | ||
362 | /* | |
363 | * The identity mapping is uncached (strongly ordered), so | |
364 | * switch away from it before attempting any exclusive accesses. | |
365 | */ | |
366 | cpu_switch_mm(mm->pgd, mm); | |
89c7e4b8 | 367 | local_flush_bp_all(); |
5f40b909 WD |
368 | enter_lazy_tlb(mm, current); |
369 | local_flush_tlb_all(); | |
e65f38ed | 370 | |
e65f38ed RK |
371 | /* |
372 | * All kernel threads share the same mm context; grab a | |
373 | * reference and switch to it. | |
374 | */ | |
5f40b909 | 375 | cpu = smp_processor_id(); |
f1f10076 | 376 | mmgrab(mm); |
e65f38ed | 377 | current->active_mm = mm; |
56f8ba83 | 378 | cpumask_set_cpu(cpu, mm_cpumask(mm)); |
e65f38ed | 379 | |
14318efb RH |
380 | cpu_init(); |
381 | ||
c68b0274 | 382 | pr_debug("CPU%u: Booted secondary processor\n", cpu); |
fde165b2 | 383 | |
5bfb5d69 | 384 | preempt_disable(); |
2c0136db | 385 | trace_hardirqs_off(); |
e65f38ed RK |
386 | |
387 | /* | |
388 | * Give the platform a chance to do its own initialisation. | |
389 | */ | |
0a301110 RK |
390 | if (smp_ops.smp_secondary_init) |
391 | smp_ops.smp_secondary_init(cpu); | |
e65f38ed | 392 | |
e545a614 | 393 | notify_cpu_starting(cpu); |
a8655e83 | 394 | |
e65f38ed RK |
395 | calibrate_delay(); |
396 | ||
397 | smp_store_cpu_info(cpu); | |
398 | ||
399 | /* | |
573619d1 RK |
400 | * OK, now it's safe to let the boot CPU continue. Wait for |
401 | * the CPU migration code to notice that the CPU is online | |
149c2415 | 402 | * before we continue - which happens after __cpu_up returns. |
e65f38ed | 403 | */ |
e03cdade | 404 | set_cpu_online(cpu, true); |
149c2415 | 405 | complete(&cpu_running); |
eb047454 | 406 | |
eb047454 TG |
407 | local_irq_enable(); |
408 | local_fiq_enable(); | |
bbeb9209 | 409 | local_abt_enable(); |
eb047454 | 410 | |
e65f38ed RK |
411 | /* |
412 | * OK, it's off to the idle thread for us | |
413 | */ | |
fc6d73d6 | 414 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
e65f38ed RK |
415 | } |
416 | ||
1da177e4 LT |
417 | void __init smp_cpus_done(unsigned int max_cpus) |
418 | { | |
4bf9636c PM |
419 | int cpu; |
420 | unsigned long bogosum = 0; | |
421 | ||
422 | for_each_online_cpu(cpu) | |
423 | bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy; | |
424 | ||
425 | printk(KERN_INFO "SMP: Total of %d processors activated " | |
426 | "(%lu.%02lu BogoMIPS).\n", | |
427 | num_online_cpus(), | |
428 | bogosum / (500000/HZ), | |
429 | (bogosum / (5000/HZ)) % 100); | |
430 | ||
4588c34d | 431 | hyp_mode_check(); |
1da177e4 LT |
432 | } |
433 | ||
434 | void __init smp_prepare_boot_cpu(void) | |
435 | { | |
14318efb | 436 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
1da177e4 LT |
437 | } |
438 | ||
05c74a6c | 439 | void __init smp_prepare_cpus(unsigned int max_cpus) |
1da177e4 | 440 | { |
05c74a6c | 441 | unsigned int ncores = num_possible_cpus(); |
1da177e4 | 442 | |
c9018aab VG |
443 | init_cpu_topology(); |
444 | ||
05c74a6c | 445 | smp_store_cpu_info(smp_processor_id()); |
1da177e4 LT |
446 | |
447 | /* | |
05c74a6c | 448 | * are we trying to boot more cores than exist? |
1da177e4 | 449 | */ |
05c74a6c RK |
450 | if (max_cpus > ncores) |
451 | max_cpus = ncores; | |
7fa22bd5 | 452 | if (ncores > 1 && max_cpus) { |
7fa22bd5 SB |
453 | /* |
454 | * Initialise the present map, which describes the set of CPUs | |
455 | * actually populated at the present time. A platform should | |
0a301110 RK |
456 | * re-initialize the map in the platforms smp_prepare_cpus() |
457 | * if present != possible (e.g. physical hotplug). | |
7fa22bd5 | 458 | */ |
0b5f9c00 | 459 | init_cpu_present(cpu_possible_mask); |
7fa22bd5 | 460 | |
05c74a6c RK |
461 | /* |
462 | * Initialise the SCU if there are more than one CPU | |
463 | * and let them know where to start. | |
464 | */ | |
0a301110 RK |
465 | if (smp_ops.smp_prepare_cpus) |
466 | smp_ops.smp_prepare_cpus(max_cpus); | |
05c74a6c | 467 | } |
1da177e4 LT |
468 | } |
469 | ||
365ec7b1 | 470 | static void (*__smp_cross_call)(const struct cpumask *, unsigned int); |
0f7b332f RK |
471 | |
472 | void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) | |
473 | { | |
365ec7b1 NP |
474 | if (!__smp_cross_call) |
475 | __smp_cross_call = fn; | |
3e459990 | 476 | } |
3e459990 | 477 | |
365ec7b1 | 478 | static const char *ipi_types[NR_IPI] __tracepoint_string = { |
559a5939 SB |
479 | #define S(x,s) [x] = s |
480 | S(IPI_WAKEUP, "CPU wakeup interrupts"), | |
4a88abd7 RK |
481 | S(IPI_TIMER, "Timer broadcast interrupts"), |
482 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), | |
483 | S(IPI_CALL_FUNC, "Function call interrupts"), | |
4a88abd7 | 484 | S(IPI_CPU_STOP, "CPU stop interrupts"), |
bf18525f | 485 | S(IPI_IRQ_WORK, "IRQ work interrupts"), |
5135d875 | 486 | S(IPI_COMPLETION, "completion interrupts"), |
4a88abd7 RK |
487 | }; |
488 | ||
365ec7b1 NP |
489 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) |
490 | { | |
7c64cc05 | 491 | trace_ipi_raise_rcuidle(target, ipi_types[ipinr]); |
365ec7b1 NP |
492 | __smp_cross_call(target, ipinr); |
493 | } | |
494 | ||
f13cd417 | 495 | void show_ipi_list(struct seq_file *p, int prec) |
1da177e4 | 496 | { |
4a88abd7 | 497 | unsigned int cpu, i; |
1da177e4 | 498 | |
4a88abd7 RK |
499 | for (i = 0; i < NR_IPI; i++) { |
500 | seq_printf(p, "%*s%u: ", prec - 1, "IPI", i); | |
1da177e4 | 501 | |
026b7c6b | 502 | for_each_online_cpu(cpu) |
4a88abd7 RK |
503 | seq_printf(p, "%10u ", |
504 | __get_irq_stat(cpu, ipi_irqs[i])); | |
1da177e4 | 505 | |
4a88abd7 RK |
506 | seq_printf(p, " %s\n", ipi_types[i]); |
507 | } | |
1da177e4 LT |
508 | } |
509 | ||
b54992fe | 510 | u64 smp_irq_stat_cpu(unsigned int cpu) |
37ee16ae | 511 | { |
b54992fe RK |
512 | u64 sum = 0; |
513 | int i; | |
37ee16ae | 514 | |
b54992fe RK |
515 | for (i = 0; i < NR_IPI; i++) |
516 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | |
37ee16ae | 517 | |
b54992fe | 518 | return sum; |
37ee16ae RK |
519 | } |
520 | ||
365ec7b1 NP |
521 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
522 | { | |
523 | smp_cross_call(mask, IPI_CALL_FUNC); | |
524 | } | |
525 | ||
526 | void arch_send_wakeup_ipi_mask(const struct cpumask *mask) | |
527 | { | |
528 | smp_cross_call(mask, IPI_WAKEUP); | |
529 | } | |
530 | ||
531 | void arch_send_call_function_single_ipi(int cpu) | |
532 | { | |
89d798b7 | 533 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC); |
365ec7b1 NP |
534 | } |
535 | ||
536 | #ifdef CONFIG_IRQ_WORK | |
537 | void arch_irq_work_raise(void) | |
538 | { | |
09f6edd4 | 539 | if (arch_irq_work_has_interrupt()) |
365ec7b1 NP |
540 | smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); |
541 | } | |
542 | #endif | |
543 | ||
bc28248e | 544 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
3d06770e | 545 | void tick_broadcast(const struct cpumask *mask) |
bc28248e | 546 | { |
e3fbb087 | 547 | smp_cross_call(mask, IPI_TIMER); |
bc28248e | 548 | } |
5388a6b2 | 549 | #endif |
bc28248e | 550 | |
bd31b859 | 551 | static DEFINE_RAW_SPINLOCK(stop_lock); |
1da177e4 LT |
552 | |
553 | /* | |
554 | * ipi_cpu_stop - handle IPI from smp_send_stop() | |
555 | */ | |
556 | static void ipi_cpu_stop(unsigned int cpu) | |
557 | { | |
5976a669 | 558 | if (system_state <= SYSTEM_RUNNING) { |
bd31b859 | 559 | raw_spin_lock(&stop_lock); |
4ed89f22 | 560 | pr_crit("CPU%u: stopping\n", cpu); |
3d3f78d7 | 561 | dump_stack(); |
bd31b859 | 562 | raw_spin_unlock(&stop_lock); |
3d3f78d7 | 563 | } |
1da177e4 | 564 | |
e03cdade | 565 | set_cpu_online(cpu, false); |
1da177e4 LT |
566 | |
567 | local_fiq_disable(); | |
568 | local_irq_disable(); | |
569 | ||
570 | while (1) | |
571 | cpu_relax(); | |
572 | } | |
573 | ||
5135d875 NP |
574 | static DEFINE_PER_CPU(struct completion *, cpu_completion); |
575 | ||
576 | int register_ipi_completion(struct completion *completion, int cpu) | |
577 | { | |
578 | per_cpu(cpu_completion, cpu) = completion; | |
579 | return IPI_COMPLETION; | |
580 | } | |
581 | ||
582 | static void ipi_complete(unsigned int cpu) | |
583 | { | |
584 | complete(per_cpu(cpu_completion, cpu)); | |
585 | } | |
586 | ||
1da177e4 LT |
587 | /* |
588 | * Main handler for inter-processor interrupts | |
1da177e4 | 589 | */ |
4073723a | 590 | asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs) |
0b5a1b95 SG |
591 | { |
592 | handle_IPI(ipinr, regs); | |
593 | } | |
594 | ||
595 | void handle_IPI(int ipinr, struct pt_regs *regs) | |
1da177e4 LT |
596 | { |
597 | unsigned int cpu = smp_processor_id(); | |
c97d4869 | 598 | struct pt_regs *old_regs = set_irq_regs(regs); |
1da177e4 | 599 | |
365ec7b1 | 600 | if ((unsigned)ipinr < NR_IPI) { |
398f7456 | 601 | trace_ipi_entry_rcuidle(ipi_types[ipinr]); |
559a5939 | 602 | __inc_irq_stat(cpu, ipi_irqs[ipinr]); |
365ec7b1 | 603 | } |
1da177e4 | 604 | |
24480d98 | 605 | switch (ipinr) { |
559a5939 SB |
606 | case IPI_WAKEUP: |
607 | break; | |
608 | ||
e2c50119 | 609 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
24480d98 | 610 | case IPI_TIMER: |
7deabca0 | 611 | irq_enter(); |
e2c50119 | 612 | tick_receive_broadcast(); |
7deabca0 | 613 | irq_exit(); |
24480d98 | 614 | break; |
e2c50119 | 615 | #endif |
1da177e4 | 616 | |
24480d98 | 617 | case IPI_RESCHEDULE: |
184748cc | 618 | scheduler_ipi(); |
24480d98 | 619 | break; |
1da177e4 | 620 | |
24480d98 | 621 | case IPI_CALL_FUNC: |
7deabca0 | 622 | irq_enter(); |
24480d98 | 623 | generic_smp_call_function_interrupt(); |
7deabca0 | 624 | irq_exit(); |
24480d98 | 625 | break; |
1da177e4 | 626 | |
24480d98 | 627 | case IPI_CPU_STOP: |
7deabca0 | 628 | irq_enter(); |
24480d98 | 629 | ipi_cpu_stop(cpu); |
7deabca0 | 630 | irq_exit(); |
24480d98 | 631 | break; |
1da177e4 | 632 | |
bf18525f SB |
633 | #ifdef CONFIG_IRQ_WORK |
634 | case IPI_IRQ_WORK: | |
635 | irq_enter(); | |
636 | irq_work_run(); | |
637 | irq_exit(); | |
638 | break; | |
639 | #endif | |
640 | ||
5135d875 NP |
641 | case IPI_COMPLETION: |
642 | irq_enter(); | |
643 | ipi_complete(cpu); | |
644 | irq_exit(); | |
645 | break; | |
646 | ||
96f0e003 | 647 | case IPI_CPU_BACKTRACE: |
42a0bb3f | 648 | printk_nmi_enter(); |
96f0e003 RK |
649 | irq_enter(); |
650 | nmi_cpu_backtrace(regs); | |
651 | irq_exit(); | |
42a0bb3f | 652 | printk_nmi_exit(); |
96f0e003 RK |
653 | break; |
654 | ||
24480d98 | 655 | default: |
4ed89f22 RK |
656 | pr_crit("CPU%u: Unknown IPI message 0x%x\n", |
657 | cpu, ipinr); | |
24480d98 | 658 | break; |
1da177e4 | 659 | } |
365ec7b1 NP |
660 | |
661 | if ((unsigned)ipinr < NR_IPI) | |
398f7456 | 662 | trace_ipi_exit_rcuidle(ipi_types[ipinr]); |
c97d4869 | 663 | set_irq_regs(old_regs); |
1da177e4 LT |
664 | } |
665 | ||
666 | void smp_send_reschedule(int cpu) | |
667 | { | |
e3fbb087 | 668 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); |
1da177e4 LT |
669 | } |
670 | ||
1da177e4 LT |
671 | void smp_send_stop(void) |
672 | { | |
28e18293 | 673 | unsigned long timeout; |
6fa99b7f | 674 | struct cpumask mask; |
1da177e4 | 675 | |
6fa99b7f WD |
676 | cpumask_copy(&mask, cpu_online_mask); |
677 | cpumask_clear_cpu(smp_processor_id(), &mask); | |
c5dff4ff JMC |
678 | if (!cpumask_empty(&mask)) |
679 | smp_cross_call(&mask, IPI_CPU_STOP); | |
4b0ef3b1 | 680 | |
28e18293 RK |
681 | /* Wait up to one second for other CPUs to stop */ |
682 | timeout = USEC_PER_SEC; | |
683 | while (num_online_cpus() > 1 && timeout--) | |
684 | udelay(1); | |
4b0ef3b1 | 685 | |
28e18293 | 686 | if (num_online_cpus() > 1) |
8b521cb2 | 687 | pr_warn("SMP: failed to stop secondary CPUs\n"); |
4b0ef3b1 RK |
688 | } |
689 | ||
4b0ef3b1 | 690 | /* |
1da177e4 | 691 | * not supported here |
4b0ef3b1 | 692 | */ |
5048bcba | 693 | int setup_profiling_timer(unsigned int multiplier) |
4b0ef3b1 | 694 | { |
1da177e4 | 695 | return -EINVAL; |
4b0ef3b1 | 696 | } |
ec971ea5 RZ |
697 | |
698 | #ifdef CONFIG_CPU_FREQ | |
699 | ||
700 | static DEFINE_PER_CPU(unsigned long, l_p_j_ref); | |
701 | static DEFINE_PER_CPU(unsigned long, l_p_j_ref_freq); | |
702 | static unsigned long global_l_p_j_ref; | |
703 | static unsigned long global_l_p_j_ref_freq; | |
704 | ||
705 | static int cpufreq_callback(struct notifier_block *nb, | |
706 | unsigned long val, void *data) | |
707 | { | |
708 | struct cpufreq_freqs *freq = data; | |
709 | int cpu = freq->cpu; | |
710 | ||
711 | if (freq->flags & CPUFREQ_CONST_LOOPS) | |
712 | return NOTIFY_OK; | |
713 | ||
714 | if (!per_cpu(l_p_j_ref, cpu)) { | |
715 | per_cpu(l_p_j_ref, cpu) = | |
716 | per_cpu(cpu_data, cpu).loops_per_jiffy; | |
717 | per_cpu(l_p_j_ref_freq, cpu) = freq->old; | |
718 | if (!global_l_p_j_ref) { | |
719 | global_l_p_j_ref = loops_per_jiffy; | |
720 | global_l_p_j_ref_freq = freq->old; | |
721 | } | |
722 | } | |
723 | ||
724 | if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || | |
0b443ead | 725 | (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { |
ec971ea5 RZ |
726 | loops_per_jiffy = cpufreq_scale(global_l_p_j_ref, |
727 | global_l_p_j_ref_freq, | |
728 | freq->new); | |
729 | per_cpu(cpu_data, cpu).loops_per_jiffy = | |
730 | cpufreq_scale(per_cpu(l_p_j_ref, cpu), | |
731 | per_cpu(l_p_j_ref_freq, cpu), | |
732 | freq->new); | |
733 | } | |
734 | return NOTIFY_OK; | |
735 | } | |
736 | ||
737 | static struct notifier_block cpufreq_notifier = { | |
738 | .notifier_call = cpufreq_callback, | |
739 | }; | |
740 | ||
741 | static int __init register_cpufreq_notifier(void) | |
742 | { | |
743 | return cpufreq_register_notifier(&cpufreq_notifier, | |
744 | CPUFREQ_TRANSITION_NOTIFIER); | |
745 | } | |
746 | core_initcall(register_cpufreq_notifier); | |
747 | ||
748 | #endif | |
96f0e003 RK |
749 | |
750 | static void raise_nmi(cpumask_t *mask) | |
751 | { | |
752 | smp_cross_call(mask, IPI_CPU_BACKTRACE); | |
753 | } | |
754 | ||
9a01c3ed | 755 | void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) |
96f0e003 | 756 | { |
9a01c3ed | 757 | nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_nmi); |
96f0e003 | 758 | } |