]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/smp.c | |
3 | * | |
4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
c97d4869 | 10 | #include <linux/module.h> |
1da177e4 LT |
11 | #include <linux/delay.h> |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/cache.h> | |
17 | #include <linux/profile.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/mm.h> | |
4e950f6f | 20 | #include <linux/err.h> |
1da177e4 | 21 | #include <linux/cpu.h> |
1da177e4 | 22 | #include <linux/seq_file.h> |
c97d4869 | 23 | #include <linux/irq.h> |
bc28248e RK |
24 | #include <linux/percpu.h> |
25 | #include <linux/clockchips.h> | |
3c030bea | 26 | #include <linux/completion.h> |
ec971ea5 | 27 | #include <linux/cpufreq.h> |
1da177e4 | 28 | |
60063497 | 29 | #include <linux/atomic.h> |
abcee5fb | 30 | #include <asm/smp.h> |
1da177e4 LT |
31 | #include <asm/cacheflush.h> |
32 | #include <asm/cpu.h> | |
42578c82 | 33 | #include <asm/cputype.h> |
5a567d78 | 34 | #include <asm/exception.h> |
8903826d | 35 | #include <asm/idmap.h> |
c9018aab | 36 | #include <asm/topology.h> |
e65f38ed RK |
37 | #include <asm/mmu_context.h> |
38 | #include <asm/pgtable.h> | |
39 | #include <asm/pgalloc.h> | |
1da177e4 | 40 | #include <asm/processor.h> |
37b05b63 | 41 | #include <asm/sections.h> |
1da177e4 LT |
42 | #include <asm/tlbflush.h> |
43 | #include <asm/ptrace.h> | |
bc28248e | 44 | #include <asm/localtimer.h> |
d6257288 | 45 | #include <asm/smp_plat.h> |
4588c34d | 46 | #include <asm/virt.h> |
abcee5fb | 47 | #include <asm/mach/arch.h> |
1da177e4 | 48 | |
e65f38ed RK |
49 | /* |
50 | * as from 2.5, kernels no longer have an init_tasks structure | |
51 | * so we need some other way of telling a new secondary core | |
52 | * where to place its SVC stack | |
53 | */ | |
54 | struct secondary_data secondary_data; | |
55 | ||
28e8e29c MZ |
56 | /* |
57 | * control for which core is the next to come out of the secondary | |
58 | * boot "holding pen" | |
59 | */ | |
60 | volatile int __cpuinitdata pen_release = -1; | |
61 | ||
1da177e4 | 62 | enum ipi_msg_type { |
559a5939 SB |
63 | IPI_WAKEUP, |
64 | IPI_TIMER, | |
1da177e4 LT |
65 | IPI_RESCHEDULE, |
66 | IPI_CALL_FUNC, | |
f6dd9fa5 | 67 | IPI_CALL_FUNC_SINGLE, |
1da177e4 LT |
68 | IPI_CPU_STOP, |
69 | }; | |
70 | ||
149c2415 RK |
71 | static DECLARE_COMPLETION(cpu_running); |
72 | ||
abcee5fb MZ |
73 | static struct smp_operations smp_ops; |
74 | ||
75 | void __init smp_set_ops(struct smp_operations *ops) | |
76 | { | |
77 | if (ops) | |
78 | smp_ops = *ops; | |
79 | }; | |
80 | ||
84ec6d57 | 81 | int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle) |
1da177e4 | 82 | { |
1da177e4 LT |
83 | int ret; |
84 | ||
e65f38ed RK |
85 | /* |
86 | * We need to tell the secondary core where to find | |
87 | * its stack and the page tables. | |
88 | */ | |
32d39a93 | 89 | secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; |
4e8ee7de | 90 | secondary_data.pgdir = virt_to_phys(idmap_pgd); |
d427958a | 91 | secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir); |
1027247f RK |
92 | __cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data)); |
93 | outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1)); | |
e65f38ed | 94 | |
1da177e4 LT |
95 | /* |
96 | * Now bring the CPU into our world. | |
97 | */ | |
98 | ret = boot_secondary(cpu, idle); | |
e65f38ed | 99 | if (ret == 0) { |
e65f38ed RK |
100 | /* |
101 | * CPU was successfully started, wait for it | |
102 | * to come online or time out. | |
103 | */ | |
149c2415 RK |
104 | wait_for_completion_timeout(&cpu_running, |
105 | msecs_to_jiffies(1000)); | |
e65f38ed | 106 | |
58613cd1 RK |
107 | if (!cpu_online(cpu)) { |
108 | pr_crit("CPU%u: failed to come online\n", cpu); | |
e65f38ed | 109 | ret = -EIO; |
58613cd1 RK |
110 | } |
111 | } else { | |
112 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
e65f38ed RK |
113 | } |
114 | ||
5d43045b | 115 | secondary_data.stack = NULL; |
e65f38ed RK |
116 | secondary_data.pgdir = 0; |
117 | ||
1da177e4 LT |
118 | return ret; |
119 | } | |
120 | ||
abcee5fb | 121 | /* platform specific SMP operations */ |
ac6c7998 | 122 | void __init smp_init_cpus(void) |
abcee5fb MZ |
123 | { |
124 | if (smp_ops.smp_init_cpus) | |
125 | smp_ops.smp_init_cpus(); | |
126 | } | |
127 | ||
ac6c7998 | 128 | static void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
abcee5fb MZ |
129 | { |
130 | if (smp_ops.smp_prepare_cpus) | |
131 | smp_ops.smp_prepare_cpus(max_cpus); | |
132 | } | |
133 | ||
ac6c7998 | 134 | static void __cpuinit platform_secondary_init(unsigned int cpu) |
abcee5fb MZ |
135 | { |
136 | if (smp_ops.smp_secondary_init) | |
137 | smp_ops.smp_secondary_init(cpu); | |
138 | } | |
139 | ||
ac6c7998 | 140 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
abcee5fb MZ |
141 | { |
142 | if (smp_ops.smp_boot_secondary) | |
143 | return smp_ops.smp_boot_secondary(cpu, idle); | |
144 | return -ENOSYS; | |
145 | } | |
146 | ||
a054a811 | 147 | #ifdef CONFIG_HOTPLUG_CPU |
10034aab RK |
148 | static void percpu_timer_stop(void); |
149 | ||
ac6c7998 | 150 | static int platform_cpu_kill(unsigned int cpu) |
abcee5fb MZ |
151 | { |
152 | if (smp_ops.cpu_kill) | |
153 | return smp_ops.cpu_kill(cpu); | |
154 | return 1; | |
155 | } | |
156 | ||
ac6c7998 | 157 | static void platform_cpu_die(unsigned int cpu) |
abcee5fb MZ |
158 | { |
159 | if (smp_ops.cpu_die) | |
160 | smp_ops.cpu_die(cpu); | |
161 | } | |
162 | ||
ac6c7998 | 163 | static int platform_cpu_disable(unsigned int cpu) |
abcee5fb MZ |
164 | { |
165 | if (smp_ops.cpu_disable) | |
166 | return smp_ops.cpu_disable(cpu); | |
167 | ||
168 | /* | |
169 | * By default, allow disabling all CPUs except the first one, | |
170 | * since this is special on a lot of platforms, e.g. because | |
171 | * of clock tick interrupts. | |
172 | */ | |
173 | return cpu == 0 ? -EPERM : 0; | |
174 | } | |
a054a811 RK |
175 | /* |
176 | * __cpu_disable runs on the processor to be shutdown. | |
177 | */ | |
ac6c7998 | 178 | int __cpuinit __cpu_disable(void) |
a054a811 RK |
179 | { |
180 | unsigned int cpu = smp_processor_id(); | |
a054a811 RK |
181 | int ret; |
182 | ||
8e2a43f5 | 183 | ret = platform_cpu_disable(cpu); |
a054a811 RK |
184 | if (ret) |
185 | return ret; | |
186 | ||
187 | /* | |
188 | * Take this CPU offline. Once we clear this, we can't return, | |
189 | * and we must not schedule until we're ready to give up the cpu. | |
190 | */ | |
e03cdade | 191 | set_cpu_online(cpu, false); |
a054a811 RK |
192 | |
193 | /* | |
194 | * OK - migrate IRQs away from this CPU | |
195 | */ | |
196 | migrate_irqs(); | |
197 | ||
37ee16ae RK |
198 | /* |
199 | * Stop the local timer for this CPU. | |
200 | */ | |
10034aab | 201 | percpu_timer_stop(); |
37ee16ae | 202 | |
a054a811 RK |
203 | /* |
204 | * Flush user cache and TLB mappings, and then remove this CPU | |
205 | * from the vm mask set of all processes. | |
e6b866e9 LP |
206 | * |
207 | * Caches are flushed to the Level of Unification Inner Shareable | |
208 | * to write-back dirty lines to unified caches shared by all CPUs. | |
a054a811 | 209 | */ |
e6b866e9 | 210 | flush_cache_louis(); |
a054a811 RK |
211 | local_flush_tlb_all(); |
212 | ||
3eaa73bd | 213 | clear_tasks_mm_cpumask(cpu); |
a054a811 RK |
214 | |
215 | return 0; | |
216 | } | |
217 | ||
3c030bea RK |
218 | static DECLARE_COMPLETION(cpu_died); |
219 | ||
a054a811 RK |
220 | /* |
221 | * called on the thread which is asking for a CPU to be shutdown - | |
222 | * waits until shutdown has completed, or it is timed out. | |
223 | */ | |
ac6c7998 | 224 | void __cpuinit __cpu_die(unsigned int cpu) |
a054a811 | 225 | { |
3c030bea RK |
226 | if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) { |
227 | pr_err("CPU%u: cpu didn't die\n", cpu); | |
228 | return; | |
229 | } | |
230 | printk(KERN_NOTICE "CPU%u: shutdown\n", cpu); | |
231 | ||
a054a811 RK |
232 | if (!platform_cpu_kill(cpu)) |
233 | printk("CPU%u: unable to kill\n", cpu); | |
234 | } | |
235 | ||
236 | /* | |
237 | * Called from the idle thread for the CPU which has been shutdown. | |
238 | * | |
239 | * Note that we disable IRQs here, but do not re-enable them | |
240 | * before returning to the caller. This is also the behaviour | |
241 | * of the other hotplug-cpu capable cores, so presumably coming | |
242 | * out of idle fixes this. | |
243 | */ | |
90140c30 | 244 | void __ref cpu_die(void) |
a054a811 RK |
245 | { |
246 | unsigned int cpu = smp_processor_id(); | |
247 | ||
a054a811 RK |
248 | idle_task_exit(); |
249 | ||
f36d3401 RK |
250 | local_irq_disable(); |
251 | mb(); | |
252 | ||
3c030bea | 253 | /* Tell __cpu_die() that this CPU is now safe to dispose of */ |
ff081e05 | 254 | RCU_NONIDLE(complete(&cpu_died)); |
3c030bea | 255 | |
a054a811 RK |
256 | /* |
257 | * actual CPU shutdown procedure is at least platform (if not | |
3c030bea | 258 | * CPU) specific. |
a054a811 RK |
259 | */ |
260 | platform_cpu_die(cpu); | |
261 | ||
262 | /* | |
263 | * Do not return to the idle loop - jump back to the secondary | |
264 | * cpu initialisation. There's some initialisation which needs | |
265 | * to be repeated to undo the effects of taking the CPU offline. | |
266 | */ | |
267 | __asm__("mov sp, %0\n" | |
faabfa08 | 268 | " mov fp, #0\n" |
a054a811 RK |
269 | " b secondary_start_kernel" |
270 | : | |
32d39a93 | 271 | : "r" (task_stack_page(current) + THREAD_SIZE - 8)); |
a054a811 RK |
272 | } |
273 | #endif /* CONFIG_HOTPLUG_CPU */ | |
274 | ||
05c74a6c RK |
275 | /* |
276 | * Called by both boot and secondaries to move global data into | |
277 | * per-processor storage. | |
278 | */ | |
279 | static void __cpuinit smp_store_cpu_info(unsigned int cpuid) | |
280 | { | |
281 | struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid); | |
282 | ||
283 | cpu_info->loops_per_jiffy = loops_per_jiffy; | |
c9018aab VG |
284 | |
285 | store_cpu_topology(cpuid); | |
05c74a6c RK |
286 | } |
287 | ||
d4578592 MZ |
288 | static void percpu_timer_setup(void); |
289 | ||
e65f38ed RK |
290 | /* |
291 | * This is the secondary CPU boot entry. We're using this CPUs | |
292 | * idle thread stack, but a set of temporary page tables. | |
293 | */ | |
bd6f68af | 294 | asmlinkage void __cpuinit secondary_start_kernel(void) |
e65f38ed RK |
295 | { |
296 | struct mm_struct *mm = &init_mm; | |
5f40b909 WD |
297 | unsigned int cpu; |
298 | ||
299 | /* | |
300 | * The identity mapping is uncached (strongly ordered), so | |
301 | * switch away from it before attempting any exclusive accesses. | |
302 | */ | |
303 | cpu_switch_mm(mm->pgd, mm); | |
304 | enter_lazy_tlb(mm, current); | |
305 | local_flush_tlb_all(); | |
e65f38ed | 306 | |
e65f38ed RK |
307 | /* |
308 | * All kernel threads share the same mm context; grab a | |
309 | * reference and switch to it. | |
310 | */ | |
5f40b909 | 311 | cpu = smp_processor_id(); |
e65f38ed RK |
312 | atomic_inc(&mm->mm_count); |
313 | current->active_mm = mm; | |
56f8ba83 | 314 | cpumask_set_cpu(cpu, mm_cpumask(mm)); |
e65f38ed | 315 | |
fde165b2 CC |
316 | printk("CPU%u: Booted secondary processor\n", cpu); |
317 | ||
e65f38ed | 318 | cpu_init(); |
5bfb5d69 | 319 | preempt_disable(); |
2c0136db | 320 | trace_hardirqs_off(); |
e65f38ed RK |
321 | |
322 | /* | |
323 | * Give the platform a chance to do its own initialisation. | |
324 | */ | |
325 | platform_secondary_init(cpu); | |
326 | ||
e545a614 | 327 | notify_cpu_starting(cpu); |
a8655e83 | 328 | |
e65f38ed RK |
329 | calibrate_delay(); |
330 | ||
331 | smp_store_cpu_info(cpu); | |
332 | ||
333 | /* | |
573619d1 RK |
334 | * OK, now it's safe to let the boot CPU continue. Wait for |
335 | * the CPU migration code to notice that the CPU is online | |
149c2415 | 336 | * before we continue - which happens after __cpu_up returns. |
e65f38ed | 337 | */ |
e03cdade | 338 | set_cpu_online(cpu, true); |
149c2415 | 339 | complete(&cpu_running); |
eb047454 TG |
340 | |
341 | /* | |
342 | * Setup the percpu timer for this CPU. | |
343 | */ | |
344 | percpu_timer_setup(); | |
345 | ||
eb047454 TG |
346 | local_irq_enable(); |
347 | local_fiq_enable(); | |
348 | ||
e65f38ed RK |
349 | /* |
350 | * OK, it's off to the idle thread for us | |
351 | */ | |
352 | cpu_idle(); | |
353 | } | |
354 | ||
1da177e4 LT |
355 | void __init smp_cpus_done(unsigned int max_cpus) |
356 | { | |
357 | int cpu; | |
358 | unsigned long bogosum = 0; | |
359 | ||
360 | for_each_online_cpu(cpu) | |
361 | bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy; | |
362 | ||
363 | printk(KERN_INFO "SMP: Total of %d processors activated " | |
364 | "(%lu.%02lu BogoMIPS).\n", | |
365 | num_online_cpus(), | |
366 | bogosum / (500000/HZ), | |
367 | (bogosum / (5000/HZ)) % 100); | |
4588c34d DM |
368 | |
369 | hyp_mode_check(); | |
1da177e4 LT |
370 | } |
371 | ||
372 | void __init smp_prepare_boot_cpu(void) | |
373 | { | |
1da177e4 LT |
374 | } |
375 | ||
05c74a6c | 376 | void __init smp_prepare_cpus(unsigned int max_cpus) |
1da177e4 | 377 | { |
05c74a6c | 378 | unsigned int ncores = num_possible_cpus(); |
1da177e4 | 379 | |
c9018aab VG |
380 | init_cpu_topology(); |
381 | ||
05c74a6c | 382 | smp_store_cpu_info(smp_processor_id()); |
1da177e4 LT |
383 | |
384 | /* | |
05c74a6c | 385 | * are we trying to boot more cores than exist? |
1da177e4 | 386 | */ |
05c74a6c RK |
387 | if (max_cpus > ncores) |
388 | max_cpus = ncores; | |
7fa22bd5 | 389 | if (ncores > 1 && max_cpus) { |
05c74a6c RK |
390 | /* |
391 | * Enable the local timer or broadcast device for the | |
392 | * boot CPU, but only if we have more than one CPU. | |
393 | */ | |
394 | percpu_timer_setup(); | |
1da177e4 | 395 | |
7fa22bd5 SB |
396 | /* |
397 | * Initialise the present map, which describes the set of CPUs | |
398 | * actually populated at the present time. A platform should | |
399 | * re-initialize the map in platform_smp_prepare_cpus() if | |
400 | * present != possible (e.g. physical hotplug). | |
401 | */ | |
0b5f9c00 | 402 | init_cpu_present(cpu_possible_mask); |
7fa22bd5 | 403 | |
05c74a6c RK |
404 | /* |
405 | * Initialise the SCU if there are more than one CPU | |
406 | * and let them know where to start. | |
407 | */ | |
408 | platform_smp_prepare_cpus(max_cpus); | |
409 | } | |
1da177e4 LT |
410 | } |
411 | ||
0f7b332f RK |
412 | static void (*smp_cross_call)(const struct cpumask *, unsigned int); |
413 | ||
414 | void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) | |
415 | { | |
416 | smp_cross_call = fn; | |
417 | } | |
418 | ||
82668104 | 419 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
1da177e4 | 420 | { |
e3fbb087 | 421 | smp_cross_call(mask, IPI_CALL_FUNC); |
1da177e4 LT |
422 | } |
423 | ||
f6dd9fa5 | 424 | void arch_send_call_function_single_ipi(int cpu) |
3e459990 | 425 | { |
e3fbb087 | 426 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE); |
3e459990 | 427 | } |
3e459990 | 428 | |
4a88abd7 | 429 | static const char *ipi_types[NR_IPI] = { |
559a5939 SB |
430 | #define S(x,s) [x] = s |
431 | S(IPI_WAKEUP, "CPU wakeup interrupts"), | |
4a88abd7 RK |
432 | S(IPI_TIMER, "Timer broadcast interrupts"), |
433 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), | |
434 | S(IPI_CALL_FUNC, "Function call interrupts"), | |
435 | S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"), | |
436 | S(IPI_CPU_STOP, "CPU stop interrupts"), | |
437 | }; | |
438 | ||
f13cd417 | 439 | void show_ipi_list(struct seq_file *p, int prec) |
1da177e4 | 440 | { |
4a88abd7 | 441 | unsigned int cpu, i; |
1da177e4 | 442 | |
4a88abd7 RK |
443 | for (i = 0; i < NR_IPI; i++) { |
444 | seq_printf(p, "%*s%u: ", prec - 1, "IPI", i); | |
1da177e4 | 445 | |
4a88abd7 RK |
446 | for_each_present_cpu(cpu) |
447 | seq_printf(p, "%10u ", | |
448 | __get_irq_stat(cpu, ipi_irqs[i])); | |
1da177e4 | 449 | |
4a88abd7 RK |
450 | seq_printf(p, " %s\n", ipi_types[i]); |
451 | } | |
1da177e4 LT |
452 | } |
453 | ||
b54992fe | 454 | u64 smp_irq_stat_cpu(unsigned int cpu) |
37ee16ae | 455 | { |
b54992fe RK |
456 | u64 sum = 0; |
457 | int i; | |
37ee16ae | 458 | |
b54992fe RK |
459 | for (i = 0; i < NR_IPI; i++) |
460 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | |
37ee16ae | 461 | |
b54992fe | 462 | return sum; |
37ee16ae RK |
463 | } |
464 | ||
bc28248e RK |
465 | /* |
466 | * Timer (local or broadcast) support | |
467 | */ | |
468 | static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent); | |
469 | ||
c97d4869 | 470 | static void ipi_timer(void) |
1da177e4 | 471 | { |
bc28248e | 472 | struct clock_event_device *evt = &__get_cpu_var(percpu_clockevent); |
bc28248e | 473 | evt->event_handler(evt); |
1da177e4 LT |
474 | } |
475 | ||
bc28248e RK |
476 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
477 | static void smp_timer_broadcast(const struct cpumask *mask) | |
478 | { | |
e3fbb087 | 479 | smp_cross_call(mask, IPI_TIMER); |
bc28248e | 480 | } |
5388a6b2 RK |
481 | #else |
482 | #define smp_timer_broadcast NULL | |
483 | #endif | |
bc28248e RK |
484 | |
485 | static void broadcast_timer_set_mode(enum clock_event_mode mode, | |
486 | struct clock_event_device *evt) | |
487 | { | |
488 | } | |
489 | ||
a8d2518c | 490 | static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt) |
bc28248e RK |
491 | { |
492 | evt->name = "dummy_timer"; | |
493 | evt->features = CLOCK_EVT_FEAT_ONESHOT | | |
494 | CLOCK_EVT_FEAT_PERIODIC | | |
495 | CLOCK_EVT_FEAT_DUMMY; | |
496 | evt->rating = 400; | |
497 | evt->mult = 1; | |
498 | evt->set_mode = broadcast_timer_set_mode; | |
bc28248e RK |
499 | |
500 | clockevents_register_device(evt); | |
501 | } | |
bc28248e | 502 | |
0ef330e1 MZ |
503 | static struct local_timer_ops *lt_ops; |
504 | ||
505 | #ifdef CONFIG_LOCAL_TIMERS | |
506 | int local_timer_register(struct local_timer_ops *ops) | |
507 | { | |
bfa05f4f MZ |
508 | if (!is_smp() || !setup_max_cpus) |
509 | return -ENXIO; | |
510 | ||
0ef330e1 MZ |
511 | if (lt_ops) |
512 | return -EBUSY; | |
513 | ||
514 | lt_ops = ops; | |
515 | return 0; | |
516 | } | |
517 | #endif | |
518 | ||
d4578592 | 519 | static void __cpuinit percpu_timer_setup(void) |
bc28248e RK |
520 | { |
521 | unsigned int cpu = smp_processor_id(); | |
522 | struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu); | |
523 | ||
524 | evt->cpumask = cpumask_of(cpu); | |
5388a6b2 | 525 | evt->broadcast = smp_timer_broadcast; |
bc28248e | 526 | |
d4578592 | 527 | if (!lt_ops || lt_ops->setup(evt)) |
af90f10d | 528 | broadcast_timer_setup(evt); |
bc28248e RK |
529 | } |
530 | ||
10034aab RK |
531 | #ifdef CONFIG_HOTPLUG_CPU |
532 | /* | |
533 | * The generic clock events code purposely does not stop the local timer | |
534 | * on CPU_DEAD/CPU_DEAD_FROZEN hotplug events, so we have to do it | |
535 | * manually here. | |
536 | */ | |
537 | static void percpu_timer_stop(void) | |
538 | { | |
539 | unsigned int cpu = smp_processor_id(); | |
540 | struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu); | |
541 | ||
d4578592 MZ |
542 | if (lt_ops) |
543 | lt_ops->stop(evt); | |
10034aab RK |
544 | } |
545 | #endif | |
546 | ||
bd31b859 | 547 | static DEFINE_RAW_SPINLOCK(stop_lock); |
1da177e4 LT |
548 | |
549 | /* | |
550 | * ipi_cpu_stop - handle IPI from smp_send_stop() | |
551 | */ | |
552 | static void ipi_cpu_stop(unsigned int cpu) | |
553 | { | |
3d3f78d7 RK |
554 | if (system_state == SYSTEM_BOOTING || |
555 | system_state == SYSTEM_RUNNING) { | |
bd31b859 | 556 | raw_spin_lock(&stop_lock); |
3d3f78d7 RK |
557 | printk(KERN_CRIT "CPU%u: stopping\n", cpu); |
558 | dump_stack(); | |
bd31b859 | 559 | raw_spin_unlock(&stop_lock); |
3d3f78d7 | 560 | } |
1da177e4 | 561 | |
e03cdade | 562 | set_cpu_online(cpu, false); |
1da177e4 LT |
563 | |
564 | local_fiq_disable(); | |
565 | local_irq_disable(); | |
566 | ||
567 | while (1) | |
568 | cpu_relax(); | |
569 | } | |
570 | ||
571 | /* | |
572 | * Main handler for inter-processor interrupts | |
1da177e4 | 573 | */ |
4073723a | 574 | asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs) |
0b5a1b95 SG |
575 | { |
576 | handle_IPI(ipinr, regs); | |
577 | } | |
578 | ||
579 | void handle_IPI(int ipinr, struct pt_regs *regs) | |
1da177e4 LT |
580 | { |
581 | unsigned int cpu = smp_processor_id(); | |
c97d4869 | 582 | struct pt_regs *old_regs = set_irq_regs(regs); |
1da177e4 | 583 | |
559a5939 SB |
584 | if (ipinr < NR_IPI) |
585 | __inc_irq_stat(cpu, ipi_irqs[ipinr]); | |
1da177e4 | 586 | |
24480d98 | 587 | switch (ipinr) { |
559a5939 SB |
588 | case IPI_WAKEUP: |
589 | break; | |
590 | ||
24480d98 | 591 | case IPI_TIMER: |
7deabca0 | 592 | irq_enter(); |
24480d98 | 593 | ipi_timer(); |
7deabca0 | 594 | irq_exit(); |
24480d98 | 595 | break; |
1da177e4 | 596 | |
24480d98 | 597 | case IPI_RESCHEDULE: |
184748cc | 598 | scheduler_ipi(); |
24480d98 | 599 | break; |
1da177e4 | 600 | |
24480d98 | 601 | case IPI_CALL_FUNC: |
7deabca0 | 602 | irq_enter(); |
24480d98 | 603 | generic_smp_call_function_interrupt(); |
7deabca0 | 604 | irq_exit(); |
24480d98 | 605 | break; |
f6dd9fa5 | 606 | |
24480d98 | 607 | case IPI_CALL_FUNC_SINGLE: |
7deabca0 | 608 | irq_enter(); |
24480d98 | 609 | generic_smp_call_function_single_interrupt(); |
7deabca0 | 610 | irq_exit(); |
24480d98 | 611 | break; |
1da177e4 | 612 | |
24480d98 | 613 | case IPI_CPU_STOP: |
7deabca0 | 614 | irq_enter(); |
24480d98 | 615 | ipi_cpu_stop(cpu); |
7deabca0 | 616 | irq_exit(); |
24480d98 | 617 | break; |
1da177e4 | 618 | |
24480d98 RK |
619 | default: |
620 | printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%x\n", | |
621 | cpu, ipinr); | |
622 | break; | |
1da177e4 | 623 | } |
c97d4869 | 624 | set_irq_regs(old_regs); |
1da177e4 LT |
625 | } |
626 | ||
627 | void smp_send_reschedule(int cpu) | |
628 | { | |
e3fbb087 | 629 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); |
1da177e4 LT |
630 | } |
631 | ||
6fa99b7f WD |
632 | #ifdef CONFIG_HOTPLUG_CPU |
633 | static void smp_kill_cpus(cpumask_t *mask) | |
634 | { | |
635 | unsigned int cpu; | |
636 | for_each_cpu(cpu, mask) | |
637 | platform_cpu_kill(cpu); | |
638 | } | |
639 | #else | |
640 | static void smp_kill_cpus(cpumask_t *mask) { } | |
641 | #endif | |
642 | ||
1da177e4 LT |
643 | void smp_send_stop(void) |
644 | { | |
28e18293 | 645 | unsigned long timeout; |
6fa99b7f | 646 | struct cpumask mask; |
1da177e4 | 647 | |
6fa99b7f WD |
648 | cpumask_copy(&mask, cpu_online_mask); |
649 | cpumask_clear_cpu(smp_processor_id(), &mask); | |
c5dff4ff JMC |
650 | if (!cpumask_empty(&mask)) |
651 | smp_cross_call(&mask, IPI_CPU_STOP); | |
4b0ef3b1 | 652 | |
28e18293 RK |
653 | /* Wait up to one second for other CPUs to stop */ |
654 | timeout = USEC_PER_SEC; | |
655 | while (num_online_cpus() > 1 && timeout--) | |
656 | udelay(1); | |
4b0ef3b1 | 657 | |
28e18293 RK |
658 | if (num_online_cpus() > 1) |
659 | pr_warning("SMP: failed to stop secondary CPUs\n"); | |
6fa99b7f WD |
660 | |
661 | smp_kill_cpus(&mask); | |
4b0ef3b1 RK |
662 | } |
663 | ||
4b0ef3b1 | 664 | /* |
1da177e4 | 665 | * not supported here |
4b0ef3b1 | 666 | */ |
5048bcba | 667 | int setup_profiling_timer(unsigned int multiplier) |
4b0ef3b1 | 668 | { |
1da177e4 | 669 | return -EINVAL; |
4b0ef3b1 | 670 | } |
ec971ea5 RZ |
671 | |
672 | #ifdef CONFIG_CPU_FREQ | |
673 | ||
674 | static DEFINE_PER_CPU(unsigned long, l_p_j_ref); | |
675 | static DEFINE_PER_CPU(unsigned long, l_p_j_ref_freq); | |
676 | static unsigned long global_l_p_j_ref; | |
677 | static unsigned long global_l_p_j_ref_freq; | |
678 | ||
679 | static int cpufreq_callback(struct notifier_block *nb, | |
680 | unsigned long val, void *data) | |
681 | { | |
682 | struct cpufreq_freqs *freq = data; | |
683 | int cpu = freq->cpu; | |
684 | ||
685 | if (freq->flags & CPUFREQ_CONST_LOOPS) | |
686 | return NOTIFY_OK; | |
687 | ||
688 | if (!per_cpu(l_p_j_ref, cpu)) { | |
689 | per_cpu(l_p_j_ref, cpu) = | |
690 | per_cpu(cpu_data, cpu).loops_per_jiffy; | |
691 | per_cpu(l_p_j_ref_freq, cpu) = freq->old; | |
692 | if (!global_l_p_j_ref) { | |
693 | global_l_p_j_ref = loops_per_jiffy; | |
694 | global_l_p_j_ref_freq = freq->old; | |
695 | } | |
696 | } | |
697 | ||
698 | if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || | |
699 | (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) || | |
700 | (val == CPUFREQ_RESUMECHANGE || val == CPUFREQ_SUSPENDCHANGE)) { | |
701 | loops_per_jiffy = cpufreq_scale(global_l_p_j_ref, | |
702 | global_l_p_j_ref_freq, | |
703 | freq->new); | |
704 | per_cpu(cpu_data, cpu).loops_per_jiffy = | |
705 | cpufreq_scale(per_cpu(l_p_j_ref, cpu), | |
706 | per_cpu(l_p_j_ref_freq, cpu), | |
707 | freq->new); | |
708 | } | |
709 | return NOTIFY_OK; | |
710 | } | |
711 | ||
712 | static struct notifier_block cpufreq_notifier = { | |
713 | .notifier_call = cpufreq_callback, | |
714 | }; | |
715 | ||
716 | static int __init register_cpufreq_notifier(void) | |
717 | { | |
718 | return cpufreq_register_notifier(&cpufreq_notifier, | |
719 | CPUFREQ_TRANSITION_NOTIFIER); | |
720 | } | |
721 | core_initcall(register_cpufreq_notifier); | |
722 | ||
723 | #endif |