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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/smp.c | |
3 | * | |
4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
c97d4869 | 10 | #include <linux/module.h> |
1da177e4 LT |
11 | #include <linux/delay.h> |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
68e21be2 | 14 | #include <linux/sched/mm.h> |
ef8bd77f | 15 | #include <linux/sched/hotplug.h> |
68db0cf1 | 16 | #include <linux/sched/task_stack.h> |
1da177e4 LT |
17 | #include <linux/interrupt.h> |
18 | #include <linux/cache.h> | |
19 | #include <linux/profile.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/mm.h> | |
4e950f6f | 22 | #include <linux/err.h> |
1da177e4 | 23 | #include <linux/cpu.h> |
1da177e4 | 24 | #include <linux/seq_file.h> |
c97d4869 | 25 | #include <linux/irq.h> |
96f0e003 | 26 | #include <linux/nmi.h> |
bc28248e RK |
27 | #include <linux/percpu.h> |
28 | #include <linux/clockchips.h> | |
3c030bea | 29 | #include <linux/completion.h> |
ec971ea5 | 30 | #include <linux/cpufreq.h> |
bf18525f | 31 | #include <linux/irq_work.h> |
1da177e4 | 32 | |
60063497 | 33 | #include <linux/atomic.h> |
26602161 | 34 | #include <asm/bugs.h> |
abcee5fb | 35 | #include <asm/smp.h> |
1da177e4 LT |
36 | #include <asm/cacheflush.h> |
37 | #include <asm/cpu.h> | |
42578c82 | 38 | #include <asm/cputype.h> |
5a567d78 | 39 | #include <asm/exception.h> |
8903826d | 40 | #include <asm/idmap.h> |
c9018aab | 41 | #include <asm/topology.h> |
e65f38ed RK |
42 | #include <asm/mmu_context.h> |
43 | #include <asm/pgtable.h> | |
44 | #include <asm/pgalloc.h> | |
383fb3ee | 45 | #include <asm/procinfo.h> |
1da177e4 | 46 | #include <asm/processor.h> |
37b05b63 | 47 | #include <asm/sections.h> |
1da177e4 LT |
48 | #include <asm/tlbflush.h> |
49 | #include <asm/ptrace.h> | |
d6257288 | 50 | #include <asm/smp_plat.h> |
4588c34d | 51 | #include <asm/virt.h> |
abcee5fb | 52 | #include <asm/mach/arch.h> |
eb08375e | 53 | #include <asm/mpu.h> |
1da177e4 | 54 | |
365ec7b1 NP |
55 | #define CREATE_TRACE_POINTS |
56 | #include <trace/events/ipi.h> | |
57 | ||
e65f38ed RK |
58 | /* |
59 | * as from 2.5, kernels no longer have an init_tasks structure | |
60 | * so we need some other way of telling a new secondary core | |
61 | * where to place its SVC stack | |
62 | */ | |
63 | struct secondary_data secondary_data; | |
64 | ||
1da177e4 | 65 | enum ipi_msg_type { |
559a5939 SB |
66 | IPI_WAKEUP, |
67 | IPI_TIMER, | |
1da177e4 LT |
68 | IPI_RESCHEDULE, |
69 | IPI_CALL_FUNC, | |
70 | IPI_CPU_STOP, | |
bf18525f | 71 | IPI_IRQ_WORK, |
5135d875 | 72 | IPI_COMPLETION, |
e7273ff4 MZ |
73 | IPI_CPU_BACKTRACE, |
74 | /* | |
75 | * SGI8-15 can be reserved by secure firmware, and thus may | |
76 | * not be usable by the kernel. Please keep the above limited | |
77 | * to at most 8 entries. | |
78 | */ | |
1da177e4 LT |
79 | }; |
80 | ||
149c2415 RK |
81 | static DECLARE_COMPLETION(cpu_running); |
82 | ||
7619751f | 83 | static struct smp_operations smp_ops __ro_after_init; |
abcee5fb | 84 | |
4caa9dda | 85 | void __init smp_set_ops(const struct smp_operations *ops) |
abcee5fb MZ |
86 | { |
87 | if (ops) | |
88 | smp_ops = *ops; | |
89 | }; | |
90 | ||
4756dcbf CC |
91 | static unsigned long get_arch_pgd(pgd_t *pgd) |
92 | { | |
b2c3e38a RK |
93 | #ifdef CONFIG_ARM_LPAE |
94 | return __phys_to_pfn(virt_to_phys(pgd)); | |
95 | #else | |
96 | return virt_to_phys(pgd); | |
97 | #endif | |
4756dcbf CC |
98 | } |
99 | ||
383fb3ee RK |
100 | #if defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR) |
101 | static int secondary_biglittle_prepare(unsigned int cpu) | |
102 | { | |
103 | if (!cpu_vtable[cpu]) | |
104 | cpu_vtable[cpu] = kzalloc(sizeof(*cpu_vtable[cpu]), GFP_KERNEL); | |
105 | ||
106 | return cpu_vtable[cpu] ? 0 : -ENOMEM; | |
107 | } | |
108 | ||
109 | static void secondary_biglittle_init(void) | |
110 | { | |
111 | init_proc_vtable(lookup_processor(read_cpuid_id())->proc); | |
112 | } | |
113 | #else | |
114 | static int secondary_biglittle_prepare(unsigned int cpu) | |
115 | { | |
116 | return 0; | |
117 | } | |
118 | ||
119 | static void secondary_biglittle_init(void) | |
120 | { | |
121 | } | |
122 | #endif | |
123 | ||
8bd26e3a | 124 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
1da177e4 | 125 | { |
1da177e4 LT |
126 | int ret; |
127 | ||
084bb5bc GU |
128 | if (!smp_ops.smp_boot_secondary) |
129 | return -ENOSYS; | |
130 | ||
383fb3ee RK |
131 | ret = secondary_biglittle_prepare(cpu); |
132 | if (ret) | |
133 | return ret; | |
134 | ||
e65f38ed RK |
135 | /* |
136 | * We need to tell the secondary core where to find | |
137 | * its stack and the page tables. | |
138 | */ | |
32d39a93 | 139 | secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; |
eb08375e | 140 | #ifdef CONFIG_ARM_MPU |
a0995c08 | 141 | secondary_data.mpu_rgn_info = &mpu_rgn_info; |
eb08375e JA |
142 | #endif |
143 | ||
c4a1f032 | 144 | #ifdef CONFIG_MMU |
b2c3e38a | 145 | secondary_data.pgdir = virt_to_phys(idmap_pgd); |
4756dcbf | 146 | secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir); |
c4a1f032 | 147 | #endif |
efcfc46e | 148 | sync_cache_w(&secondary_data); |
e65f38ed | 149 | |
1da177e4 LT |
150 | /* |
151 | * Now bring the CPU into our world. | |
152 | */ | |
084bb5bc | 153 | ret = smp_ops.smp_boot_secondary(cpu, idle); |
e65f38ed | 154 | if (ret == 0) { |
e65f38ed RK |
155 | /* |
156 | * CPU was successfully started, wait for it | |
157 | * to come online or time out. | |
158 | */ | |
149c2415 RK |
159 | wait_for_completion_timeout(&cpu_running, |
160 | msecs_to_jiffies(1000)); | |
e65f38ed | 161 | |
58613cd1 RK |
162 | if (!cpu_online(cpu)) { |
163 | pr_crit("CPU%u: failed to come online\n", cpu); | |
e65f38ed | 164 | ret = -EIO; |
58613cd1 RK |
165 | } |
166 | } else { | |
167 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
e65f38ed RK |
168 | } |
169 | ||
e65f38ed | 170 | |
eb08375e | 171 | memset(&secondary_data, 0, sizeof(secondary_data)); |
1da177e4 LT |
172 | return ret; |
173 | } | |
174 | ||
abcee5fb | 175 | /* platform specific SMP operations */ |
ac6c7998 | 176 | void __init smp_init_cpus(void) |
abcee5fb MZ |
177 | { |
178 | if (smp_ops.smp_init_cpus) | |
179 | smp_ops.smp_init_cpus(); | |
180 | } | |
181 | ||
fee3fd4f GU |
182 | int platform_can_secondary_boot(void) |
183 | { | |
184 | return !!smp_ops.smp_boot_secondary; | |
185 | } | |
186 | ||
2103f6cb SW |
187 | int platform_can_cpu_hotplug(void) |
188 | { | |
189 | #ifdef CONFIG_HOTPLUG_CPU | |
190 | if (smp_ops.cpu_kill) | |
191 | return 1; | |
192 | #endif | |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
a054a811 | 197 | #ifdef CONFIG_HOTPLUG_CPU |
ac6c7998 | 198 | static int platform_cpu_kill(unsigned int cpu) |
abcee5fb MZ |
199 | { |
200 | if (smp_ops.cpu_kill) | |
201 | return smp_ops.cpu_kill(cpu); | |
202 | return 1; | |
203 | } | |
204 | ||
ac6c7998 | 205 | static int platform_cpu_disable(unsigned int cpu) |
abcee5fb MZ |
206 | { |
207 | if (smp_ops.cpu_disable) | |
208 | return smp_ops.cpu_disable(cpu); | |
209 | ||
787047ee SB |
210 | return 0; |
211 | } | |
212 | ||
213 | int platform_can_hotplug_cpu(unsigned int cpu) | |
214 | { | |
215 | /* cpu_die must be specified to support hotplug */ | |
216 | if (!smp_ops.cpu_die) | |
217 | return 0; | |
218 | ||
219 | if (smp_ops.cpu_can_disable) | |
220 | return smp_ops.cpu_can_disable(cpu); | |
221 | ||
abcee5fb MZ |
222 | /* |
223 | * By default, allow disabling all CPUs except the first one, | |
224 | * since this is special on a lot of platforms, e.g. because | |
225 | * of clock tick interrupts. | |
226 | */ | |
787047ee | 227 | return cpu != 0; |
abcee5fb | 228 | } |
787047ee | 229 | |
a054a811 RK |
230 | /* |
231 | * __cpu_disable runs on the processor to be shutdown. | |
232 | */ | |
8bd26e3a | 233 | int __cpu_disable(void) |
a054a811 RK |
234 | { |
235 | unsigned int cpu = smp_processor_id(); | |
a054a811 RK |
236 | int ret; |
237 | ||
8e2a43f5 | 238 | ret = platform_cpu_disable(cpu); |
a054a811 RK |
239 | if (ret) |
240 | return ret; | |
241 | ||
242 | /* | |
243 | * Take this CPU offline. Once we clear this, we can't return, | |
244 | * and we must not schedule until we're ready to give up the cpu. | |
245 | */ | |
e03cdade | 246 | set_cpu_online(cpu, false); |
a054a811 RK |
247 | |
248 | /* | |
249 | * OK - migrate IRQs away from this CPU | |
250 | */ | |
251 | migrate_irqs(); | |
252 | ||
253 | /* | |
254 | * Flush user cache and TLB mappings, and then remove this CPU | |
255 | * from the vm mask set of all processes. | |
e6b866e9 LP |
256 | * |
257 | * Caches are flushed to the Level of Unification Inner Shareable | |
258 | * to write-back dirty lines to unified caches shared by all CPUs. | |
a054a811 | 259 | */ |
e6b866e9 | 260 | flush_cache_louis(); |
a054a811 RK |
261 | local_flush_tlb_all(); |
262 | ||
a054a811 RK |
263 | return 0; |
264 | } | |
265 | ||
3c030bea RK |
266 | static DECLARE_COMPLETION(cpu_died); |
267 | ||
a054a811 RK |
268 | /* |
269 | * called on the thread which is asking for a CPU to be shutdown - | |
270 | * waits until shutdown has completed, or it is timed out. | |
271 | */ | |
8bd26e3a | 272 | void __cpu_die(unsigned int cpu) |
a054a811 | 273 | { |
3c030bea RK |
274 | if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) { |
275 | pr_err("CPU%u: cpu didn't die\n", cpu); | |
276 | return; | |
277 | } | |
035e7875 | 278 | pr_debug("CPU%u: shutdown\n", cpu); |
3c030bea | 279 | |
98f1b5a7 | 280 | clear_tasks_mm_cpumask(cpu); |
51acdfd1 RK |
281 | /* |
282 | * platform_cpu_kill() is generally expected to do the powering off | |
283 | * and/or cutting of clocks to the dying CPU. Optionally, this may | |
284 | * be done by the CPU which is dying in preference to supporting | |
285 | * this call, but that means there is _no_ synchronisation between | |
286 | * the requesting CPU and the dying CPU actually losing power. | |
287 | */ | |
a054a811 | 288 | if (!platform_cpu_kill(cpu)) |
4ed89f22 | 289 | pr_err("CPU%u: unable to kill\n", cpu); |
a054a811 RK |
290 | } |
291 | ||
292 | /* | |
293 | * Called from the idle thread for the CPU which has been shutdown. | |
294 | * | |
295 | * Note that we disable IRQs here, but do not re-enable them | |
296 | * before returning to the caller. This is also the behaviour | |
297 | * of the other hotplug-cpu capable cores, so presumably coming | |
298 | * out of idle fixes this. | |
299 | */ | |
9205b797 | 300 | void arch_cpu_idle_dead(void) |
a054a811 RK |
301 | { |
302 | unsigned int cpu = smp_processor_id(); | |
303 | ||
a054a811 RK |
304 | idle_task_exit(); |
305 | ||
f36d3401 | 306 | local_irq_disable(); |
f36d3401 | 307 | |
51acdfd1 RK |
308 | /* |
309 | * Flush the data out of the L1 cache for this CPU. This must be | |
310 | * before the completion to ensure that data is safely written out | |
311 | * before platform_cpu_kill() gets called - which may disable | |
312 | * *this* CPU and power down its cache. | |
313 | */ | |
314 | flush_cache_louis(); | |
315 | ||
316 | /* | |
317 | * Tell __cpu_die() that this CPU is now safe to dispose of. Once | |
318 | * this returns, power and/or clocks can be removed at any point | |
319 | * from this CPU and its cache by platform_cpu_kill(). | |
320 | */ | |
aa033810 | 321 | complete(&cpu_died); |
3c030bea | 322 | |
a054a811 | 323 | /* |
51acdfd1 RK |
324 | * Ensure that the cache lines associated with that completion are |
325 | * written out. This covers the case where _this_ CPU is doing the | |
326 | * powering down, to ensure that the completion is visible to the | |
327 | * CPU waiting for this one. | |
328 | */ | |
329 | flush_cache_louis(); | |
330 | ||
331 | /* | |
332 | * The actual CPU shutdown procedure is at least platform (if not | |
333 | * CPU) specific. This may remove power, or it may simply spin. | |
334 | * | |
335 | * Platforms are generally expected *NOT* to return from this call, | |
336 | * although there are some which do because they have no way to | |
337 | * power down the CPU. These platforms are the _only_ reason we | |
338 | * have a return path which uses the fragment of assembly below. | |
339 | * | |
340 | * The return path should not be used for platforms which can | |
341 | * power off the CPU. | |
a054a811 | 342 | */ |
0a301110 RK |
343 | if (smp_ops.cpu_die) |
344 | smp_ops.cpu_die(cpu); | |
a054a811 | 345 | |
668bc386 RK |
346 | pr_warn("CPU%u: smp_ops.cpu_die() returned, trying to resuscitate\n", |
347 | cpu); | |
348 | ||
a054a811 RK |
349 | /* |
350 | * Do not return to the idle loop - jump back to the secondary | |
351 | * cpu initialisation. There's some initialisation which needs | |
352 | * to be repeated to undo the effects of taking the CPU offline. | |
353 | */ | |
354 | __asm__("mov sp, %0\n" | |
faabfa08 | 355 | " mov fp, #0\n" |
a054a811 RK |
356 | " b secondary_start_kernel" |
357 | : | |
32d39a93 | 358 | : "r" (task_stack_page(current) + THREAD_SIZE - 8)); |
a054a811 RK |
359 | } |
360 | #endif /* CONFIG_HOTPLUG_CPU */ | |
361 | ||
05c74a6c RK |
362 | /* |
363 | * Called by both boot and secondaries to move global data into | |
364 | * per-processor storage. | |
365 | */ | |
8bd26e3a | 366 | static void smp_store_cpu_info(unsigned int cpuid) |
05c74a6c RK |
367 | { |
368 | struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid); | |
369 | ||
370 | cpu_info->loops_per_jiffy = loops_per_jiffy; | |
e8d432c9 | 371 | cpu_info->cpuid = read_cpuid_id(); |
c9018aab VG |
372 | |
373 | store_cpu_topology(cpuid); | |
05c74a6c RK |
374 | } |
375 | ||
e65f38ed RK |
376 | /* |
377 | * This is the secondary CPU boot entry. We're using this CPUs | |
378 | * idle thread stack, but a set of temporary page tables. | |
379 | */ | |
8bd26e3a | 380 | asmlinkage void secondary_start_kernel(void) |
e65f38ed RK |
381 | { |
382 | struct mm_struct *mm = &init_mm; | |
5f40b909 WD |
383 | unsigned int cpu; |
384 | ||
383fb3ee RK |
385 | secondary_biglittle_init(); |
386 | ||
5f40b909 WD |
387 | /* |
388 | * The identity mapping is uncached (strongly ordered), so | |
389 | * switch away from it before attempting any exclusive accesses. | |
390 | */ | |
391 | cpu_switch_mm(mm->pgd, mm); | |
89c7e4b8 | 392 | local_flush_bp_all(); |
5f40b909 WD |
393 | enter_lazy_tlb(mm, current); |
394 | local_flush_tlb_all(); | |
e65f38ed | 395 | |
e65f38ed RK |
396 | /* |
397 | * All kernel threads share the same mm context; grab a | |
398 | * reference and switch to it. | |
399 | */ | |
5f40b909 | 400 | cpu = smp_processor_id(); |
f1f10076 | 401 | mmgrab(mm); |
e65f38ed | 402 | current->active_mm = mm; |
56f8ba83 | 403 | cpumask_set_cpu(cpu, mm_cpumask(mm)); |
e65f38ed | 404 | |
14318efb RH |
405 | cpu_init(); |
406 | ||
62d1c95d VM |
407 | #ifndef CONFIG_MMU |
408 | setup_vectors_base(); | |
409 | #endif | |
c68b0274 | 410 | pr_debug("CPU%u: Booted secondary processor\n", cpu); |
fde165b2 | 411 | |
5bfb5d69 | 412 | preempt_disable(); |
2c0136db | 413 | trace_hardirqs_off(); |
e65f38ed RK |
414 | |
415 | /* | |
416 | * Give the platform a chance to do its own initialisation. | |
417 | */ | |
0a301110 RK |
418 | if (smp_ops.smp_secondary_init) |
419 | smp_ops.smp_secondary_init(cpu); | |
e65f38ed | 420 | |
e545a614 | 421 | notify_cpu_starting(cpu); |
a8655e83 | 422 | |
e65f38ed RK |
423 | calibrate_delay(); |
424 | ||
425 | smp_store_cpu_info(cpu); | |
426 | ||
427 | /* | |
573619d1 RK |
428 | * OK, now it's safe to let the boot CPU continue. Wait for |
429 | * the CPU migration code to notice that the CPU is online | |
149c2415 | 430 | * before we continue - which happens after __cpu_up returns. |
e65f38ed | 431 | */ |
e03cdade | 432 | set_cpu_online(cpu, true); |
26602161 RK |
433 | |
434 | check_other_bugs(); | |
435 | ||
149c2415 | 436 | complete(&cpu_running); |
eb047454 | 437 | |
eb047454 TG |
438 | local_irq_enable(); |
439 | local_fiq_enable(); | |
bbeb9209 | 440 | local_abt_enable(); |
eb047454 | 441 | |
e65f38ed RK |
442 | /* |
443 | * OK, it's off to the idle thread for us | |
444 | */ | |
fc6d73d6 | 445 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
e65f38ed RK |
446 | } |
447 | ||
1da177e4 LT |
448 | void __init smp_cpus_done(unsigned int max_cpus) |
449 | { | |
4bf9636c PM |
450 | int cpu; |
451 | unsigned long bogosum = 0; | |
452 | ||
453 | for_each_online_cpu(cpu) | |
454 | bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy; | |
455 | ||
456 | printk(KERN_INFO "SMP: Total of %d processors activated " | |
457 | "(%lu.%02lu BogoMIPS).\n", | |
458 | num_online_cpus(), | |
459 | bogosum / (500000/HZ), | |
460 | (bogosum / (5000/HZ)) % 100); | |
461 | ||
4588c34d | 462 | hyp_mode_check(); |
1da177e4 LT |
463 | } |
464 | ||
465 | void __init smp_prepare_boot_cpu(void) | |
466 | { | |
14318efb | 467 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
1da177e4 LT |
468 | } |
469 | ||
05c74a6c | 470 | void __init smp_prepare_cpus(unsigned int max_cpus) |
1da177e4 | 471 | { |
05c74a6c | 472 | unsigned int ncores = num_possible_cpus(); |
1da177e4 | 473 | |
c9018aab VG |
474 | init_cpu_topology(); |
475 | ||
05c74a6c | 476 | smp_store_cpu_info(smp_processor_id()); |
1da177e4 LT |
477 | |
478 | /* | |
05c74a6c | 479 | * are we trying to boot more cores than exist? |
1da177e4 | 480 | */ |
05c74a6c RK |
481 | if (max_cpus > ncores) |
482 | max_cpus = ncores; | |
7fa22bd5 | 483 | if (ncores > 1 && max_cpus) { |
7fa22bd5 SB |
484 | /* |
485 | * Initialise the present map, which describes the set of CPUs | |
486 | * actually populated at the present time. A platform should | |
0a301110 RK |
487 | * re-initialize the map in the platforms smp_prepare_cpus() |
488 | * if present != possible (e.g. physical hotplug). | |
7fa22bd5 | 489 | */ |
0b5f9c00 | 490 | init_cpu_present(cpu_possible_mask); |
7fa22bd5 | 491 | |
05c74a6c RK |
492 | /* |
493 | * Initialise the SCU if there are more than one CPU | |
494 | * and let them know where to start. | |
495 | */ | |
0a301110 RK |
496 | if (smp_ops.smp_prepare_cpus) |
497 | smp_ops.smp_prepare_cpus(max_cpus); | |
05c74a6c | 498 | } |
1da177e4 LT |
499 | } |
500 | ||
365ec7b1 | 501 | static void (*__smp_cross_call)(const struct cpumask *, unsigned int); |
0f7b332f RK |
502 | |
503 | void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) | |
504 | { | |
365ec7b1 NP |
505 | if (!__smp_cross_call) |
506 | __smp_cross_call = fn; | |
3e459990 | 507 | } |
3e459990 | 508 | |
365ec7b1 | 509 | static const char *ipi_types[NR_IPI] __tracepoint_string = { |
559a5939 SB |
510 | #define S(x,s) [x] = s |
511 | S(IPI_WAKEUP, "CPU wakeup interrupts"), | |
4a88abd7 RK |
512 | S(IPI_TIMER, "Timer broadcast interrupts"), |
513 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), | |
514 | S(IPI_CALL_FUNC, "Function call interrupts"), | |
4a88abd7 | 515 | S(IPI_CPU_STOP, "CPU stop interrupts"), |
bf18525f | 516 | S(IPI_IRQ_WORK, "IRQ work interrupts"), |
5135d875 | 517 | S(IPI_COMPLETION, "completion interrupts"), |
4a88abd7 RK |
518 | }; |
519 | ||
365ec7b1 NP |
520 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) |
521 | { | |
7c64cc05 | 522 | trace_ipi_raise_rcuidle(target, ipi_types[ipinr]); |
365ec7b1 NP |
523 | __smp_cross_call(target, ipinr); |
524 | } | |
525 | ||
f13cd417 | 526 | void show_ipi_list(struct seq_file *p, int prec) |
1da177e4 | 527 | { |
4a88abd7 | 528 | unsigned int cpu, i; |
1da177e4 | 529 | |
4a88abd7 RK |
530 | for (i = 0; i < NR_IPI; i++) { |
531 | seq_printf(p, "%*s%u: ", prec - 1, "IPI", i); | |
1da177e4 | 532 | |
026b7c6b | 533 | for_each_online_cpu(cpu) |
4a88abd7 RK |
534 | seq_printf(p, "%10u ", |
535 | __get_irq_stat(cpu, ipi_irqs[i])); | |
1da177e4 | 536 | |
4a88abd7 RK |
537 | seq_printf(p, " %s\n", ipi_types[i]); |
538 | } | |
1da177e4 LT |
539 | } |
540 | ||
b54992fe | 541 | u64 smp_irq_stat_cpu(unsigned int cpu) |
37ee16ae | 542 | { |
b54992fe RK |
543 | u64 sum = 0; |
544 | int i; | |
37ee16ae | 545 | |
b54992fe RK |
546 | for (i = 0; i < NR_IPI; i++) |
547 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | |
37ee16ae | 548 | |
b54992fe | 549 | return sum; |
37ee16ae RK |
550 | } |
551 | ||
365ec7b1 NP |
552 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
553 | { | |
554 | smp_cross_call(mask, IPI_CALL_FUNC); | |
555 | } | |
556 | ||
557 | void arch_send_wakeup_ipi_mask(const struct cpumask *mask) | |
558 | { | |
559 | smp_cross_call(mask, IPI_WAKEUP); | |
560 | } | |
561 | ||
562 | void arch_send_call_function_single_ipi(int cpu) | |
563 | { | |
89d798b7 | 564 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC); |
365ec7b1 NP |
565 | } |
566 | ||
567 | #ifdef CONFIG_IRQ_WORK | |
568 | void arch_irq_work_raise(void) | |
569 | { | |
09f6edd4 | 570 | if (arch_irq_work_has_interrupt()) |
365ec7b1 NP |
571 | smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); |
572 | } | |
573 | #endif | |
574 | ||
bc28248e | 575 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
3d06770e | 576 | void tick_broadcast(const struct cpumask *mask) |
bc28248e | 577 | { |
e3fbb087 | 578 | smp_cross_call(mask, IPI_TIMER); |
bc28248e | 579 | } |
5388a6b2 | 580 | #endif |
bc28248e | 581 | |
bd31b859 | 582 | static DEFINE_RAW_SPINLOCK(stop_lock); |
1da177e4 LT |
583 | |
584 | /* | |
585 | * ipi_cpu_stop - handle IPI from smp_send_stop() | |
586 | */ | |
587 | static void ipi_cpu_stop(unsigned int cpu) | |
588 | { | |
5976a669 | 589 | if (system_state <= SYSTEM_RUNNING) { |
bd31b859 | 590 | raw_spin_lock(&stop_lock); |
4ed89f22 | 591 | pr_crit("CPU%u: stopping\n", cpu); |
3d3f78d7 | 592 | dump_stack(); |
bd31b859 | 593 | raw_spin_unlock(&stop_lock); |
3d3f78d7 | 594 | } |
1da177e4 | 595 | |
e03cdade | 596 | set_cpu_online(cpu, false); |
1da177e4 LT |
597 | |
598 | local_fiq_disable(); | |
599 | local_irq_disable(); | |
600 | ||
601 | while (1) | |
602 | cpu_relax(); | |
603 | } | |
604 | ||
5135d875 NP |
605 | static DEFINE_PER_CPU(struct completion *, cpu_completion); |
606 | ||
607 | int register_ipi_completion(struct completion *completion, int cpu) | |
608 | { | |
609 | per_cpu(cpu_completion, cpu) = completion; | |
610 | return IPI_COMPLETION; | |
611 | } | |
612 | ||
613 | static void ipi_complete(unsigned int cpu) | |
614 | { | |
615 | complete(per_cpu(cpu_completion, cpu)); | |
616 | } | |
617 | ||
1da177e4 LT |
618 | /* |
619 | * Main handler for inter-processor interrupts | |
1da177e4 | 620 | */ |
4073723a | 621 | asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs) |
0b5a1b95 SG |
622 | { |
623 | handle_IPI(ipinr, regs); | |
624 | } | |
625 | ||
626 | void handle_IPI(int ipinr, struct pt_regs *regs) | |
1da177e4 LT |
627 | { |
628 | unsigned int cpu = smp_processor_id(); | |
c97d4869 | 629 | struct pt_regs *old_regs = set_irq_regs(regs); |
1da177e4 | 630 | |
365ec7b1 | 631 | if ((unsigned)ipinr < NR_IPI) { |
398f7456 | 632 | trace_ipi_entry_rcuidle(ipi_types[ipinr]); |
559a5939 | 633 | __inc_irq_stat(cpu, ipi_irqs[ipinr]); |
365ec7b1 | 634 | } |
1da177e4 | 635 | |
24480d98 | 636 | switch (ipinr) { |
559a5939 SB |
637 | case IPI_WAKEUP: |
638 | break; | |
639 | ||
e2c50119 | 640 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
24480d98 | 641 | case IPI_TIMER: |
7deabca0 | 642 | irq_enter(); |
e2c50119 | 643 | tick_receive_broadcast(); |
7deabca0 | 644 | irq_exit(); |
24480d98 | 645 | break; |
e2c50119 | 646 | #endif |
1da177e4 | 647 | |
24480d98 | 648 | case IPI_RESCHEDULE: |
184748cc | 649 | scheduler_ipi(); |
24480d98 | 650 | break; |
1da177e4 | 651 | |
24480d98 | 652 | case IPI_CALL_FUNC: |
7deabca0 | 653 | irq_enter(); |
24480d98 | 654 | generic_smp_call_function_interrupt(); |
7deabca0 | 655 | irq_exit(); |
24480d98 | 656 | break; |
1da177e4 | 657 | |
24480d98 | 658 | case IPI_CPU_STOP: |
7deabca0 | 659 | irq_enter(); |
24480d98 | 660 | ipi_cpu_stop(cpu); |
7deabca0 | 661 | irq_exit(); |
24480d98 | 662 | break; |
1da177e4 | 663 | |
bf18525f SB |
664 | #ifdef CONFIG_IRQ_WORK |
665 | case IPI_IRQ_WORK: | |
666 | irq_enter(); | |
667 | irq_work_run(); | |
668 | irq_exit(); | |
669 | break; | |
670 | #endif | |
671 | ||
5135d875 NP |
672 | case IPI_COMPLETION: |
673 | irq_enter(); | |
674 | ipi_complete(cpu); | |
675 | irq_exit(); | |
676 | break; | |
677 | ||
96f0e003 | 678 | case IPI_CPU_BACKTRACE: |
42a0bb3f | 679 | printk_nmi_enter(); |
96f0e003 RK |
680 | irq_enter(); |
681 | nmi_cpu_backtrace(regs); | |
682 | irq_exit(); | |
42a0bb3f | 683 | printk_nmi_exit(); |
96f0e003 RK |
684 | break; |
685 | ||
24480d98 | 686 | default: |
4ed89f22 RK |
687 | pr_crit("CPU%u: Unknown IPI message 0x%x\n", |
688 | cpu, ipinr); | |
24480d98 | 689 | break; |
1da177e4 | 690 | } |
365ec7b1 NP |
691 | |
692 | if ((unsigned)ipinr < NR_IPI) | |
398f7456 | 693 | trace_ipi_exit_rcuidle(ipi_types[ipinr]); |
c97d4869 | 694 | set_irq_regs(old_regs); |
1da177e4 LT |
695 | } |
696 | ||
697 | void smp_send_reschedule(int cpu) | |
698 | { | |
e3fbb087 | 699 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); |
1da177e4 LT |
700 | } |
701 | ||
1da177e4 LT |
702 | void smp_send_stop(void) |
703 | { | |
28e18293 | 704 | unsigned long timeout; |
6fa99b7f | 705 | struct cpumask mask; |
1da177e4 | 706 | |
6fa99b7f WD |
707 | cpumask_copy(&mask, cpu_online_mask); |
708 | cpumask_clear_cpu(smp_processor_id(), &mask); | |
c5dff4ff JMC |
709 | if (!cpumask_empty(&mask)) |
710 | smp_cross_call(&mask, IPI_CPU_STOP); | |
4b0ef3b1 | 711 | |
28e18293 RK |
712 | /* Wait up to one second for other CPUs to stop */ |
713 | timeout = USEC_PER_SEC; | |
714 | while (num_online_cpus() > 1 && timeout--) | |
715 | udelay(1); | |
4b0ef3b1 | 716 | |
28e18293 | 717 | if (num_online_cpus() > 1) |
8b521cb2 | 718 | pr_warn("SMP: failed to stop secondary CPUs\n"); |
4b0ef3b1 RK |
719 | } |
720 | ||
82c08c3e YW |
721 | /* In case panic() and panic() called at the same time on CPU1 and CPU2, |
722 | * and CPU 1 calls panic_smp_self_stop() before crash_smp_send_stop() | |
723 | * CPU1 can't receive the ipi irqs from CPU2, CPU1 will be always online, | |
724 | * kdump fails. So split out the panic_smp_self_stop() and add | |
725 | * set_cpu_online(smp_processor_id(), false). | |
726 | */ | |
727 | void panic_smp_self_stop(void) | |
728 | { | |
729 | pr_debug("CPU %u will stop doing anything useful since another CPU has paniced\n", | |
730 | smp_processor_id()); | |
731 | set_cpu_online(smp_processor_id(), false); | |
732 | while (1) | |
733 | cpu_relax(); | |
734 | } | |
735 | ||
4b0ef3b1 | 736 | /* |
1da177e4 | 737 | * not supported here |
4b0ef3b1 | 738 | */ |
5048bcba | 739 | int setup_profiling_timer(unsigned int multiplier) |
4b0ef3b1 | 740 | { |
1da177e4 | 741 | return -EINVAL; |
4b0ef3b1 | 742 | } |
ec971ea5 RZ |
743 | |
744 | #ifdef CONFIG_CPU_FREQ | |
745 | ||
746 | static DEFINE_PER_CPU(unsigned long, l_p_j_ref); | |
747 | static DEFINE_PER_CPU(unsigned long, l_p_j_ref_freq); | |
748 | static unsigned long global_l_p_j_ref; | |
749 | static unsigned long global_l_p_j_ref_freq; | |
750 | ||
751 | static int cpufreq_callback(struct notifier_block *nb, | |
752 | unsigned long val, void *data) | |
753 | { | |
754 | struct cpufreq_freqs *freq = data; | |
755 | int cpu = freq->cpu; | |
756 | ||
757 | if (freq->flags & CPUFREQ_CONST_LOOPS) | |
758 | return NOTIFY_OK; | |
759 | ||
760 | if (!per_cpu(l_p_j_ref, cpu)) { | |
761 | per_cpu(l_p_j_ref, cpu) = | |
762 | per_cpu(cpu_data, cpu).loops_per_jiffy; | |
763 | per_cpu(l_p_j_ref_freq, cpu) = freq->old; | |
764 | if (!global_l_p_j_ref) { | |
765 | global_l_p_j_ref = loops_per_jiffy; | |
766 | global_l_p_j_ref_freq = freq->old; | |
767 | } | |
768 | } | |
769 | ||
770 | if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || | |
0b443ead | 771 | (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { |
ec971ea5 RZ |
772 | loops_per_jiffy = cpufreq_scale(global_l_p_j_ref, |
773 | global_l_p_j_ref_freq, | |
774 | freq->new); | |
775 | per_cpu(cpu_data, cpu).loops_per_jiffy = | |
776 | cpufreq_scale(per_cpu(l_p_j_ref, cpu), | |
777 | per_cpu(l_p_j_ref_freq, cpu), | |
778 | freq->new); | |
779 | } | |
780 | return NOTIFY_OK; | |
781 | } | |
782 | ||
783 | static struct notifier_block cpufreq_notifier = { | |
784 | .notifier_call = cpufreq_callback, | |
785 | }; | |
786 | ||
787 | static int __init register_cpufreq_notifier(void) | |
788 | { | |
789 | return cpufreq_register_notifier(&cpufreq_notifier, | |
790 | CPUFREQ_TRANSITION_NOTIFIER); | |
791 | } | |
792 | core_initcall(register_cpufreq_notifier); | |
793 | ||
794 | #endif | |
96f0e003 RK |
795 | |
796 | static void raise_nmi(cpumask_t *mask) | |
797 | { | |
798 | smp_cross_call(mask, IPI_CPU_BACKTRACE); | |
799 | } | |
800 | ||
9a01c3ed | 801 | void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) |
96f0e003 | 802 | { |
9a01c3ed | 803 | nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_nmi); |
96f0e003 | 804 | } |