]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - arch/arm/kernel/smp.c
Merge tag 'powerpc-5.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / kernel / smp.c
CommitLineData
1da177e4
LT
1/*
2 * linux/arch/arm/kernel/smp.c
3 *
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
c97d4869 10#include <linux/module.h>
1da177e4
LT
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
68e21be2 14#include <linux/sched/mm.h>
ef8bd77f 15#include <linux/sched/hotplug.h>
68db0cf1 16#include <linux/sched/task_stack.h>
1da177e4
LT
17#include <linux/interrupt.h>
18#include <linux/cache.h>
19#include <linux/profile.h>
20#include <linux/errno.h>
21#include <linux/mm.h>
4e950f6f 22#include <linux/err.h>
1da177e4 23#include <linux/cpu.h>
1da177e4 24#include <linux/seq_file.h>
c97d4869 25#include <linux/irq.h>
96f0e003 26#include <linux/nmi.h>
bc28248e
RK
27#include <linux/percpu.h>
28#include <linux/clockchips.h>
3c030bea 29#include <linux/completion.h>
ec971ea5 30#include <linux/cpufreq.h>
bf18525f 31#include <linux/irq_work.h>
1da177e4 32
60063497 33#include <linux/atomic.h>
26602161 34#include <asm/bugs.h>
abcee5fb 35#include <asm/smp.h>
1da177e4
LT
36#include <asm/cacheflush.h>
37#include <asm/cpu.h>
42578c82 38#include <asm/cputype.h>
5a567d78 39#include <asm/exception.h>
8903826d 40#include <asm/idmap.h>
c9018aab 41#include <asm/topology.h>
e65f38ed
RK
42#include <asm/mmu_context.h>
43#include <asm/pgtable.h>
44#include <asm/pgalloc.h>
383fb3ee 45#include <asm/procinfo.h>
1da177e4 46#include <asm/processor.h>
37b05b63 47#include <asm/sections.h>
1da177e4
LT
48#include <asm/tlbflush.h>
49#include <asm/ptrace.h>
d6257288 50#include <asm/smp_plat.h>
4588c34d 51#include <asm/virt.h>
abcee5fb 52#include <asm/mach/arch.h>
eb08375e 53#include <asm/mpu.h>
1da177e4 54
365ec7b1
NP
55#define CREATE_TRACE_POINTS
56#include <trace/events/ipi.h>
57
e65f38ed
RK
58/*
59 * as from 2.5, kernels no longer have an init_tasks structure
60 * so we need some other way of telling a new secondary core
61 * where to place its SVC stack
62 */
63struct secondary_data secondary_data;
64
1da177e4 65enum ipi_msg_type {
559a5939
SB
66 IPI_WAKEUP,
67 IPI_TIMER,
1da177e4
LT
68 IPI_RESCHEDULE,
69 IPI_CALL_FUNC,
70 IPI_CPU_STOP,
bf18525f 71 IPI_IRQ_WORK,
5135d875 72 IPI_COMPLETION,
be167862
AB
73 /*
74 * CPU_BACKTRACE is special and not included in NR_IPI
75 * or tracable with trace_ipi_*
76 */
e7273ff4
MZ
77 IPI_CPU_BACKTRACE,
78 /*
79 * SGI8-15 can be reserved by secure firmware, and thus may
80 * not be usable by the kernel. Please keep the above limited
81 * to at most 8 entries.
82 */
1da177e4
LT
83};
84
149c2415
RK
85static DECLARE_COMPLETION(cpu_running);
86
7619751f 87static struct smp_operations smp_ops __ro_after_init;
abcee5fb 88
4caa9dda 89void __init smp_set_ops(const struct smp_operations *ops)
abcee5fb
MZ
90{
91 if (ops)
92 smp_ops = *ops;
93};
94
4756dcbf
CC
95static unsigned long get_arch_pgd(pgd_t *pgd)
96{
b2c3e38a
RK
97#ifdef CONFIG_ARM_LPAE
98 return __phys_to_pfn(virt_to_phys(pgd));
99#else
100 return virt_to_phys(pgd);
101#endif
4756dcbf
CC
102}
103
383fb3ee
RK
104#if defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR)
105static int secondary_biglittle_prepare(unsigned int cpu)
106{
107 if (!cpu_vtable[cpu])
108 cpu_vtable[cpu] = kzalloc(sizeof(*cpu_vtable[cpu]), GFP_KERNEL);
109
110 return cpu_vtable[cpu] ? 0 : -ENOMEM;
111}
112
113static void secondary_biglittle_init(void)
114{
115 init_proc_vtable(lookup_processor(read_cpuid_id())->proc);
116}
117#else
118static int secondary_biglittle_prepare(unsigned int cpu)
119{
120 return 0;
121}
122
123static void secondary_biglittle_init(void)
124{
125}
126#endif
127
8bd26e3a 128int __cpu_up(unsigned int cpu, struct task_struct *idle)
1da177e4 129{
1da177e4
LT
130 int ret;
131
084bb5bc
GU
132 if (!smp_ops.smp_boot_secondary)
133 return -ENOSYS;
134
383fb3ee
RK
135 ret = secondary_biglittle_prepare(cpu);
136 if (ret)
137 return ret;
138
e65f38ed
RK
139 /*
140 * We need to tell the secondary core where to find
141 * its stack and the page tables.
142 */
32d39a93 143 secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
eb08375e 144#ifdef CONFIG_ARM_MPU
a0995c08 145 secondary_data.mpu_rgn_info = &mpu_rgn_info;
eb08375e
JA
146#endif
147
c4a1f032 148#ifdef CONFIG_MMU
b2c3e38a 149 secondary_data.pgdir = virt_to_phys(idmap_pgd);
4756dcbf 150 secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir);
c4a1f032 151#endif
efcfc46e 152 sync_cache_w(&secondary_data);
e65f38ed 153
1da177e4
LT
154 /*
155 * Now bring the CPU into our world.
156 */
084bb5bc 157 ret = smp_ops.smp_boot_secondary(cpu, idle);
e65f38ed 158 if (ret == 0) {
e65f38ed
RK
159 /*
160 * CPU was successfully started, wait for it
161 * to come online or time out.
162 */
149c2415
RK
163 wait_for_completion_timeout(&cpu_running,
164 msecs_to_jiffies(1000));
e65f38ed 165
58613cd1
RK
166 if (!cpu_online(cpu)) {
167 pr_crit("CPU%u: failed to come online\n", cpu);
e65f38ed 168 ret = -EIO;
58613cd1
RK
169 }
170 } else {
171 pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
e65f38ed
RK
172 }
173
e65f38ed 174
eb08375e 175 memset(&secondary_data, 0, sizeof(secondary_data));
1da177e4
LT
176 return ret;
177}
178
abcee5fb 179/* platform specific SMP operations */
ac6c7998 180void __init smp_init_cpus(void)
abcee5fb
MZ
181{
182 if (smp_ops.smp_init_cpus)
183 smp_ops.smp_init_cpus();
184}
185
fee3fd4f
GU
186int platform_can_secondary_boot(void)
187{
188 return !!smp_ops.smp_boot_secondary;
189}
190
2103f6cb
SW
191int platform_can_cpu_hotplug(void)
192{
193#ifdef CONFIG_HOTPLUG_CPU
194 if (smp_ops.cpu_kill)
195 return 1;
196#endif
197
198 return 0;
199}
200
a054a811 201#ifdef CONFIG_HOTPLUG_CPU
ac6c7998 202static int platform_cpu_kill(unsigned int cpu)
abcee5fb
MZ
203{
204 if (smp_ops.cpu_kill)
205 return smp_ops.cpu_kill(cpu);
206 return 1;
207}
208
ac6c7998 209static int platform_cpu_disable(unsigned int cpu)
abcee5fb
MZ
210{
211 if (smp_ops.cpu_disable)
212 return smp_ops.cpu_disable(cpu);
213
787047ee
SB
214 return 0;
215}
216
217int platform_can_hotplug_cpu(unsigned int cpu)
218{
219 /* cpu_die must be specified to support hotplug */
220 if (!smp_ops.cpu_die)
221 return 0;
222
223 if (smp_ops.cpu_can_disable)
224 return smp_ops.cpu_can_disable(cpu);
225
abcee5fb
MZ
226 /*
227 * By default, allow disabling all CPUs except the first one,
228 * since this is special on a lot of platforms, e.g. because
229 * of clock tick interrupts.
230 */
787047ee 231 return cpu != 0;
abcee5fb 232}
787047ee 233
a054a811
RK
234/*
235 * __cpu_disable runs on the processor to be shutdown.
236 */
8bd26e3a 237int __cpu_disable(void)
a054a811
RK
238{
239 unsigned int cpu = smp_processor_id();
a054a811
RK
240 int ret;
241
8e2a43f5 242 ret = platform_cpu_disable(cpu);
a054a811
RK
243 if (ret)
244 return ret;
245
246 /*
247 * Take this CPU offline. Once we clear this, we can't return,
248 * and we must not schedule until we're ready to give up the cpu.
249 */
e03cdade 250 set_cpu_online(cpu, false);
a054a811
RK
251
252 /*
253 * OK - migrate IRQs away from this CPU
254 */
1b5ba350 255 irq_migrate_all_off_this_cpu();
a054a811
RK
256
257 /*
258 * Flush user cache and TLB mappings, and then remove this CPU
259 * from the vm mask set of all processes.
e6b866e9
LP
260 *
261 * Caches are flushed to the Level of Unification Inner Shareable
262 * to write-back dirty lines to unified caches shared by all CPUs.
a054a811 263 */
e6b866e9 264 flush_cache_louis();
a054a811
RK
265 local_flush_tlb_all();
266
a054a811
RK
267 return 0;
268}
269
3c030bea
RK
270static DECLARE_COMPLETION(cpu_died);
271
a054a811
RK
272/*
273 * called on the thread which is asking for a CPU to be shutdown -
274 * waits until shutdown has completed, or it is timed out.
275 */
8bd26e3a 276void __cpu_die(unsigned int cpu)
a054a811 277{
3c030bea
RK
278 if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
279 pr_err("CPU%u: cpu didn't die\n", cpu);
280 return;
281 }
035e7875 282 pr_debug("CPU%u: shutdown\n", cpu);
3c030bea 283
98f1b5a7 284 clear_tasks_mm_cpumask(cpu);
51acdfd1
RK
285 /*
286 * platform_cpu_kill() is generally expected to do the powering off
287 * and/or cutting of clocks to the dying CPU. Optionally, this may
288 * be done by the CPU which is dying in preference to supporting
289 * this call, but that means there is _no_ synchronisation between
290 * the requesting CPU and the dying CPU actually losing power.
291 */
a054a811 292 if (!platform_cpu_kill(cpu))
4ed89f22 293 pr_err("CPU%u: unable to kill\n", cpu);
a054a811
RK
294}
295
296/*
297 * Called from the idle thread for the CPU which has been shutdown.
298 *
299 * Note that we disable IRQs here, but do not re-enable them
300 * before returning to the caller. This is also the behaviour
301 * of the other hotplug-cpu capable cores, so presumably coming
302 * out of idle fixes this.
303 */
9205b797 304void arch_cpu_idle_dead(void)
a054a811
RK
305{
306 unsigned int cpu = smp_processor_id();
307
a054a811
RK
308 idle_task_exit();
309
f36d3401 310 local_irq_disable();
f36d3401 311
51acdfd1
RK
312 /*
313 * Flush the data out of the L1 cache for this CPU. This must be
314 * before the completion to ensure that data is safely written out
315 * before platform_cpu_kill() gets called - which may disable
316 * *this* CPU and power down its cache.
317 */
318 flush_cache_louis();
319
320 /*
321 * Tell __cpu_die() that this CPU is now safe to dispose of. Once
322 * this returns, power and/or clocks can be removed at any point
323 * from this CPU and its cache by platform_cpu_kill().
324 */
aa033810 325 complete(&cpu_died);
3c030bea 326
a054a811 327 /*
51acdfd1
RK
328 * Ensure that the cache lines associated with that completion are
329 * written out. This covers the case where _this_ CPU is doing the
330 * powering down, to ensure that the completion is visible to the
331 * CPU waiting for this one.
332 */
333 flush_cache_louis();
334
335 /*
336 * The actual CPU shutdown procedure is at least platform (if not
337 * CPU) specific. This may remove power, or it may simply spin.
338 *
339 * Platforms are generally expected *NOT* to return from this call,
340 * although there are some which do because they have no way to
341 * power down the CPU. These platforms are the _only_ reason we
342 * have a return path which uses the fragment of assembly below.
343 *
344 * The return path should not be used for platforms which can
345 * power off the CPU.
a054a811 346 */
0a301110
RK
347 if (smp_ops.cpu_die)
348 smp_ops.cpu_die(cpu);
a054a811 349
668bc386
RK
350 pr_warn("CPU%u: smp_ops.cpu_die() returned, trying to resuscitate\n",
351 cpu);
352
a054a811
RK
353 /*
354 * Do not return to the idle loop - jump back to the secondary
355 * cpu initialisation. There's some initialisation which needs
356 * to be repeated to undo the effects of taking the CPU offline.
357 */
358 __asm__("mov sp, %0\n"
faabfa08 359 " mov fp, #0\n"
a054a811
RK
360 " b secondary_start_kernel"
361 :
32d39a93 362 : "r" (task_stack_page(current) + THREAD_SIZE - 8));
a054a811
RK
363}
364#endif /* CONFIG_HOTPLUG_CPU */
365
05c74a6c
RK
366/*
367 * Called by both boot and secondaries to move global data into
368 * per-processor storage.
369 */
8bd26e3a 370static void smp_store_cpu_info(unsigned int cpuid)
05c74a6c
RK
371{
372 struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid);
373
374 cpu_info->loops_per_jiffy = loops_per_jiffy;
e8d432c9 375 cpu_info->cpuid = read_cpuid_id();
c9018aab
VG
376
377 store_cpu_topology(cpuid);
05c74a6c
RK
378}
379
e65f38ed
RK
380/*
381 * This is the secondary CPU boot entry. We're using this CPUs
382 * idle thread stack, but a set of temporary page tables.
383 */
8bd26e3a 384asmlinkage void secondary_start_kernel(void)
e65f38ed
RK
385{
386 struct mm_struct *mm = &init_mm;
5f40b909
WD
387 unsigned int cpu;
388
383fb3ee
RK
389 secondary_biglittle_init();
390
5f40b909
WD
391 /*
392 * The identity mapping is uncached (strongly ordered), so
393 * switch away from it before attempting any exclusive accesses.
394 */
395 cpu_switch_mm(mm->pgd, mm);
89c7e4b8 396 local_flush_bp_all();
5f40b909
WD
397 enter_lazy_tlb(mm, current);
398 local_flush_tlb_all();
e65f38ed 399
e65f38ed
RK
400 /*
401 * All kernel threads share the same mm context; grab a
402 * reference and switch to it.
403 */
5f40b909 404 cpu = smp_processor_id();
f1f10076 405 mmgrab(mm);
e65f38ed 406 current->active_mm = mm;
56f8ba83 407 cpumask_set_cpu(cpu, mm_cpumask(mm));
e65f38ed 408
14318efb
RH
409 cpu_init();
410
62d1c95d
VM
411#ifndef CONFIG_MMU
412 setup_vectors_base();
413#endif
c68b0274 414 pr_debug("CPU%u: Booted secondary processor\n", cpu);
fde165b2 415
5bfb5d69 416 preempt_disable();
2c0136db 417 trace_hardirqs_off();
e65f38ed
RK
418
419 /*
420 * Give the platform a chance to do its own initialisation.
421 */
0a301110
RK
422 if (smp_ops.smp_secondary_init)
423 smp_ops.smp_secondary_init(cpu);
e65f38ed 424
e545a614 425 notify_cpu_starting(cpu);
a8655e83 426
e65f38ed
RK
427 calibrate_delay();
428
429 smp_store_cpu_info(cpu);
430
431 /*
573619d1
RK
432 * OK, now it's safe to let the boot CPU continue. Wait for
433 * the CPU migration code to notice that the CPU is online
149c2415 434 * before we continue - which happens after __cpu_up returns.
e65f38ed 435 */
e03cdade 436 set_cpu_online(cpu, true);
26602161
RK
437
438 check_other_bugs();
439
149c2415 440 complete(&cpu_running);
eb047454 441
eb047454
TG
442 local_irq_enable();
443 local_fiq_enable();
bbeb9209 444 local_abt_enable();
eb047454 445
e65f38ed
RK
446 /*
447 * OK, it's off to the idle thread for us
448 */
fc6d73d6 449 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
e65f38ed
RK
450}
451
1da177e4
LT
452void __init smp_cpus_done(unsigned int max_cpus)
453{
4bf9636c
PM
454 int cpu;
455 unsigned long bogosum = 0;
456
457 for_each_online_cpu(cpu)
458 bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy;
459
460 printk(KERN_INFO "SMP: Total of %d processors activated "
461 "(%lu.%02lu BogoMIPS).\n",
462 num_online_cpus(),
463 bogosum / (500000/HZ),
464 (bogosum / (5000/HZ)) % 100);
465
4588c34d 466 hyp_mode_check();
1da177e4
LT
467}
468
469void __init smp_prepare_boot_cpu(void)
470{
14318efb 471 set_my_cpu_offset(per_cpu_offset(smp_processor_id()));
1da177e4
LT
472}
473
05c74a6c 474void __init smp_prepare_cpus(unsigned int max_cpus)
1da177e4 475{
05c74a6c 476 unsigned int ncores = num_possible_cpus();
1da177e4 477
c9018aab
VG
478 init_cpu_topology();
479
05c74a6c 480 smp_store_cpu_info(smp_processor_id());
1da177e4
LT
481
482 /*
05c74a6c 483 * are we trying to boot more cores than exist?
1da177e4 484 */
05c74a6c
RK
485 if (max_cpus > ncores)
486 max_cpus = ncores;
7fa22bd5 487 if (ncores > 1 && max_cpus) {
7fa22bd5
SB
488 /*
489 * Initialise the present map, which describes the set of CPUs
490 * actually populated at the present time. A platform should
0a301110
RK
491 * re-initialize the map in the platforms smp_prepare_cpus()
492 * if present != possible (e.g. physical hotplug).
7fa22bd5 493 */
0b5f9c00 494 init_cpu_present(cpu_possible_mask);
7fa22bd5 495
05c74a6c
RK
496 /*
497 * Initialise the SCU if there are more than one CPU
498 * and let them know where to start.
499 */
0a301110
RK
500 if (smp_ops.smp_prepare_cpus)
501 smp_ops.smp_prepare_cpus(max_cpus);
05c74a6c 502 }
1da177e4
LT
503}
504
365ec7b1 505static void (*__smp_cross_call)(const struct cpumask *, unsigned int);
0f7b332f
RK
506
507void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
508{
365ec7b1
NP
509 if (!__smp_cross_call)
510 __smp_cross_call = fn;
3e459990 511}
3e459990 512
365ec7b1 513static const char *ipi_types[NR_IPI] __tracepoint_string = {
559a5939
SB
514#define S(x,s) [x] = s
515 S(IPI_WAKEUP, "CPU wakeup interrupts"),
4a88abd7
RK
516 S(IPI_TIMER, "Timer broadcast interrupts"),
517 S(IPI_RESCHEDULE, "Rescheduling interrupts"),
518 S(IPI_CALL_FUNC, "Function call interrupts"),
4a88abd7 519 S(IPI_CPU_STOP, "CPU stop interrupts"),
bf18525f 520 S(IPI_IRQ_WORK, "IRQ work interrupts"),
5135d875 521 S(IPI_COMPLETION, "completion interrupts"),
4a88abd7
RK
522};
523
365ec7b1
NP
524static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
525{
7c64cc05 526 trace_ipi_raise_rcuidle(target, ipi_types[ipinr]);
365ec7b1
NP
527 __smp_cross_call(target, ipinr);
528}
529
f13cd417 530void show_ipi_list(struct seq_file *p, int prec)
1da177e4 531{
4a88abd7 532 unsigned int cpu, i;
1da177e4 533
4a88abd7
RK
534 for (i = 0; i < NR_IPI; i++) {
535 seq_printf(p, "%*s%u: ", prec - 1, "IPI", i);
1da177e4 536
026b7c6b 537 for_each_online_cpu(cpu)
4a88abd7
RK
538 seq_printf(p, "%10u ",
539 __get_irq_stat(cpu, ipi_irqs[i]));
1da177e4 540
4a88abd7
RK
541 seq_printf(p, " %s\n", ipi_types[i]);
542 }
1da177e4
LT
543}
544
b54992fe 545u64 smp_irq_stat_cpu(unsigned int cpu)
37ee16ae 546{
b54992fe
RK
547 u64 sum = 0;
548 int i;
37ee16ae 549
b54992fe
RK
550 for (i = 0; i < NR_IPI; i++)
551 sum += __get_irq_stat(cpu, ipi_irqs[i]);
37ee16ae 552
b54992fe 553 return sum;
37ee16ae
RK
554}
555
365ec7b1
NP
556void arch_send_call_function_ipi_mask(const struct cpumask *mask)
557{
558 smp_cross_call(mask, IPI_CALL_FUNC);
559}
560
561void arch_send_wakeup_ipi_mask(const struct cpumask *mask)
562{
563 smp_cross_call(mask, IPI_WAKEUP);
564}
565
566void arch_send_call_function_single_ipi(int cpu)
567{
89d798b7 568 smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC);
365ec7b1
NP
569}
570
571#ifdef CONFIG_IRQ_WORK
572void arch_irq_work_raise(void)
573{
09f6edd4 574 if (arch_irq_work_has_interrupt())
365ec7b1
NP
575 smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK);
576}
577#endif
578
bc28248e 579#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
3d06770e 580void tick_broadcast(const struct cpumask *mask)
bc28248e 581{
e3fbb087 582 smp_cross_call(mask, IPI_TIMER);
bc28248e 583}
5388a6b2 584#endif
bc28248e 585
bd31b859 586static DEFINE_RAW_SPINLOCK(stop_lock);
1da177e4
LT
587
588/*
589 * ipi_cpu_stop - handle IPI from smp_send_stop()
590 */
591static void ipi_cpu_stop(unsigned int cpu)
592{
5976a669 593 if (system_state <= SYSTEM_RUNNING) {
bd31b859 594 raw_spin_lock(&stop_lock);
4ed89f22 595 pr_crit("CPU%u: stopping\n", cpu);
3d3f78d7 596 dump_stack();
bd31b859 597 raw_spin_unlock(&stop_lock);
3d3f78d7 598 }
1da177e4 599
e03cdade 600 set_cpu_online(cpu, false);
1da177e4
LT
601
602 local_fiq_disable();
603 local_irq_disable();
604
5388a5b8 605 while (1) {
1da177e4 606 cpu_relax();
5388a5b8
RK
607 wfe();
608 }
1da177e4
LT
609}
610
5135d875
NP
611static DEFINE_PER_CPU(struct completion *, cpu_completion);
612
613int register_ipi_completion(struct completion *completion, int cpu)
614{
615 per_cpu(cpu_completion, cpu) = completion;
616 return IPI_COMPLETION;
617}
618
619static void ipi_complete(unsigned int cpu)
620{
621 complete(per_cpu(cpu_completion, cpu));
622}
623
1da177e4
LT
624/*
625 * Main handler for inter-processor interrupts
1da177e4 626 */
4073723a 627asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs)
0b5a1b95
SG
628{
629 handle_IPI(ipinr, regs);
630}
631
632void handle_IPI(int ipinr, struct pt_regs *regs)
1da177e4
LT
633{
634 unsigned int cpu = smp_processor_id();
c97d4869 635 struct pt_regs *old_regs = set_irq_regs(regs);
1da177e4 636
365ec7b1 637 if ((unsigned)ipinr < NR_IPI) {
398f7456 638 trace_ipi_entry_rcuidle(ipi_types[ipinr]);
559a5939 639 __inc_irq_stat(cpu, ipi_irqs[ipinr]);
365ec7b1 640 }
1da177e4 641
24480d98 642 switch (ipinr) {
559a5939
SB
643 case IPI_WAKEUP:
644 break;
645
e2c50119 646#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
24480d98 647 case IPI_TIMER:
7deabca0 648 irq_enter();
e2c50119 649 tick_receive_broadcast();
7deabca0 650 irq_exit();
24480d98 651 break;
e2c50119 652#endif
1da177e4 653
24480d98 654 case IPI_RESCHEDULE:
184748cc 655 scheduler_ipi();
24480d98 656 break;
1da177e4 657
24480d98 658 case IPI_CALL_FUNC:
7deabca0 659 irq_enter();
24480d98 660 generic_smp_call_function_interrupt();
7deabca0 661 irq_exit();
24480d98 662 break;
1da177e4 663
24480d98 664 case IPI_CPU_STOP:
7deabca0 665 irq_enter();
24480d98 666 ipi_cpu_stop(cpu);
7deabca0 667 irq_exit();
24480d98 668 break;
1da177e4 669
bf18525f
SB
670#ifdef CONFIG_IRQ_WORK
671 case IPI_IRQ_WORK:
672 irq_enter();
673 irq_work_run();
674 irq_exit();
675 break;
676#endif
677
5135d875
NP
678 case IPI_COMPLETION:
679 irq_enter();
680 ipi_complete(cpu);
681 irq_exit();
682 break;
683
96f0e003 684 case IPI_CPU_BACKTRACE:
42a0bb3f 685 printk_nmi_enter();
96f0e003
RK
686 irq_enter();
687 nmi_cpu_backtrace(regs);
688 irq_exit();
42a0bb3f 689 printk_nmi_exit();
96f0e003
RK
690 break;
691
24480d98 692 default:
4ed89f22
RK
693 pr_crit("CPU%u: Unknown IPI message 0x%x\n",
694 cpu, ipinr);
24480d98 695 break;
1da177e4 696 }
365ec7b1
NP
697
698 if ((unsigned)ipinr < NR_IPI)
398f7456 699 trace_ipi_exit_rcuidle(ipi_types[ipinr]);
c97d4869 700 set_irq_regs(old_regs);
1da177e4
LT
701}
702
703void smp_send_reschedule(int cpu)
704{
e3fbb087 705 smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
1da177e4
LT
706}
707
1da177e4
LT
708void smp_send_stop(void)
709{
28e18293 710 unsigned long timeout;
6fa99b7f 711 struct cpumask mask;
1da177e4 712
6fa99b7f
WD
713 cpumask_copy(&mask, cpu_online_mask);
714 cpumask_clear_cpu(smp_processor_id(), &mask);
c5dff4ff
JMC
715 if (!cpumask_empty(&mask))
716 smp_cross_call(&mask, IPI_CPU_STOP);
4b0ef3b1 717
28e18293
RK
718 /* Wait up to one second for other CPUs to stop */
719 timeout = USEC_PER_SEC;
720 while (num_online_cpus() > 1 && timeout--)
721 udelay(1);
4b0ef3b1 722
28e18293 723 if (num_online_cpus() > 1)
8b521cb2 724 pr_warn("SMP: failed to stop secondary CPUs\n");
4b0ef3b1
RK
725}
726
82c08c3e
YW
727/* In case panic() and panic() called at the same time on CPU1 and CPU2,
728 * and CPU 1 calls panic_smp_self_stop() before crash_smp_send_stop()
729 * CPU1 can't receive the ipi irqs from CPU2, CPU1 will be always online,
730 * kdump fails. So split out the panic_smp_self_stop() and add
731 * set_cpu_online(smp_processor_id(), false).
732 */
733void panic_smp_self_stop(void)
734{
735 pr_debug("CPU %u will stop doing anything useful since another CPU has paniced\n",
736 smp_processor_id());
737 set_cpu_online(smp_processor_id(), false);
738 while (1)
739 cpu_relax();
740}
741
4b0ef3b1 742/*
1da177e4 743 * not supported here
4b0ef3b1 744 */
5048bcba 745int setup_profiling_timer(unsigned int multiplier)
4b0ef3b1 746{
1da177e4 747 return -EINVAL;
4b0ef3b1 748}
ec971ea5
RZ
749
750#ifdef CONFIG_CPU_FREQ
751
752static DEFINE_PER_CPU(unsigned long, l_p_j_ref);
753static DEFINE_PER_CPU(unsigned long, l_p_j_ref_freq);
754static unsigned long global_l_p_j_ref;
755static unsigned long global_l_p_j_ref_freq;
756
757static int cpufreq_callback(struct notifier_block *nb,
758 unsigned long val, void *data)
759{
760 struct cpufreq_freqs *freq = data;
df24014a
VK
761 struct cpumask *cpus = freq->policy->cpus;
762 int cpu, first = cpumask_first(cpus);
763 unsigned int lpj;
ec971ea5
RZ
764
765 if (freq->flags & CPUFREQ_CONST_LOOPS)
766 return NOTIFY_OK;
767
df24014a
VK
768 if (!per_cpu(l_p_j_ref, first)) {
769 for_each_cpu(cpu, cpus) {
770 per_cpu(l_p_j_ref, cpu) =
771 per_cpu(cpu_data, cpu).loops_per_jiffy;
772 per_cpu(l_p_j_ref_freq, cpu) = freq->old;
773 }
774
ec971ea5
RZ
775 if (!global_l_p_j_ref) {
776 global_l_p_j_ref = loops_per_jiffy;
777 global_l_p_j_ref_freq = freq->old;
778 }
779 }
780
781 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
0b443ead 782 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
ec971ea5
RZ
783 loops_per_jiffy = cpufreq_scale(global_l_p_j_ref,
784 global_l_p_j_ref_freq,
785 freq->new);
df24014a
VK
786
787 lpj = cpufreq_scale(per_cpu(l_p_j_ref, first),
788 per_cpu(l_p_j_ref_freq, first), freq->new);
789 for_each_cpu(cpu, cpus)
790 per_cpu(cpu_data, cpu).loops_per_jiffy = lpj;
ec971ea5
RZ
791 }
792 return NOTIFY_OK;
793}
794
795static struct notifier_block cpufreq_notifier = {
796 .notifier_call = cpufreq_callback,
797};
798
799static int __init register_cpufreq_notifier(void)
800{
801 return cpufreq_register_notifier(&cpufreq_notifier,
802 CPUFREQ_TRANSITION_NOTIFIER);
803}
804core_initcall(register_cpufreq_notifier);
805
806#endif
96f0e003
RK
807
808static void raise_nmi(cpumask_t *mask)
809{
be167862 810 __smp_cross_call(mask, IPI_CPU_BACKTRACE);
96f0e003
RK
811}
812
9a01c3ed 813void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
96f0e003 814{
9a01c3ed 815 nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_nmi);
96f0e003 816}