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f32f4ce2 RK |
1 | /* |
2 | * linux/arch/arm/kernel/smp_twd.c | |
3 | * | |
4 | * Copyright (C) 2002 ARM Ltd. | |
5 | * All Rights Reserved | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/kernel.h> | |
5def51b0 | 13 | #include <linux/clk.h> |
a894fcc2 | 14 | #include <linux/cpu.h> |
f32f4ce2 RK |
15 | #include <linux/delay.h> |
16 | #include <linux/device.h> | |
5def51b0 | 17 | #include <linux/err.h> |
f32f4ce2 RK |
18 | #include <linux/smp.h> |
19 | #include <linux/jiffies.h> | |
20 | #include <linux/clockchips.h> | |
92485104 | 21 | #include <linux/interrupt.h> |
f32f4ce2 | 22 | #include <linux/io.h> |
d8e03643 MZ |
23 | #include <linux/of_irq.h> |
24 | #include <linux/of_address.h> | |
f32f4ce2 RK |
25 | |
26 | #include <asm/smp_twd.h> | |
f32f4ce2 | 27 | |
f32f4ce2 | 28 | /* set up by the platform code */ |
92485104 | 29 | static void __iomem *twd_base; |
f32f4ce2 | 30 | |
5def51b0 | 31 | static struct clk *twd_clk; |
f32f4ce2 | 32 | static unsigned long twd_timer_rate; |
a68becd1 | 33 | static DEFINE_PER_CPU(bool, percpu_setup_called); |
f32f4ce2 | 34 | |
a894fcc2 | 35 | static struct clock_event_device __percpu *twd_evt; |
e1b8c05d RK |
36 | static unsigned int twd_features = |
37 | CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; | |
81e46f7b | 38 | static int twd_ppi; |
28af690a | 39 | |
5e253571 | 40 | static int twd_shutdown(struct clock_event_device *clk) |
f32f4ce2 | 41 | { |
5e253571 VK |
42 | writel_relaxed(0, twd_base + TWD_TIMER_CONTROL); |
43 | return 0; | |
44 | } | |
f32f4ce2 | 45 | |
5e253571 VK |
46 | static int twd_set_oneshot(struct clock_event_device *clk) |
47 | { | |
48 | /* period set, and timer enabled in 'next_event' hook */ | |
49 | writel_relaxed(TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT, | |
50 | twd_base + TWD_TIMER_CONTROL); | |
51 | return 0; | |
52 | } | |
53 | ||
54 | static int twd_set_periodic(struct clock_event_device *clk) | |
55 | { | |
56 | unsigned long ctrl = TWD_TIMER_CONTROL_ENABLE | | |
57 | TWD_TIMER_CONTROL_IT_ENABLE | | |
58 | TWD_TIMER_CONTROL_PERIODIC; | |
59 | ||
60 | writel_relaxed(DIV_ROUND_CLOSEST(twd_timer_rate, HZ), | |
61 | twd_base + TWD_TIMER_LOAD); | |
2e874ea3 | 62 | writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL); |
5e253571 | 63 | return 0; |
f32f4ce2 RK |
64 | } |
65 | ||
66 | static int twd_set_next_event(unsigned long evt, | |
67 | struct clock_event_device *unused) | |
68 | { | |
2e874ea3 | 69 | unsigned long ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL); |
f32f4ce2 | 70 | |
4c5158d4 RK |
71 | ctrl |= TWD_TIMER_CONTROL_ENABLE; |
72 | ||
2e874ea3 BD |
73 | writel_relaxed(evt, twd_base + TWD_TIMER_COUNTER); |
74 | writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL); | |
f32f4ce2 RK |
75 | |
76 | return 0; | |
77 | } | |
78 | ||
79 | /* | |
80 | * local_timer_ack: checks for a local timer interrupt. | |
81 | * | |
82 | * If a local timer interrupt has occurred, acknowledge and return 1. | |
83 | * Otherwise, return 0. | |
84 | */ | |
92485104 | 85 | static int twd_timer_ack(void) |
f32f4ce2 | 86 | { |
2e874ea3 BD |
87 | if (readl_relaxed(twd_base + TWD_TIMER_INTSTAT)) { |
88 | writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT); | |
f32f4ce2 RK |
89 | return 1; |
90 | } | |
91 | ||
92 | return 0; | |
93 | } | |
94 | ||
a894fcc2 | 95 | static void twd_timer_stop(void) |
28af690a | 96 | { |
06b96c8b | 97 | struct clock_event_device *clk = raw_cpu_ptr(twd_evt); |
a894fcc2 | 98 | |
5e253571 | 99 | twd_shutdown(clk); |
28af690a MZ |
100 | disable_percpu_irq(clk->irq); |
101 | } | |
102 | ||
2b25d9f6 MT |
103 | #ifdef CONFIG_COMMON_CLK |
104 | ||
105 | /* | |
106 | * Updates clockevent frequency when the cpu frequency changes. | |
107 | * Called on the cpu that is changing frequency with interrupts disabled. | |
108 | */ | |
109 | static void twd_update_frequency(void *new_rate) | |
110 | { | |
111 | twd_timer_rate = *((unsigned long *) new_rate); | |
112 | ||
06b96c8b | 113 | clockevents_update_freq(raw_cpu_ptr(twd_evt), twd_timer_rate); |
2b25d9f6 MT |
114 | } |
115 | ||
116 | static int twd_rate_change(struct notifier_block *nb, | |
117 | unsigned long flags, void *data) | |
118 | { | |
119 | struct clk_notifier_data *cnd = data; | |
120 | ||
121 | /* | |
122 | * The twd clock events must be reprogrammed to account for the new | |
123 | * frequency. The timer is local to a cpu, so cross-call to the | |
124 | * changing cpu. | |
125 | */ | |
126 | if (flags == POST_RATE_CHANGE) | |
cbbe6f82 | 127 | on_each_cpu(twd_update_frequency, |
2b25d9f6 MT |
128 | (void *)&cnd->new_rate, 1); |
129 | ||
130 | return NOTIFY_OK; | |
131 | } | |
132 | ||
133 | static struct notifier_block twd_clk_nb = { | |
134 | .notifier_call = twd_rate_change, | |
135 | }; | |
136 | ||
137 | static int twd_clk_init(void) | |
138 | { | |
06b96c8b | 139 | if (twd_evt && raw_cpu_ptr(twd_evt) && !IS_ERR(twd_clk)) |
2b25d9f6 MT |
140 | return clk_notifier_register(twd_clk, &twd_clk_nb); |
141 | ||
142 | return 0; | |
143 | } | |
144 | core_initcall(twd_clk_init); | |
145 | ||
146 | #elif defined (CONFIG_CPU_FREQ) | |
147 | ||
148 | #include <linux/cpufreq.h> | |
4fd7f9b1 LW |
149 | |
150 | /* | |
151 | * Updates clockevent frequency when the cpu frequency changes. | |
152 | * Called on the cpu that is changing frequency with interrupts disabled. | |
153 | */ | |
154 | static void twd_update_frequency(void *data) | |
155 | { | |
156 | twd_timer_rate = clk_get_rate(twd_clk); | |
157 | ||
06b96c8b | 158 | clockevents_update_freq(raw_cpu_ptr(twd_evt), twd_timer_rate); |
4fd7f9b1 LW |
159 | } |
160 | ||
161 | static int twd_cpufreq_transition(struct notifier_block *nb, | |
162 | unsigned long state, void *data) | |
163 | { | |
164 | struct cpufreq_freqs *freqs = data; | |
165 | ||
166 | /* | |
167 | * The twd clock events must be reprogrammed to account for the new | |
168 | * frequency. The timer is local to a cpu, so cross-call to the | |
169 | * changing cpu. | |
170 | */ | |
0b443ead | 171 | if (state == CPUFREQ_POSTCHANGE) |
4fd7f9b1 | 172 | smp_call_function_single(freqs->cpu, twd_update_frequency, |
3cd88f99 | 173 | NULL, 1); |
4fd7f9b1 LW |
174 | |
175 | return NOTIFY_OK; | |
176 | } | |
177 | ||
178 | static struct notifier_block twd_cpufreq_nb = { | |
179 | .notifier_call = twd_cpufreq_transition, | |
180 | }; | |
181 | ||
182 | static int twd_cpufreq_init(void) | |
183 | { | |
06b96c8b | 184 | if (twd_evt && raw_cpu_ptr(twd_evt) && !IS_ERR(twd_clk)) |
4fd7f9b1 LW |
185 | return cpufreq_register_notifier(&twd_cpufreq_nb, |
186 | CPUFREQ_TRANSITION_NOTIFIER); | |
187 | ||
188 | return 0; | |
189 | } | |
190 | core_initcall(twd_cpufreq_init); | |
191 | ||
192 | #endif | |
193 | ||
8bd26e3a | 194 | static void twd_calibrate_rate(void) |
f32f4ce2 | 195 | { |
03399c1c | 196 | unsigned long count; |
f32f4ce2 RK |
197 | u64 waitjiffies; |
198 | ||
199 | /* | |
200 | * If this is the first time round, we need to work out how fast | |
201 | * the timer ticks | |
202 | */ | |
203 | if (twd_timer_rate == 0) { | |
4ed89f22 | 204 | pr_info("Calibrating local timer... "); |
f32f4ce2 RK |
205 | |
206 | /* Wait for a tick to start */ | |
207 | waitjiffies = get_jiffies_64() + 1; | |
208 | ||
209 | while (get_jiffies_64() < waitjiffies) | |
210 | udelay(10); | |
211 | ||
212 | /* OK, now the tick has started, let's get the timer going */ | |
213 | waitjiffies += 5; | |
214 | ||
215 | /* enable, no interrupt or reload */ | |
2e874ea3 | 216 | writel_relaxed(0x1, twd_base + TWD_TIMER_CONTROL); |
f32f4ce2 RK |
217 | |
218 | /* maximum value */ | |
2e874ea3 | 219 | writel_relaxed(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER); |
f32f4ce2 RK |
220 | |
221 | while (get_jiffies_64() < waitjiffies) | |
222 | udelay(10); | |
223 | ||
2e874ea3 | 224 | count = readl_relaxed(twd_base + TWD_TIMER_COUNTER); |
f32f4ce2 RK |
225 | |
226 | twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5); | |
227 | ||
4ed89f22 | 228 | pr_cont("%lu.%02luMHz.\n", twd_timer_rate / 1000000, |
90c5ffe5 | 229 | (twd_timer_rate / 10000) % 100); |
f32f4ce2 | 230 | } |
f32f4ce2 RK |
231 | } |
232 | ||
28af690a MZ |
233 | static irqreturn_t twd_handler(int irq, void *dev_id) |
234 | { | |
a894fcc2 | 235 | struct clock_event_device *evt = dev_id; |
28af690a MZ |
236 | |
237 | if (twd_timer_ack()) { | |
238 | evt->event_handler(evt); | |
239 | return IRQ_HANDLED; | |
240 | } | |
241 | ||
242 | return IRQ_NONE; | |
243 | } | |
244 | ||
bd603455 | 245 | static void twd_get_clock(struct device_node *np) |
5def51b0 | 246 | { |
5def51b0 LW |
247 | int err; |
248 | ||
bd603455 RH |
249 | if (np) |
250 | twd_clk = of_clk_get(np, 0); | |
251 | else | |
252 | twd_clk = clk_get_sys("smp_twd", NULL); | |
253 | ||
254 | if (IS_ERR(twd_clk)) { | |
255 | pr_err("smp_twd: clock not found %d\n", (int) PTR_ERR(twd_clk)); | |
256 | return; | |
5def51b0 LW |
257 | } |
258 | ||
bd603455 | 259 | err = clk_prepare_enable(twd_clk); |
5def51b0 | 260 | if (err) { |
2577cf24 | 261 | pr_err("smp_twd: clock failed to prepare+enable: %d\n", err); |
bd603455 RH |
262 | clk_put(twd_clk); |
263 | return; | |
5def51b0 LW |
264 | } |
265 | ||
bd603455 | 266 | twd_timer_rate = clk_get_rate(twd_clk); |
5def51b0 LW |
267 | } |
268 | ||
f32f4ce2 RK |
269 | /* |
270 | * Setup the local clock events for a CPU. | |
271 | */ | |
47dcd356 | 272 | static void twd_timer_setup(void) |
f32f4ce2 | 273 | { |
06b96c8b | 274 | struct clock_event_device *clk = raw_cpu_ptr(twd_evt); |
a68becd1 | 275 | int cpu = smp_processor_id(); |
28af690a | 276 | |
a68becd1 LW |
277 | /* |
278 | * If the basic setup for this CPU has been done before don't | |
279 | * bother with the below. | |
280 | */ | |
281 | if (per_cpu(percpu_setup_called, cpu)) { | |
2e874ea3 | 282 | writel_relaxed(0, twd_base + TWD_TIMER_CONTROL); |
a894fcc2 | 283 | clockevents_register_device(clk); |
a68becd1 | 284 | enable_percpu_irq(clk->irq, 0); |
a894fcc2 | 285 | return; |
a68becd1 LW |
286 | } |
287 | per_cpu(percpu_setup_called, cpu) = true; | |
28af690a | 288 | |
bd603455 | 289 | twd_calibrate_rate(); |
f32f4ce2 | 290 | |
a68becd1 LW |
291 | /* |
292 | * The following is done once per CPU the first time .setup() is | |
293 | * called. | |
294 | */ | |
2e874ea3 | 295 | writel_relaxed(0, twd_base + TWD_TIMER_CONTROL); |
c214455f | 296 | |
4c5158d4 | 297 | clk->name = "local_timer"; |
e1b8c05d | 298 | clk->features = twd_features; |
4c5158d4 | 299 | clk->rating = 350; |
5e253571 VK |
300 | clk->set_state_shutdown = twd_shutdown; |
301 | clk->set_state_periodic = twd_set_periodic; | |
302 | clk->set_state_oneshot = twd_set_oneshot; | |
303 | clk->tick_resume = twd_shutdown; | |
4c5158d4 | 304 | clk->set_next_event = twd_set_next_event; |
92485104 | 305 | clk->irq = twd_ppi; |
a894fcc2 | 306 | clk->cpumask = cpumask_of(cpu); |
28af690a | 307 | |
54d15b1d LW |
308 | clockevents_config_and_register(clk, twd_timer_rate, |
309 | 0xf, 0xffffffff); | |
28af690a | 310 | enable_percpu_irq(clk->irq, 0); |
a894fcc2 | 311 | } |
81e46f7b | 312 | |
26b87688 | 313 | static int twd_timer_starting_cpu(unsigned int cpu) |
a894fcc2 | 314 | { |
26b87688 RC |
315 | twd_timer_setup(); |
316 | return 0; | |
81e46f7b MZ |
317 | } |
318 | ||
26b87688 RC |
319 | static int twd_timer_dying_cpu(unsigned int cpu) |
320 | { | |
321 | twd_timer_stop(); | |
322 | return 0; | |
323 | } | |
81e46f7b | 324 | |
bd603455 | 325 | static int __init twd_local_timer_common_register(struct device_node *np) |
81e46f7b MZ |
326 | { |
327 | int err; | |
328 | ||
a894fcc2 | 329 | twd_evt = alloc_percpu(struct clock_event_device); |
d8e03643 | 330 | if (!twd_evt) { |
81e46f7b | 331 | err = -ENOMEM; |
d8e03643 | 332 | goto out_free; |
81e46f7b MZ |
333 | } |
334 | ||
335 | err = request_percpu_irq(twd_ppi, twd_handler, "twd", twd_evt); | |
336 | if (err) { | |
337 | pr_err("twd: can't register interrupt %d (%d)\n", twd_ppi, err); | |
d8e03643 | 338 | goto out_free; |
81e46f7b MZ |
339 | } |
340 | ||
26b87688 | 341 | cpuhp_setup_state_nocalls(CPUHP_AP_ARM_TWD_STARTING, |
73c1b41e | 342 | "arm/timer/twd:starting", |
26b87688 | 343 | twd_timer_starting_cpu, twd_timer_dying_cpu); |
81e46f7b | 344 | |
bd603455 | 345 | twd_get_clock(np); |
194444c5 | 346 | if (!of_property_read_bool(np, "always-on")) |
e1b8c05d | 347 | twd_features |= CLOCK_EVT_FEAT_C3STOP; |
bd603455 | 348 | |
a894fcc2 SB |
349 | /* |
350 | * Immediately configure the timer on the boot CPU, unless we need | |
351 | * jiffies to be incrementing to calibrate the rate in which case | |
352 | * setup the timer in late_time_init. | |
353 | */ | |
354 | if (twd_timer_rate) | |
355 | twd_timer_setup(); | |
356 | else | |
357 | late_time_init = twd_timer_setup; | |
358 | ||
81e46f7b MZ |
359 | return 0; |
360 | ||
d8e03643 | 361 | out_free: |
81e46f7b | 362 | iounmap(twd_base); |
d8e03643 | 363 | twd_base = NULL; |
81e46f7b | 364 | free_percpu(twd_evt); |
d8e03643 | 365 | |
81e46f7b | 366 | return err; |
f32f4ce2 | 367 | } |
d8e03643 MZ |
368 | |
369 | int __init twd_local_timer_register(struct twd_local_timer *tlt) | |
370 | { | |
371 | if (twd_base || twd_evt) | |
372 | return -EBUSY; | |
373 | ||
374 | twd_ppi = tlt->res[1].start; | |
375 | ||
376 | twd_base = ioremap(tlt->res[0].start, resource_size(&tlt->res[0])); | |
377 | if (!twd_base) | |
378 | return -ENOMEM; | |
379 | ||
bd603455 | 380 | return twd_local_timer_common_register(NULL); |
d8e03643 MZ |
381 | } |
382 | ||
383 | #ifdef CONFIG_OF | |
dcbc0edd | 384 | static int __init twd_local_timer_of_register(struct device_node *np) |
d8e03643 | 385 | { |
d8e03643 MZ |
386 | int err; |
387 | ||
d8e03643 MZ |
388 | twd_ppi = irq_of_parse_and_map(np, 0); |
389 | if (!twd_ppi) { | |
390 | err = -EINVAL; | |
391 | goto out; | |
392 | } | |
393 | ||
394 | twd_base = of_iomap(np, 0); | |
395 | if (!twd_base) { | |
396 | err = -ENOMEM; | |
397 | goto out; | |
398 | } | |
399 | ||
bd603455 | 400 | err = twd_local_timer_common_register(np); |
d8e03643 MZ |
401 | |
402 | out: | |
403 | WARN(err, "twd_local_timer_of_register failed (%d)\n", err); | |
dcbc0edd | 404 | return err; |
d8e03643 | 405 | } |
17273395 DL |
406 | TIMER_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register); |
407 | TIMER_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register); | |
408 | TIMER_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register); | |
d8e03643 | 409 | #endif |