[mirror_ubuntu-hirsute-kernel.git] / arch / arm / kernel / smp_twd.c

/*
 *  linux/arch/arm/kernel/smp_twd.c
 *
 *  Copyright (C) 2002 ARM Ltd.
 *  All Rights Reserved
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/smp.h>
#include <linux/jiffies.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>

#include <asm/smp_twd.h>
#include <asm/localtimer.h>
#include <asm/hardware/gic.h>

/* set up by the platform code */
static void __iomem *twd_base;

static struct clk *twd_clk;
static unsigned long twd_timer_rate;

static struct clock_event_device __percpu **twd_evt;
static int twd_ppi;

static void twd_set_mode(enum clock_event_mode mode,
			struct clock_event_device *clk)
{
	unsigned long ctrl;

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		/* timer load already set up */
		ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
			| TWD_TIMER_CONTROL_PERIODIC;
		__raw_writel(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* period set, and timer enabled in 'next_event' hook */
		ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT;
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		ctrl = 0;
	}

	__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
}

static int twd_set_next_event(unsigned long evt,
			struct clock_event_device *unused)
{
	unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);

	ctrl |= TWD_TIMER_CONTROL_ENABLE;

	__raw_writel(evt, twd_base + TWD_TIMER_COUNTER);
	__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);

	return 0;
}

/*
 * local_timer_ack: checks for a local timer interrupt.
 *
 * If a local timer interrupt has occurred, acknowledge and return 1.
 * Otherwise, return 0.
 */
static int twd_timer_ack(void)
{
	if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) {
		__raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
		return 1;
	}

	return 0;
}

static void twd_timer_stop(struct clock_event_device *clk)
{
	twd_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
	disable_percpu_irq(clk->irq);
}

#ifdef CONFIG_CPU_FREQ

/*
 * Updates clockevent frequency when the cpu frequency changes.
 * Called on the cpu that is changing frequency with interrupts disabled.
 */
static void twd_update_frequency(void *data)
{
	twd_timer_rate = clk_get_rate(twd_clk);

	clockevents_update_freq(*__this_cpu_ptr(twd_evt), twd_timer_rate);
}

static int twd_cpufreq_transition(struct notifier_block *nb,
	unsigned long state, void *data)
{
	struct cpufreq_freqs *freqs = data;

	/*
	 * The twd clock events must be reprogrammed to account for the new
	 * frequency.  The timer is local to a cpu, so cross-call to the
	 * changing cpu.
	 *
	 * Only wait for it to finish, if the cpu is active to avoid
	 * deadlock when cpu1 is spinning on while(!cpu_active(cpu1)) during
	 * booting of that cpu.
	 */
	if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE)
		smp_call_function_single(freqs->cpu, twd_update_frequency,
					 NULL, cpu_active(freqs->cpu));

	return NOTIFY_OK;
}

static struct notifier_block twd_cpufreq_nb = {
	.notifier_call = twd_cpufreq_transition,
};

static int twd_cpufreq_init(void)
{
	if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
		return cpufreq_register_notifier(&twd_cpufreq_nb,
			CPUFREQ_TRANSITION_NOTIFIER);

	return 0;
}
core_initcall(twd_cpufreq_init);

#endif

static void __cpuinit twd_calibrate_rate(void)
{
	unsigned long count;
	u64 waitjiffies;

	/*
	 * If this is the first time round, we need to work out how fast
	 * the timer ticks
	 */
	if (twd_timer_rate == 0) {
		printk(KERN_INFO "Calibrating local timer... ");

		/* Wait for a tick to start */
		waitjiffies = get_jiffies_64() + 1;

		while (get_jiffies_64() < waitjiffies)
			udelay(10);

		/* OK, now the tick has started, let's get the timer going */
		waitjiffies += 5;

				 /* enable, no interrupt or reload */
		__raw_writel(0x1, twd_base + TWD_TIMER_CONTROL);

				 /* maximum value */
		__raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);

		while (get_jiffies_64() < waitjiffies)
			udelay(10);

		count = __raw_readl(twd_base + TWD_TIMER_COUNTER);

		twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);

		printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000,
			(twd_timer_rate / 10000) % 100);
	}
}

static irqreturn_t twd_handler(int irq, void *dev_id)
{
	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;

	if (twd_timer_ack()) {
		evt->event_handler(evt);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static struct clk *twd_get_clock(void)
{
	struct clk *clk;
	int err;

	clk = clk_get_sys("smp_twd", NULL);
	if (IS_ERR(clk)) {
		pr_err("smp_twd: clock not found: %d\n", (int)PTR_ERR(clk));
		return clk;
	}

	err = clk_prepare(clk);
	if (err) {
		pr_err("smp_twd: clock failed to prepare: %d\n", err);
		clk_put(clk);
		return ERR_PTR(err);
	}

	err = clk_enable(clk);
	if (err) {
		pr_err("smp_twd: clock failed to enable: %d\n", err);
		clk_unprepare(clk);
		clk_put(clk);
		return ERR_PTR(err);
	}

	return clk;
}

/*
 * Setup the local clock events for a CPU.
 */
static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
{
	struct clock_event_device **this_cpu_clk;

	if (!twd_clk)
		twd_clk = twd_get_clock();

	if (!IS_ERR_OR_NULL(twd_clk))
		twd_timer_rate = clk_get_rate(twd_clk);
	else
		twd_calibrate_rate();

	__raw_writel(0, twd_base + TWD_TIMER_CONTROL);

	clk->name = "local_timer";
	clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
			CLOCK_EVT_FEAT_C3STOP;
	clk->rating = 350;
	clk->set_mode = twd_set_mode;
	clk->set_next_event = twd_set_next_event;
	clk->irq = twd_ppi;

	this_cpu_clk = __this_cpu_ptr(twd_evt);
	*this_cpu_clk = clk;

	clockevents_config_and_register(clk, twd_timer_rate,
					0xf, 0xffffffff);
	enable_percpu_irq(clk->irq, 0);

	return 0;
}

static struct local_timer_ops twd_lt_ops __cpuinitdata = {
	.setup	= twd_timer_setup,
	.stop	= twd_timer_stop,
};

static int __init twd_local_timer_common_register(void)
{
	int err;

	twd_evt = alloc_percpu(struct clock_event_device *);
	if (!twd_evt) {
		err = -ENOMEM;
		goto out_free;
	}

	err = request_percpu_irq(twd_ppi, twd_handler, "twd", twd_evt);
	if (err) {
		pr_err("twd: can't register interrupt %d (%d)\n", twd_ppi, err);
		goto out_free;
	}

	err = local_timer_register(&twd_lt_ops);
	if (err)
		goto out_irq;

	return 0;

out_irq:
	free_percpu_irq(twd_ppi, twd_evt);
out_free:
	iounmap(twd_base);
	twd_base = NULL;
	free_percpu(twd_evt);

	return err;
}

int __init twd_local_timer_register(struct twd_local_timer *tlt)
{
	if (twd_base || twd_evt)
		return -EBUSY;

	twd_ppi	= tlt->res[1].start;

	twd_base = ioremap(tlt->res[0].start, resource_size(&tlt->res[0]));
	if (!twd_base)
		return -ENOMEM;

	return twd_local_timer_common_register();
}

#ifdef CONFIG_OF
const static struct of_device_id twd_of_match[] __initconst = {
	{ .compatible = "arm,cortex-a9-twd-timer",	},
	{ .compatible = "arm,cortex-a5-twd-timer",	},
	{ .compatible = "arm,arm11mp-twd-timer",	},
	{ },
};

void __init twd_local_timer_of_register(void)
{
	struct device_node *np;
	int err;

	np = of_find_matching_node(NULL, twd_of_match);
	if (!np) {
		err = -ENODEV;
		goto out;
	}

	twd_ppi = irq_of_parse_and_map(np, 0);
	if (!twd_ppi) {
		err = -EINVAL;
		goto out;
	}

	twd_base = of_iomap(np, 0);
	if (!twd_base) {
		err = -ENOMEM;
		goto out;
	}

	err = twd_local_timer_common_register();

out:
	WARN(err, "twd_local_timer_of_register failed (%d)\n", err);
}
#endif
Commit	Line	Data
f32f4ce2 RK	1	/*
	2	* linux/arch/arm/kernel/smp_twd.c
	3	*
	4	* Copyright (C) 2002 ARM Ltd.
	5	* All Rights Reserved
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#include <linux/init.h>
	12	#include <linux/kernel.h>
5def51b0	13	#include <linux/clk.h>
4fd7f9b1	14	#include <linux/cpufreq.h>
f32f4ce2 RK	15	#include <linux/delay.h>
f32f4ce2 RK	16	#include <linux/device.h>
5def51b0	17	#include <linux/err.h>
f32f4ce2 RK	18	#include <linux/smp.h>
	19	#include <linux/jiffies.h>
	20	#include <linux/clockchips.h>
92485104	21	#include <linux/interrupt.h>
f32f4ce2	22	#include <linux/io.h>
d8e03643 MZ	23	#include <linux/of_irq.h>
d8e03643 MZ	24	#include <linux/of_address.h>
f32f4ce2 RK	25
f32f4ce2 RK	26	#include <asm/smp_twd.h>
28af690a	27	#include <asm/localtimer.h>
f32f4ce2 RK	28	#include <asm/hardware/gic.h>
f32f4ce2 RK	29
f32f4ce2	30	/* set up by the platform code */
92485104	31	static void __iomem *twd_base;
f32f4ce2	32
5def51b0	33	static struct clk *twd_clk;
f32f4ce2 RK	34	static unsigned long twd_timer_rate;
f32f4ce2 RK	35
28af690a	36	static struct clock_event_device __percpu **twd_evt;
81e46f7b	37	static int twd_ppi;
28af690a	38
f32f4ce2 RK	39	static void twd_set_mode(enum clock_event_mode mode,
	40	struct clock_event_device *clk)
	41	{
	42	unsigned long ctrl;
	43
4c5158d4	44	switch (mode) {
f32f4ce2 RK	45	case CLOCK_EVT_MODE_PERIODIC:
	46	/* timer load already set up */
	47	ctrl = TWD_TIMER_CONTROL_ENABLE \| TWD_TIMER_CONTROL_IT_ENABLE
	48	\| TWD_TIMER_CONTROL_PERIODIC;
03399c1c	49	__raw_writel(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD);
f32f4ce2 RK	50	break;
	51	case CLOCK_EVT_MODE_ONESHOT:
	52	/* period set, and timer enabled in 'next_event' hook */
	53	ctrl = TWD_TIMER_CONTROL_IT_ENABLE \| TWD_TIMER_CONTROL_ONESHOT;
	54	break;
	55	case CLOCK_EVT_MODE_UNUSED:
	56	case CLOCK_EVT_MODE_SHUTDOWN:
	57	default:
	58	ctrl = 0;
	59	}
	60
	61	__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
	62	}
	63
	64	static int twd_set_next_event(unsigned long evt,
	65	struct clock_event_device *unused)
	66	{
	67	unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
	68
4c5158d4 RK	69	ctrl \|= TWD_TIMER_CONTROL_ENABLE;
4c5158d4 RK	70
f32f4ce2	71	__raw_writel(evt, twd_base + TWD_TIMER_COUNTER);
4c5158d4	72	__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
f32f4ce2 RK	73
	74	return 0;
	75	}
	76
	77	/*
	78	* local_timer_ack: checks for a local timer interrupt.
	79	*
	80	* If a local timer interrupt has occurred, acknowledge and return 1.
	81	* Otherwise, return 0.
	82	*/
92485104	83	static int twd_timer_ack(void)
f32f4ce2 RK	84	{
	85	if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) {
	86	__raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
	87	return 1;
	88	}
	89
	90	return 0;
	91	}
	92
abde710c	93	static void twd_timer_stop(struct clock_event_device *clk)
28af690a MZ	94	{
	95	twd_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
	96	disable_percpu_irq(clk->irq);
	97	}
	98
4fd7f9b1 LW	99	#ifdef CONFIG_CPU_FREQ
	100
	101	/*
	102	* Updates clockevent frequency when the cpu frequency changes.
	103	* Called on the cpu that is changing frequency with interrupts disabled.
	104	*/
	105	static void twd_update_frequency(void *data)
	106	{
	107	twd_timer_rate = clk_get_rate(twd_clk);
	108
	109	clockevents_update_freq(*__this_cpu_ptr(twd_evt), twd_timer_rate);
	110	}
	111
	112	static int twd_cpufreq_transition(struct notifier_block *nb,
	113	unsigned long state, void *data)
	114	{
	115	struct cpufreq_freqs *freqs = data;
	116
	117	/*
	118	* The twd clock events must be reprogrammed to account for the new
	119	* frequency. The timer is local to a cpu, so cross-call to the
	120	* changing cpu.
9f855503 LW	121	*
	122	* Only wait for it to finish, if the cpu is active to avoid
	123	* deadlock when cpu1 is spinning on while(!cpu_active(cpu1)) during
	124	* booting of that cpu.
4fd7f9b1 LW	125	*/
	126	if (state == CPUFREQ_POSTCHANGE \|\| state == CPUFREQ_RESUMECHANGE)
	127	smp_call_function_single(freqs->cpu, twd_update_frequency,
9f855503	128	NULL, cpu_active(freqs->cpu));
4fd7f9b1 LW	129
	130	return NOTIFY_OK;
	131	}
	132
	133	static struct notifier_block twd_cpufreq_nb = {
	134	.notifier_call = twd_cpufreq_transition,
	135	};
	136
	137	static int twd_cpufreq_init(void)
	138	{
910ba598	139	if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
4fd7f9b1 LW	140	return cpufreq_register_notifier(&twd_cpufreq_nb,
	141	CPUFREQ_TRANSITION_NOTIFIER);
	142
	143	return 0;
	144	}
	145	core_initcall(twd_cpufreq_init);
	146
	147	#endif
	148
f32f4ce2 RK	149	static void __cpuinit twd_calibrate_rate(void)
f32f4ce2 RK	150	{
03399c1c	151	unsigned long count;
f32f4ce2 RK	152	u64 waitjiffies;
	153
	154	/*
	155	* If this is the first time round, we need to work out how fast
	156	* the timer ticks
	157	*/
	158	if (twd_timer_rate == 0) {
4c5158d4	159	printk(KERN_INFO "Calibrating local timer... ");
f32f4ce2 RK	160
	161	/* Wait for a tick to start */
	162	waitjiffies = get_jiffies_64() + 1;
	163
	164	while (get_jiffies_64() < waitjiffies)
	165	udelay(10);
	166
	167	/* OK, now the tick has started, let's get the timer going */
	168	waitjiffies += 5;
	169
	170	/* enable, no interrupt or reload */
	171	__raw_writel(0x1, twd_base + TWD_TIMER_CONTROL);
	172
	173	/* maximum value */
	174	__raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
	175
	176	while (get_jiffies_64() < waitjiffies)
	177	udelay(10);
	178
	179	count = __raw_readl(twd_base + TWD_TIMER_COUNTER);
	180
	181	twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
	182
	183	printk("%lu.%02luMHz.\n", twd_timer_rate / 1000000,
90c5ffe5	184	(twd_timer_rate / 10000) % 100);
f32f4ce2	185	}
f32f4ce2 RK	186	}
f32f4ce2 RK	187
28af690a MZ	188	static irqreturn_t twd_handler(int irq, void *dev_id)
	189	{
	190	struct clock_event_device evt = (struct clock_event_device **)dev_id;
	191
	192	if (twd_timer_ack()) {
	193	evt->event_handler(evt);
	194	return IRQ_HANDLED;
	195	}
	196
	197	return IRQ_NONE;
	198	}
	199
5def51b0 LW	200	static struct clk *twd_get_clock(void)
	201	{
	202	struct clk *clk;
	203	int err;
	204
	205	clk = clk_get_sys("smp_twd", NULL);
	206	if (IS_ERR(clk)) {
	207	pr_err("smp_twd: clock not found: %d\n", (int)PTR_ERR(clk));
	208	return clk;
	209	}
	210
	211	err = clk_prepare(clk);
	212	if (err) {
	213	pr_err("smp_twd: clock failed to prepare: %d\n", err);
	214	clk_put(clk);
	215	return ERR_PTR(err);
	216	}
	217
	218	err = clk_enable(clk);
	219	if (err) {
	220	pr_err("smp_twd: clock failed to enable: %d\n", err);
	221	clk_unprepare(clk);
	222	clk_put(clk);
	223	return ERR_PTR(err);
	224	}
	225
	226	return clk;
	227	}
	228
f32f4ce2 RK	229	/*
	230	* Setup the local clock events for a CPU.
	231	*/
92485104	232	static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
f32f4ce2	233	{
28af690a MZ	234	struct clock_event_device **this_cpu_clk;
28af690a MZ	235
5def51b0 LW	236	if (!twd_clk)
	237	twd_clk = twd_get_clock();
	238
	239	if (!IS_ERR_OR_NULL(twd_clk))
	240	twd_timer_rate = clk_get_rate(twd_clk);
	241	else
	242	twd_calibrate_rate();
f32f4ce2	243
c214455f MZ	244	__raw_writel(0, twd_base + TWD_TIMER_CONTROL);
c214455f MZ	245
4c5158d4	246	clk->name = "local_timer";
5388a6b2 RK	247	clk->features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT \|
5388a6b2 RK	248	CLOCK_EVT_FEAT_C3STOP;
4c5158d4 RK	249	clk->rating = 350;
	250	clk->set_mode = twd_set_mode;
	251	clk->set_next_event = twd_set_next_event;
92485104	252	clk->irq = twd_ppi;
f32f4ce2	253
28af690a MZ	254	this_cpu_clk = __this_cpu_ptr(twd_evt);
	255	*this_cpu_clk = clk;
	256
54d15b1d LW	257	clockevents_config_and_register(clk, twd_timer_rate,
54d15b1d LW	258	0xf, 0xffffffff);
28af690a	259	enable_percpu_irq(clk->irq, 0);
81e46f7b MZ	260
	261	return 0;
	262	}
	263
	264	static struct local_timer_ops twd_lt_ops __cpuinitdata = {
	265	.setup = twd_timer_setup,
	266	.stop = twd_timer_stop,
	267	};
	268
d8e03643	269	static int __init twd_local_timer_common_register(void)
81e46f7b MZ	270	{
	271	int err;
	272
81e46f7b	273	twd_evt = alloc_percpu(struct clock_event_device *);
d8e03643	274	if (!twd_evt) {
81e46f7b	275	err = -ENOMEM;
d8e03643	276	goto out_free;
81e46f7b MZ	277	}
	278
	279	err = request_percpu_irq(twd_ppi, twd_handler, "twd", twd_evt);
	280	if (err) {
	281	pr_err("twd: can't register interrupt %d (%d)\n", twd_ppi, err);
d8e03643	282	goto out_free;
81e46f7b MZ	283	}
	284
	285	err = local_timer_register(&twd_lt_ops);
	286	if (err)
d8e03643	287	goto out_irq;
81e46f7b MZ	288
	289	return 0;
	290
d8e03643 MZ	291	out_irq:
	292	free_percpu_irq(twd_ppi, twd_evt);
	293	out_free:
81e46f7b	294	iounmap(twd_base);
d8e03643	295	twd_base = NULL;
81e46f7b	296	free_percpu(twd_evt);
d8e03643	297
81e46f7b	298	return err;
f32f4ce2	299	}
d8e03643 MZ	300
	301	int __init twd_local_timer_register(struct twd_local_timer *tlt)
	302	{
	303	if (twd_base \|\| twd_evt)
	304	return -EBUSY;
	305
	306	twd_ppi = tlt->res[1].start;
	307
	308	twd_base = ioremap(tlt->res[0].start, resource_size(&tlt->res[0]));
	309	if (!twd_base)
	310	return -ENOMEM;
	311
	312	return twd_local_timer_common_register();
	313	}
	314
	315	#ifdef CONFIG_OF
	316	const static struct of_device_id twd_of_match[] __initconst = {
	317	{ .compatible = "arm,cortex-a9-twd-timer", },
	318	{ .compatible = "arm,cortex-a5-twd-timer", },
	319	{ .compatible = "arm,arm11mp-twd-timer", },
	320	{ },
	321	};
	322
	323	void __init twd_local_timer_of_register(void)
	324	{
	325	struct device_node *np;
	326	int err;
	327
	328	np = of_find_matching_node(NULL, twd_of_match);
	329	if (!np) {
	330	err = -ENODEV;
	331	goto out;
	332	}
	333
	334	twd_ppi = irq_of_parse_and_map(np, 0);
	335	if (!twd_ppi) {
	336	err = -EINVAL;
	337	goto out;
	338	}
	339
	340	twd_base = of_iomap(np, 0);
	341	if (!twd_base) {
	342	err = -ENOMEM;
	343	goto out;
	344	}
	345
	346	err = twd_local_timer_common_register();
	347
	348	out:
	349	WARN(err, "twd_local_timer_of_register failed (%d)\n", err);
	350	}
	351	#endif