[mirror_ubuntu-artful-kernel.git] / arch / arm / kernel / topology.c

/*
 * arch/arm/kernel/topology.c
 *
 * Copyright (C) 2011 Linaro Limited.
 * Written by: Vincent Guittot
 *
 * based on arch/sh/kernel/topology.c
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/arch_topology.h>
#include <linux/cpu.h>
#include <linux/cpufreq.h>
#include <linux/cpumask.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/percpu.h>
#include <linux/node.h>
#include <linux/nodemask.h>
#include <linux/of.h>
#include <linux/sched.h>
#include <linux/sched/topology.h>
#include <linux/slab.h>
#include <linux/string.h>

#include <asm/cpu.h>
#include <asm/cputype.h>
#include <asm/topology.h>

/*
 * cpu capacity scale management
 */

/*
 * cpu capacity table
 * This per cpu data structure describes the relative capacity of each core.
 * On a heteregenous system, cores don't have the same computation capacity
 * and we reflect that difference in the cpu_capacity field so the scheduler
 * can take this difference into account during load balance. A per cpu
 * structure is preferred because each CPU updates its own cpu_capacity field
 * during the load balance except for idle cores. One idle core is selected
 * to run the rebalance_domains for all idle cores and the cpu_capacity can be
 * updated during this sequence.
 */

#ifdef CONFIG_OF
struct cpu_efficiency {
	const char *compatible;
	unsigned long efficiency;
};

/*
 * Table of relative efficiency of each processors
 * The efficiency value must fit in 20bit and the final
 * cpu_scale value must be in the range
 *   0 < cpu_scale < 3*SCHED_CAPACITY_SCALE/2
 * in order to return at most 1 when DIV_ROUND_CLOSEST
 * is used to compute the capacity of a CPU.
 * Processors that are not defined in the table,
 * use the default SCHED_CAPACITY_SCALE value for cpu_scale.
 */
static const struct cpu_efficiency table_efficiency[] = {
	{"arm,cortex-a15", 3891},
	{"arm,cortex-a7",  2048},
	{NULL, },
};

static unsigned long *__cpu_capacity;
#define cpu_capacity(cpu)	__cpu_capacity[cpu]

static unsigned long middle_capacity = 1;
static bool cap_from_dt = true;

/*
 * Iterate all CPUs' descriptor in DT and compute the efficiency
 * (as per table_efficiency). Also calculate a middle efficiency
 * as close as possible to  (max{eff_i} - min{eff_i}) / 2
 * This is later used to scale the cpu_capacity field such that an
 * 'average' CPU is of middle capacity. Also see the comments near
 * table_efficiency[] and update_cpu_capacity().
 */
static void __init parse_dt_topology(void)
{
	const struct cpu_efficiency *cpu_eff;
	struct device_node *cn = NULL;
	unsigned long min_capacity = ULONG_MAX;
	unsigned long max_capacity = 0;
	unsigned long capacity = 0;
	int cpu = 0;

	__cpu_capacity = kcalloc(nr_cpu_ids, sizeof(*__cpu_capacity),
				 GFP_NOWAIT);

	cn = of_find_node_by_path("/cpus");
	if (!cn) {
		pr_err("No CPU information found in DT\n");
		return;
	}

	for_each_possible_cpu(cpu) {
		const u32 *rate;
		int len;

		/* too early to use cpu->of_node */
		cn = of_get_cpu_node(cpu, NULL);
		if (!cn) {
			pr_err("missing device node for CPU %d\n", cpu);
			continue;
		}

		if (topology_parse_cpu_capacity(cn, cpu)) {
			of_node_put(cn);
			continue;
		}

		cap_from_dt = false;

		for (cpu_eff = table_efficiency; cpu_eff->compatible; cpu_eff++)
			if (of_device_is_compatible(cn, cpu_eff->compatible))
				break;

		if (cpu_eff->compatible == NULL)
			continue;

		rate = of_get_property(cn, "clock-frequency", &len);
		if (!rate || len != 4) {
			pr_err("%s missing clock-frequency property\n",
				cn->full_name);
			continue;
		}

		capacity = ((be32_to_cpup(rate)) >> 20) * cpu_eff->efficiency;

		/* Save min capacity of the system */
		if (capacity < min_capacity)
			min_capacity = capacity;

		/* Save max capacity of the system */
		if (capacity > max_capacity)
			max_capacity = capacity;

		cpu_capacity(cpu) = capacity;
	}

	/* If min and max capacities are equals, we bypass the update of the
	 * cpu_scale because all CPUs have the same capacity. Otherwise, we
	 * compute a middle_capacity factor that will ensure that the capacity
	 * of an 'average' CPU of the system will be as close as possible to
	 * SCHED_CAPACITY_SCALE, which is the default value, but with the
	 * constraint explained near table_efficiency[].
	 */
	if (4*max_capacity < (3*(max_capacity + min_capacity)))
		middle_capacity = (min_capacity + max_capacity)
				>> (SCHED_CAPACITY_SHIFT+1);
	else
		middle_capacity = ((max_capacity / 3)
				>> (SCHED_CAPACITY_SHIFT-1)) + 1;

	if (cap_from_dt)
		topology_normalize_cpu_scale();
}

/*
 * Look for a customed capacity of a CPU in the cpu_capacity table during the
 * boot. The update of all CPUs is in O(n^2) for heteregeneous system but the
 * function returns directly for SMP system.
 */
static void update_cpu_capacity(unsigned int cpu)
{
	if (!cpu_capacity(cpu) || cap_from_dt)
		return;

	topology_set_cpu_scale(cpu, cpu_capacity(cpu) / middle_capacity);

	pr_info("CPU%u: update cpu_capacity %lu\n",
		cpu, topology_get_cpu_scale(NULL, cpu));
}

#else
static inline void parse_dt_topology(void) {}
static inline void update_cpu_capacity(unsigned int cpuid) {}
#endif

 /*
 * cpu topology table
 */
struct cputopo_arm cpu_topology[NR_CPUS];
EXPORT_SYMBOL_GPL(cpu_topology);

const struct cpumask *cpu_coregroup_mask(int cpu)
{
	return &cpu_topology[cpu].core_sibling;
}

/*
 * The current assumption is that we can power gate each core independently.
 * This will be superseded by DT binding once available.
 */
const struct cpumask *cpu_corepower_mask(int cpu)
{
	return &cpu_topology[cpu].thread_sibling;
}

static void update_siblings_masks(unsigned int cpuid)
{
	struct cputopo_arm *cpu_topo, *cpuid_topo = &cpu_topology[cpuid];
	int cpu;

	/* update core and thread sibling masks */
	for_each_possible_cpu(cpu) {
		cpu_topo = &cpu_topology[cpu];

		if (cpuid_topo->socket_id != cpu_topo->socket_id)
			continue;

		cpumask_set_cpu(cpuid, &cpu_topo->core_sibling);
		if (cpu != cpuid)
			cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);

		if (cpuid_topo->core_id != cpu_topo->core_id)
			continue;

		cpumask_set_cpu(cpuid, &cpu_topo->thread_sibling);
		if (cpu != cpuid)
			cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);
	}
	smp_wmb();
}

/*
 * store_cpu_topology is called at boot when only one cpu is running
 * and with the mutex cpu_hotplug.lock locked, when several cpus have booted,
 * which prevents simultaneous write access to cpu_topology array
 */
void store_cpu_topology(unsigned int cpuid)
{
	struct cputopo_arm *cpuid_topo = &cpu_topology[cpuid];
	unsigned int mpidr;

	/* If the cpu topology has been already set, just return */
	if (cpuid_topo->core_id != -1)
		return;

	mpidr = read_cpuid_mpidr();

	/* create cpu topology mapping */
	if ((mpidr & MPIDR_SMP_BITMASK) == MPIDR_SMP_VALUE) {
		/*
		 * This is a multiprocessor system
		 * multiprocessor format & multiprocessor mode field are set
		 */

		if (mpidr & MPIDR_MT_BITMASK) {
			/* core performance interdependency */
			cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
			cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
			cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
		} else {
			/* largely independent cores */
			cpuid_topo->thread_id = -1;
			cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
			cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
		}
	} else {
		/*
		 * This is an uniprocessor system
		 * we are in multiprocessor format but uniprocessor system
		 * or in the old uniprocessor format
		 */
		cpuid_topo->thread_id = -1;
		cpuid_topo->core_id = 0;
		cpuid_topo->socket_id = -1;
	}

	update_siblings_masks(cpuid);

	update_cpu_capacity(cpuid);

	pr_info("CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n",
		cpuid, cpu_topology[cpuid].thread_id,
		cpu_topology[cpuid].core_id,
		cpu_topology[cpuid].socket_id, mpidr);
}

static inline int cpu_corepower_flags(void)
{
	return SD_SHARE_PKG_RESOURCES  | SD_SHARE_POWERDOMAIN;
}

static struct sched_domain_topology_level arm_topology[] = {
#ifdef CONFIG_SCHED_MC
	{ cpu_corepower_mask, cpu_corepower_flags, SD_INIT_NAME(GMC) },
	{ cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
#endif
	{ cpu_cpu_mask, SD_INIT_NAME(DIE) },
	{ NULL, },
};

/*
 * init_cpu_topology is called at boot when only one cpu is running
 * which prevent simultaneous write access to cpu_topology array
 */
void __init init_cpu_topology(void)
{
	unsigned int cpu;

	/* init core mask and capacity */
	for_each_possible_cpu(cpu) {
		struct cputopo_arm *cpu_topo = &(cpu_topology[cpu]);

		cpu_topo->thread_id = -1;
		cpu_topo->core_id =  -1;
		cpu_topo->socket_id = -1;
		cpumask_clear(&cpu_topo->core_sibling);
		cpumask_clear(&cpu_topo->thread_sibling);
	}
	smp_wmb();

	parse_dt_topology();

	/* Set scheduler topology descriptor */
	set_sched_topology(arm_topology);
}
Commit	Line	Data
c9018aab VG	1	/*
	2	* arch/arm/kernel/topology.c
	3	*
	4	* Copyright (C) 2011 Linaro Limited.
	5	* Written by: Vincent Guittot
	6	*
	7	* based on arch/sh/kernel/topology.c
	8	*
	9	* This file is subject to the terms and conditions of the GNU General Public
	10	* License. See the file "COPYING" in the main directory of this archive
	11	* for more details.
	12	*/
	13
615ffd63	14	#include <linux/arch_topology.h>
c9018aab	15	#include <linux/cpu.h>
06073ee2	16	#include <linux/cpufreq.h>
c9018aab	17	#include <linux/cpumask.h>
92bdd3f5	18	#include <linux/export.h>
c9018aab VG	19	#include <linux/init.h>
	20	#include <linux/percpu.h>
	21	#include <linux/node.h>
	22	#include <linux/nodemask.h>
339ca09d	23	#include <linux/of.h>
c9018aab	24	#include <linux/sched.h>
105ab3d8	25	#include <linux/sched/topology.h>
339ca09d	26	#include <linux/slab.h>
7e5930aa	27	#include <linux/string.h>
c9018aab	28
7e5930aa	29	#include <asm/cpu.h>
c9018aab VG	30	#include <asm/cputype.h>
	31	#include <asm/topology.h>
	32
130d9aab	33	/*
ca8ce3d0	34	* cpu capacity scale management
130d9aab VG	35	*/
	36
	37	/*
ca8ce3d0	38	* cpu capacity table
130d9aab VG	39	* This per cpu data structure describes the relative capacity of each core.
130d9aab VG	40	* On a heteregenous system, cores don't have the same computation capacity
ca8ce3d0 NP	41	* and we reflect that difference in the cpu_capacity field so the scheduler
	42	* can take this difference into account during load balance. A per cpu
	43	* structure is preferred because each CPU updates its own cpu_capacity field
	44	* during the load balance except for idle cores. One idle core is selected
	45	* to run the rebalance_domains for all idle cores and the cpu_capacity can be
	46	* updated during this sequence.
130d9aab	47	*/
130d9aab	48
339ca09d VG	49	#ifdef CONFIG_OF
	50	struct cpu_efficiency {
	51	const char *compatible;
	52	unsigned long efficiency;
	53	};
	54
	55	/*
	56	* Table of relative efficiency of each processors
	57	* The efficiency value must fit in 20bit and the final
	58	* cpu_scale value must be in the range
ca8ce3d0	59	* 0 < cpu_scale < 3*SCHED_CAPACITY_SCALE/2
339ca09d VG	60	* in order to return at most 1 when DIV_ROUND_CLOSEST
	61	* is used to compute the capacity of a CPU.
	62	* Processors that are not defined in the table,
ca8ce3d0	63	* use the default SCHED_CAPACITY_SCALE value for cpu_scale.
339ca09d	64	*/
145bc292	65	static const struct cpu_efficiency table_efficiency[] = {
339ca09d VG	66	{"arm,cortex-a15", 3891},
	67	{"arm,cortex-a7", 2048},
	68	{NULL, },
	69	};
	70
145bc292	71	static unsigned long *__cpu_capacity;
816a8de0	72	#define cpu_capacity(cpu) __cpu_capacity[cpu]
339ca09d	73
145bc292	74	static unsigned long middle_capacity = 1;
06073ee2	75	static bool cap_from_dt = true;
339ca09d VG	76
	77	/*
	78	* Iterate all CPUs' descriptor in DT and compute the efficiency
	79	* (as per table_efficiency). Also calculate a middle efficiency
	80	* as close as possible to (max{eff_i} - min{eff_i}) / 2
ca8ce3d0 NP	81	* This is later used to scale the cpu_capacity field such that an
	82	* 'average' CPU is of middle capacity. Also see the comments near
	83	* table_efficiency[] and update_cpu_capacity().
339ca09d VG	84	*/
	85	static void __init parse_dt_topology(void)
	86	{
145bc292	87	const struct cpu_efficiency *cpu_eff;
339ca09d	88	struct device_node *cn = NULL;
44ae903b	89	unsigned long min_capacity = ULONG_MAX;
339ca09d VG	90	unsigned long max_capacity = 0;
339ca09d VG	91	unsigned long capacity = 0;
44ae903b	92	int cpu = 0;
339ca09d	93
44ae903b MB	94	__cpu_capacity = kcalloc(nr_cpu_ids, sizeof(*__cpu_capacity),
44ae903b MB	95	GFP_NOWAIT);
339ca09d	96
06073ee2 JL	97	cn = of_find_node_by_path("/cpus");
	98	if (!cn) {
	99	pr_err("No CPU information found in DT\n");
	100	return;
	101	}
	102
816a8de0 SH	103	for_each_possible_cpu(cpu) {
816a8de0 SH	104	const u32 *rate;
339ca09d VG	105	int len;
339ca09d VG	106
816a8de0 SH	107	/* too early to use cpu->of_node */
	108	cn = of_get_cpu_node(cpu, NULL);
	109	if (!cn) {
	110	pr_err("missing device node for CPU %d\n", cpu);
	111	continue;
	112	}
339ca09d	113
4ca4f26a	114	if (topology_parse_cpu_capacity(cn, cpu)) {
06073ee2 JL	115	of_node_put(cn);
	116	continue;
	117	}
	118
	119	cap_from_dt = false;
	120
339ca09d VG	121	for (cpu_eff = table_efficiency; cpu_eff->compatible; cpu_eff++)
	122	if (of_device_is_compatible(cn, cpu_eff->compatible))
	123	break;
	124
	125	if (cpu_eff->compatible == NULL)
	126	continue;
	127
	128	rate = of_get_property(cn, "clock-frequency", &len);
	129	if (!rate \|\| len != 4) {
	130	pr_err("%s missing clock-frequency property\n",
	131	cn->full_name);
	132	continue;
	133	}
	134
339ca09d VG	135	capacity = ((be32_to_cpup(rate)) >> 20) * cpu_eff->efficiency;
	136
	137	/* Save min capacity of the system */
	138	if (capacity < min_capacity)
	139	min_capacity = capacity;
	140
	141	/* Save max capacity of the system */
	142	if (capacity > max_capacity)
	143	max_capacity = capacity;
	144
816a8de0	145	cpu_capacity(cpu) = capacity;
339ca09d VG	146	}
339ca09d VG	147
339ca09d VG	148	/* If min and max capacities are equals, we bypass the update of the
	149	* cpu_scale because all CPUs have the same capacity. Otherwise, we
	150	* compute a middle_capacity factor that will ensure that the capacity
	151	* of an 'average' CPU of the system will be as close as possible to
ca8ce3d0	152	* SCHED_CAPACITY_SCALE, which is the default value, but with the
339ca09d VG	153	* constraint explained near table_efficiency[].
339ca09d VG	154	*/
816a8de0	155	if (4max_capacity < (3(max_capacity + min_capacity)))
339ca09d	156	middle_capacity = (min_capacity + max_capacity)
ca8ce3d0	157	>> (SCHED_CAPACITY_SHIFT+1);
339ca09d VG	158	else
339ca09d VG	159	middle_capacity = ((max_capacity / 3)
ca8ce3d0	160	>> (SCHED_CAPACITY_SHIFT-1)) + 1;
339ca09d	161
c105aa31	162	if (cap_from_dt)
4ca4f26a	163	topology_normalize_cpu_scale();
339ca09d VG	164	}
	165
	166	/*
	167	* Look for a customed capacity of a CPU in the cpu_capacity table during the
	168	* boot. The update of all CPUs is in O(n^2) for heteregeneous system but the
	169	* function returns directly for SMP system.
	170	*/
ca8ce3d0	171	static void update_cpu_capacity(unsigned int cpu)
339ca09d	172	{
06073ee2	173	if (!cpu_capacity(cpu) \|\| cap_from_dt)
339ca09d VG	174	return;
339ca09d VG	175
4ca4f26a	176	topology_set_cpu_scale(cpu, cpu_capacity(cpu) / middle_capacity);
339ca09d	177
4ed89f22	178	pr_info("CPU%u: update cpu_capacity %lu\n",
4ca4f26a	179	cpu, topology_get_cpu_scale(NULL, cpu));
339ca09d VG	180	}
	181
	182	#else
	183	static inline void parse_dt_topology(void) {}
ca8ce3d0	184	static inline void update_cpu_capacity(unsigned int cpuid) {}
339ca09d VG	185	#endif
339ca09d VG	186
dca463da	187	/*
130d9aab VG	188	* cpu topology table
130d9aab VG	189	*/
c9018aab	190	struct cputopo_arm cpu_topology[NR_CPUS];
92bdd3f5	191	EXPORT_SYMBOL_GPL(cpu_topology);
c9018aab	192
4cbd6b16	193	const struct cpumask *cpu_coregroup_mask(int cpu)
c9018aab VG	194	{
	195	return &cpu_topology[cpu].core_sibling;
	196	}
	197
fb2aa855 VG	198	/*
	199	* The current assumption is that we can power gate each core independently.
	200	* This will be superseded by DT binding once available.
	201	*/
	202	const struct cpumask *cpu_corepower_mask(int cpu)
	203	{
	204	return &cpu_topology[cpu].thread_sibling;
	205	}
	206
145bc292	207	static void update_siblings_masks(unsigned int cpuid)
cb75dacb VG	208	{
	209	struct cputopo_arm cpu_topo, cpuid_topo = &cpu_topology[cpuid];
	210	int cpu;
	211
	212	/* update core and thread sibling masks */
	213	for_each_possible_cpu(cpu) {
	214	cpu_topo = &cpu_topology[cpu];
	215
	216	if (cpuid_topo->socket_id != cpu_topo->socket_id)
	217	continue;
	218
	219	cpumask_set_cpu(cpuid, &cpu_topo->core_sibling);
	220	if (cpu != cpuid)
	221	cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);
	222
	223	if (cpuid_topo->core_id != cpu_topo->core_id)
	224	continue;
	225
	226	cpumask_set_cpu(cpuid, &cpu_topo->thread_sibling);
	227	if (cpu != cpuid)
	228	cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);
	229	}
	230	smp_wmb();
	231	}
	232
c9018aab VG	233	/*
	234	* store_cpu_topology is called at boot when only one cpu is running
	235	* and with the mutex cpu_hotplug.lock locked, when several cpus have booted,
	236	* which prevents simultaneous write access to cpu_topology array
	237	*/
	238	void store_cpu_topology(unsigned int cpuid)
	239	{
	240	struct cputopo_arm *cpuid_topo = &cpu_topology[cpuid];
	241	unsigned int mpidr;
c9018aab VG	242
	243	/* If the cpu topology has been already set, just return */
	244	if (cpuid_topo->core_id != -1)
	245	return;
	246
	247	mpidr = read_cpuid_mpidr();
	248
	249	/* create cpu topology mapping */
	250	if ((mpidr & MPIDR_SMP_BITMASK) == MPIDR_SMP_VALUE) {
	251	/*
	252	* This is a multiprocessor system
	253	* multiprocessor format & multiprocessor mode field are set
	254	*/
	255
	256	if (mpidr & MPIDR_MT_BITMASK) {
	257	/* core performance interdependency */
71db5bfe LP	258	cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
	259	cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
	260	cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
c9018aab VG	261	} else {
	262	/* largely independent cores */
	263	cpuid_topo->thread_id = -1;
71db5bfe LP	264	cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
71db5bfe LP	265	cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
c9018aab VG	266	}
	267	} else {
	268	/*
	269	* This is an uniprocessor system
	270	* we are in multiprocessor format but uniprocessor system
	271	* or in the old uniprocessor format
	272	*/
	273	cpuid_topo->thread_id = -1;
	274	cpuid_topo->core_id = 0;
	275	cpuid_topo->socket_id = -1;
	276	}
	277
cb75dacb	278	update_siblings_masks(cpuid);
c9018aab	279
ca8ce3d0	280	update_cpu_capacity(cpuid);
339ca09d	281
4ed89f22	282	pr_info("CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n",
c9018aab VG	283	cpuid, cpu_topology[cpuid].thread_id,
	284	cpu_topology[cpuid].core_id,
	285	cpu_topology[cpuid].socket_id, mpidr);
	286	}
	287
b6220ad6	288	static inline int cpu_corepower_flags(void)
fb2aa855 VG	289	{
	290	return SD_SHARE_PKG_RESOURCES \| SD_SHARE_POWERDOMAIN;
	291	}
	292
	293	static struct sched_domain_topology_level arm_topology[] = {
	294	#ifdef CONFIG_SCHED_MC
	295	{ cpu_corepower_mask, cpu_corepower_flags, SD_INIT_NAME(GMC) },
	296	{ cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
	297	#endif
	298	{ cpu_cpu_mask, SD_INIT_NAME(DIE) },
	299	{ NULL, },
	300	};
	301
c9018aab VG	302	/*
	303	* init_cpu_topology is called at boot when only one cpu is running
	304	* which prevent simultaneous write access to cpu_topology array
	305	*/
f7e416eb	306	void __init init_cpu_topology(void)
c9018aab VG	307	{
	308	unsigned int cpu;
	309
ca8ce3d0	310	/* init core mask and capacity */
c9018aab VG	311	for_each_possible_cpu(cpu) {
	312	struct cputopo_arm *cpu_topo = &(cpu_topology[cpu]);
	313
	314	cpu_topo->thread_id = -1;
	315	cpu_topo->core_id = -1;
	316	cpu_topo->socket_id = -1;
	317	cpumask_clear(&cpu_topo->core_sibling);
	318	cpumask_clear(&cpu_topo->thread_sibling);
	319	}
	320	smp_wmb();
339ca09d VG	321
339ca09d VG	322	parse_dt_topology();
fb2aa855 VG	323
	324	/* Set scheduler topology descriptor */
	325	set_sched_topology(arm_topology);
c9018aab	326	}