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73a59c1c | 1 | /* |
9d041268 | 2 | * linux/arch/arm/mach-at91/at91rm9200_time.c |
73a59c1c SP |
3 | * |
4 | * Copyright (C) 2003 SAN People | |
5 | * Copyright (C) 2003 ATMEL | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
5e802dfa | 22 | #include <linux/kernel.h> |
73a59c1c | 23 | #include <linux/interrupt.h> |
07d265dd | 24 | #include <linux/irq.h> |
5e802dfa | 25 | #include <linux/clockchips.h> |
9fce85c7 | 26 | #include <linux/export.h> |
454c46df JE |
27 | #include <linux/of.h> |
28 | #include <linux/of_address.h> | |
29 | #include <linux/of_irq.h> | |
73a59c1c | 30 | |
73a59c1c SP |
31 | #include <asm/mach/time.h> |
32 | ||
a09e64fb | 33 | #include <mach/at91_st.h> |
55d8baee | 34 | |
963151f2 | 35 | static unsigned long last_crtr; |
5e802dfa DB |
36 | static u32 irqmask; |
37 | static struct clock_event_device clkevt; | |
963151f2 | 38 | |
2f5893cf JCPV |
39 | #define RM9200_TIMER_LATCH ((AT91_SLOW_CLOCK + HZ/2) / HZ) |
40 | ||
73a59c1c | 41 | /* |
5e802dfa DB |
42 | * The ST_CRTR is updated asynchronously to the master clock ... but |
43 | * the updates as seen by the CPU don't seem to be strictly monotonic. | |
44 | * Waiting until we read the same value twice avoids glitching. | |
73a59c1c | 45 | */ |
5e802dfa DB |
46 | static inline unsigned long read_CRTR(void) |
47 | { | |
73a59c1c SP |
48 | unsigned long x1, x2; |
49 | ||
5e9cf5e1 | 50 | x1 = at91_st_read(AT91_ST_CRTR); |
73a59c1c | 51 | do { |
5e9cf5e1 | 52 | x2 = at91_st_read(AT91_ST_CRTR); |
5e802dfa DB |
53 | if (x1 == x2) |
54 | break; | |
55 | x1 = x2; | |
56 | } while (1); | |
73a59c1c SP |
57 | return x1; |
58 | } | |
59 | ||
73a59c1c SP |
60 | /* |
61 | * IRQ handler for the timer. | |
62 | */ | |
0cd61b68 | 63 | static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) |
73a59c1c | 64 | { |
5e9cf5e1 | 65 | u32 sr = at91_st_read(AT91_ST_SR) & irqmask; |
73a59c1c | 66 | |
501d7038 UKK |
67 | /* |
68 | * irqs should be disabled here, but as the irq is shared they are only | |
69 | * guaranteed to be off if the timer irq is registered first. | |
70 | */ | |
71 | WARN_ON_ONCE(!irqs_disabled()); | |
72 | ||
5e802dfa DB |
73 | /* simulate "oneshot" timer with alarm */ |
74 | if (sr & AT91_ST_ALMS) { | |
75 | clkevt.event_handler(&clkevt); | |
76 | return IRQ_HANDLED; | |
77 | } | |
73a59c1c | 78 | |
5e802dfa DB |
79 | /* periodic mode should handle delayed ticks */ |
80 | if (sr & AT91_ST_PITS) { | |
81 | u32 crtr = read_CRTR(); | |
73a59c1c | 82 | |
2f5893cf JCPV |
83 | while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) { |
84 | last_crtr += RM9200_TIMER_LATCH; | |
5e802dfa DB |
85 | clkevt.event_handler(&clkevt); |
86 | } | |
73a59c1c SP |
87 | return IRQ_HANDLED; |
88 | } | |
5e802dfa DB |
89 | |
90 | /* this irq is shared ... */ | |
91 | return IRQ_NONE; | |
73a59c1c SP |
92 | } |
93 | ||
94 | static struct irqaction at91rm9200_timer_irq = { | |
95 | .name = "at91_tick", | |
9ceb389d | 96 | .flags = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL, |
454c46df JE |
97 | .handler = at91rm9200_timer_interrupt, |
98 | .irq = NR_IRQS_LEGACY + AT91_ID_SYS, | |
73a59c1c SP |
99 | }; |
100 | ||
8e19608e | 101 | static cycle_t read_clk32k(struct clocksource *cs) |
2a6f9902 | 102 | { |
5e802dfa DB |
103 | return read_CRTR(); |
104 | } | |
2a6f9902 | 105 | |
5e802dfa DB |
106 | static struct clocksource clk32k = { |
107 | .name = "32k_counter", | |
108 | .rating = 150, | |
109 | .read = read_clk32k, | |
110 | .mask = CLOCKSOURCE_MASK(20), | |
5e802dfa DB |
111 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
112 | }; | |
113 | ||
114 | static void | |
115 | clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev) | |
116 | { | |
117 | /* Disable and flush pending timer interrupts */ | |
5e9cf5e1 | 118 | at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS); |
9e1c0b2e | 119 | at91_st_read(AT91_ST_SR); |
2a6f9902 | 120 | |
5e802dfa DB |
121 | last_crtr = read_CRTR(); |
122 | switch (mode) { | |
123 | case CLOCK_EVT_MODE_PERIODIC: | |
124 | /* PIT for periodic irqs; fixed rate of 1/HZ */ | |
125 | irqmask = AT91_ST_PITS; | |
5e9cf5e1 | 126 | at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH); |
5e802dfa DB |
127 | break; |
128 | case CLOCK_EVT_MODE_ONESHOT: | |
129 | /* ALM for oneshot irqs, set by next_event() | |
130 | * before 32 seconds have passed | |
131 | */ | |
132 | irqmask = AT91_ST_ALMS; | |
5e9cf5e1 | 133 | at91_st_write(AT91_ST_RTAR, last_crtr); |
5e802dfa DB |
134 | break; |
135 | case CLOCK_EVT_MODE_SHUTDOWN: | |
136 | case CLOCK_EVT_MODE_UNUSED: | |
137 | case CLOCK_EVT_MODE_RESUME: | |
138 | irqmask = 0; | |
139 | break; | |
140 | } | |
5e9cf5e1 | 141 | at91_st_write(AT91_ST_IER, irqmask); |
5e802dfa | 142 | } |
2a6f9902 | 143 | |
5e802dfa DB |
144 | static int |
145 | clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) | |
146 | { | |
5e802dfa DB |
147 | u32 alm; |
148 | int status = 0; | |
149 | ||
150 | BUG_ON(delta < 2); | |
151 | ||
5e802dfa DB |
152 | /* The alarm IRQ uses absolute time (now+delta), not the relative |
153 | * time (delta) in our calling convention. Like all clockevents | |
154 | * using such "match" hardware, we have a race to defend against. | |
155 | * | |
156 | * Our defense here is to have set up the clockevent device so the | |
157 | * delta is at least two. That way we never end up writing RTAR | |
158 | * with the value then held in CRTR ... which would mean the match | |
159 | * wouldn't trigger until 32 seconds later, after CRTR wraps. | |
160 | */ | |
161 | alm = read_CRTR(); | |
162 | ||
163 | /* Cancel any pending alarm; flush any pending IRQ */ | |
5e9cf5e1 | 164 | at91_st_write(AT91_ST_RTAR, alm); |
9e1c0b2e | 165 | at91_st_read(AT91_ST_SR); |
d100f259 | 166 | |
5e802dfa DB |
167 | /* Schedule alarm by writing RTAR. */ |
168 | alm += delta; | |
5e9cf5e1 | 169 | at91_st_write(AT91_ST_RTAR, alm); |
5e802dfa | 170 | |
5e802dfa | 171 | return status; |
2a6f9902 AV |
172 | } |
173 | ||
5e802dfa DB |
174 | static struct clock_event_device clkevt = { |
175 | .name = "at91_tick", | |
176 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
b7a8ca51 | 177 | .shift = 32, |
5e802dfa | 178 | .rating = 150, |
5e802dfa DB |
179 | .set_next_event = clkevt32k_next_event, |
180 | .set_mode = clkevt32k_mode, | |
181 | }; | |
182 | ||
5e9cf5e1 | 183 | void __iomem *at91_st_base; |
9fce85c7 | 184 | EXPORT_SYMBOL_GPL(at91_st_base); |
5e9cf5e1 | 185 | |
454c46df JE |
186 | #ifdef CONFIG_OF |
187 | static struct of_device_id at91rm9200_st_timer_ids[] = { | |
188 | { .compatible = "atmel,at91rm9200-st" }, | |
189 | { /* sentinel */ } | |
190 | }; | |
191 | ||
192 | static int __init of_at91rm9200_st_init(void) | |
193 | { | |
194 | struct device_node *np; | |
195 | int ret; | |
196 | ||
197 | np = of_find_matching_node(NULL, at91rm9200_st_timer_ids); | |
198 | if (!np) | |
199 | goto err; | |
200 | ||
201 | at91_st_base = of_iomap(np, 0); | |
202 | if (!at91_st_base) | |
203 | goto node_err; | |
204 | ||
205 | /* Get the interrupts property */ | |
206 | ret = irq_of_parse_and_map(np, 0); | |
207 | if (!ret) | |
208 | goto ioremap_err; | |
209 | at91rm9200_timer_irq.irq = ret; | |
210 | ||
211 | of_node_put(np); | |
212 | ||
213 | return 0; | |
214 | ||
215 | ioremap_err: | |
216 | iounmap(at91_st_base); | |
217 | node_err: | |
218 | of_node_put(np); | |
219 | err: | |
220 | return -EINVAL; | |
221 | } | |
222 | #else | |
223 | static int __init of_at91rm9200_st_init(void) | |
224 | { | |
225 | return -EINVAL; | |
226 | } | |
227 | #endif | |
228 | ||
5e9cf5e1 JCPV |
229 | void __init at91rm9200_ioremap_st(u32 addr) |
230 | { | |
454c46df JE |
231 | #ifdef CONFIG_OF |
232 | struct device_node *np; | |
233 | ||
234 | np = of_find_matching_node(NULL, at91rm9200_st_timer_ids); | |
235 | if (np) { | |
236 | of_node_put(np); | |
237 | return; | |
238 | } | |
239 | #endif | |
5e9cf5e1 JCPV |
240 | at91_st_base = ioremap(addr, 256); |
241 | if (!at91_st_base) | |
242 | panic("Impossible to ioremap ST\n"); | |
243 | } | |
244 | ||
73a59c1c | 245 | /* |
5e802dfa | 246 | * ST (system timer) module supports both clockevents and clocksource. |
73a59c1c SP |
247 | */ |
248 | void __init at91rm9200_timer_init(void) | |
249 | { | |
454c46df JE |
250 | /* For device tree enabled device: initialize here */ |
251 | of_at91rm9200_st_init(); | |
252 | ||
5e802dfa | 253 | /* Disable all timer interrupts, and clear any pending ones */ |
5e9cf5e1 | 254 | at91_st_write(AT91_ST_IDR, |
5e802dfa | 255 | AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); |
9e1c0b2e | 256 | at91_st_read(AT91_ST_SR); |
73a59c1c | 257 | |
2a6f9902 | 258 | /* Make IRQs happen for the system timer */ |
454c46df | 259 | setup_irq(at91rm9200_timer_irq.irq, &at91rm9200_timer_irq); |
73a59c1c | 260 | |
5e802dfa DB |
261 | /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used |
262 | * directly for the clocksource and all clockevents, after adjusting | |
263 | * its prescaler from the 1 Hz default. | |
264 | */ | |
5e9cf5e1 | 265 | at91_st_write(AT91_ST_RTMR, 1); |
73a59c1c | 266 | |
5e802dfa | 267 | /* Setup timer clockevent, with minimum of two ticks (important!!) */ |
b7a8ca51 JCPV |
268 | clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift); |
269 | clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt); | |
270 | clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1; | |
320ab2b0 | 271 | clkevt.cpumask = cpumask_of(0); |
b7a8ca51 | 272 | clockevents_register_device(&clkevt); |
2a6f9902 | 273 | |
5e802dfa | 274 | /* register clocksource */ |
132b1632 | 275 | clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK); |
73a59c1c | 276 | } |