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73a59c1c | 1 | /* |
9d041268 | 2 | * linux/arch/arm/mach-at91/at91rm9200_time.c |
73a59c1c SP |
3 | * |
4 | * Copyright (C) 2003 SAN People | |
5 | * Copyright (C) 2003 ATMEL | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
5e802dfa | 22 | #include <linux/kernel.h> |
73a59c1c | 23 | #include <linux/interrupt.h> |
07d265dd | 24 | #include <linux/irq.h> |
5e802dfa | 25 | #include <linux/clockchips.h> |
9fce85c7 | 26 | #include <linux/export.h> |
454c46df JE |
27 | #include <linux/of.h> |
28 | #include <linux/of_address.h> | |
29 | #include <linux/of_irq.h> | |
73a59c1c | 30 | |
73a59c1c SP |
31 | #include <asm/mach/time.h> |
32 | ||
a09e64fb | 33 | #include <mach/at91_st.h> |
ac11a1d4 | 34 | #include <mach/hardware.h> |
55d8baee | 35 | |
963151f2 | 36 | static unsigned long last_crtr; |
5e802dfa DB |
37 | static u32 irqmask; |
38 | static struct clock_event_device clkevt; | |
963151f2 | 39 | |
2f5893cf JCPV |
40 | #define RM9200_TIMER_LATCH ((AT91_SLOW_CLOCK + HZ/2) / HZ) |
41 | ||
73a59c1c | 42 | /* |
5e802dfa DB |
43 | * The ST_CRTR is updated asynchronously to the master clock ... but |
44 | * the updates as seen by the CPU don't seem to be strictly monotonic. | |
45 | * Waiting until we read the same value twice avoids glitching. | |
73a59c1c | 46 | */ |
5e802dfa DB |
47 | static inline unsigned long read_CRTR(void) |
48 | { | |
73a59c1c SP |
49 | unsigned long x1, x2; |
50 | ||
5e9cf5e1 | 51 | x1 = at91_st_read(AT91_ST_CRTR); |
73a59c1c | 52 | do { |
5e9cf5e1 | 53 | x2 = at91_st_read(AT91_ST_CRTR); |
5e802dfa DB |
54 | if (x1 == x2) |
55 | break; | |
56 | x1 = x2; | |
57 | } while (1); | |
73a59c1c SP |
58 | return x1; |
59 | } | |
60 | ||
73a59c1c SP |
61 | /* |
62 | * IRQ handler for the timer. | |
63 | */ | |
0cd61b68 | 64 | static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) |
73a59c1c | 65 | { |
5e9cf5e1 | 66 | u32 sr = at91_st_read(AT91_ST_SR) & irqmask; |
73a59c1c | 67 | |
501d7038 UKK |
68 | /* |
69 | * irqs should be disabled here, but as the irq is shared they are only | |
70 | * guaranteed to be off if the timer irq is registered first. | |
71 | */ | |
72 | WARN_ON_ONCE(!irqs_disabled()); | |
73 | ||
5e802dfa DB |
74 | /* simulate "oneshot" timer with alarm */ |
75 | if (sr & AT91_ST_ALMS) { | |
76 | clkevt.event_handler(&clkevt); | |
77 | return IRQ_HANDLED; | |
78 | } | |
73a59c1c | 79 | |
5e802dfa DB |
80 | /* periodic mode should handle delayed ticks */ |
81 | if (sr & AT91_ST_PITS) { | |
82 | u32 crtr = read_CRTR(); | |
73a59c1c | 83 | |
2f5893cf JCPV |
84 | while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) { |
85 | last_crtr += RM9200_TIMER_LATCH; | |
5e802dfa DB |
86 | clkevt.event_handler(&clkevt); |
87 | } | |
73a59c1c SP |
88 | return IRQ_HANDLED; |
89 | } | |
5e802dfa DB |
90 | |
91 | /* this irq is shared ... */ | |
92 | return IRQ_NONE; | |
73a59c1c SP |
93 | } |
94 | ||
95 | static struct irqaction at91rm9200_timer_irq = { | |
96 | .name = "at91_tick", | |
9ceb389d | 97 | .flags = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL, |
454c46df JE |
98 | .handler = at91rm9200_timer_interrupt, |
99 | .irq = NR_IRQS_LEGACY + AT91_ID_SYS, | |
73a59c1c SP |
100 | }; |
101 | ||
8e19608e | 102 | static cycle_t read_clk32k(struct clocksource *cs) |
2a6f9902 | 103 | { |
5e802dfa DB |
104 | return read_CRTR(); |
105 | } | |
2a6f9902 | 106 | |
5e802dfa DB |
107 | static struct clocksource clk32k = { |
108 | .name = "32k_counter", | |
109 | .rating = 150, | |
110 | .read = read_clk32k, | |
111 | .mask = CLOCKSOURCE_MASK(20), | |
5e802dfa DB |
112 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
113 | }; | |
114 | ||
115 | static void | |
116 | clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev) | |
117 | { | |
118 | /* Disable and flush pending timer interrupts */ | |
5e9cf5e1 | 119 | at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS); |
9e1c0b2e | 120 | at91_st_read(AT91_ST_SR); |
2a6f9902 | 121 | |
5e802dfa DB |
122 | last_crtr = read_CRTR(); |
123 | switch (mode) { | |
124 | case CLOCK_EVT_MODE_PERIODIC: | |
125 | /* PIT for periodic irqs; fixed rate of 1/HZ */ | |
126 | irqmask = AT91_ST_PITS; | |
5e9cf5e1 | 127 | at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH); |
5e802dfa DB |
128 | break; |
129 | case CLOCK_EVT_MODE_ONESHOT: | |
130 | /* ALM for oneshot irqs, set by next_event() | |
131 | * before 32 seconds have passed | |
132 | */ | |
133 | irqmask = AT91_ST_ALMS; | |
5e9cf5e1 | 134 | at91_st_write(AT91_ST_RTAR, last_crtr); |
5e802dfa DB |
135 | break; |
136 | case CLOCK_EVT_MODE_SHUTDOWN: | |
137 | case CLOCK_EVT_MODE_UNUSED: | |
138 | case CLOCK_EVT_MODE_RESUME: | |
139 | irqmask = 0; | |
140 | break; | |
141 | } | |
5e9cf5e1 | 142 | at91_st_write(AT91_ST_IER, irqmask); |
5e802dfa | 143 | } |
2a6f9902 | 144 | |
5e802dfa DB |
145 | static int |
146 | clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) | |
147 | { | |
5e802dfa DB |
148 | u32 alm; |
149 | int status = 0; | |
150 | ||
151 | BUG_ON(delta < 2); | |
152 | ||
5e802dfa DB |
153 | /* The alarm IRQ uses absolute time (now+delta), not the relative |
154 | * time (delta) in our calling convention. Like all clockevents | |
155 | * using such "match" hardware, we have a race to defend against. | |
156 | * | |
157 | * Our defense here is to have set up the clockevent device so the | |
158 | * delta is at least two. That way we never end up writing RTAR | |
159 | * with the value then held in CRTR ... which would mean the match | |
160 | * wouldn't trigger until 32 seconds later, after CRTR wraps. | |
161 | */ | |
162 | alm = read_CRTR(); | |
163 | ||
164 | /* Cancel any pending alarm; flush any pending IRQ */ | |
5e9cf5e1 | 165 | at91_st_write(AT91_ST_RTAR, alm); |
9e1c0b2e | 166 | at91_st_read(AT91_ST_SR); |
d100f259 | 167 | |
5e802dfa DB |
168 | /* Schedule alarm by writing RTAR. */ |
169 | alm += delta; | |
5e9cf5e1 | 170 | at91_st_write(AT91_ST_RTAR, alm); |
5e802dfa | 171 | |
5e802dfa | 172 | return status; |
2a6f9902 AV |
173 | } |
174 | ||
5e802dfa DB |
175 | static struct clock_event_device clkevt = { |
176 | .name = "at91_tick", | |
177 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
5e802dfa | 178 | .rating = 150, |
5e802dfa DB |
179 | .set_next_event = clkevt32k_next_event, |
180 | .set_mode = clkevt32k_mode, | |
181 | }; | |
182 | ||
5e9cf5e1 | 183 | void __iomem *at91_st_base; |
9fce85c7 | 184 | EXPORT_SYMBOL_GPL(at91_st_base); |
5e9cf5e1 | 185 | |
444d2d33 | 186 | static const struct of_device_id at91rm9200_st_timer_ids[] = { |
454c46df JE |
187 | { .compatible = "atmel,at91rm9200-st" }, |
188 | { /* sentinel */ } | |
189 | }; | |
190 | ||
191 | static int __init of_at91rm9200_st_init(void) | |
192 | { | |
193 | struct device_node *np; | |
194 | int ret; | |
195 | ||
196 | np = of_find_matching_node(NULL, at91rm9200_st_timer_ids); | |
197 | if (!np) | |
198 | goto err; | |
199 | ||
200 | at91_st_base = of_iomap(np, 0); | |
201 | if (!at91_st_base) | |
202 | goto node_err; | |
203 | ||
204 | /* Get the interrupts property */ | |
205 | ret = irq_of_parse_and_map(np, 0); | |
206 | if (!ret) | |
207 | goto ioremap_err; | |
208 | at91rm9200_timer_irq.irq = ret; | |
209 | ||
210 | of_node_put(np); | |
211 | ||
212 | return 0; | |
213 | ||
214 | ioremap_err: | |
215 | iounmap(at91_st_base); | |
216 | node_err: | |
217 | of_node_put(np); | |
218 | err: | |
219 | return -EINVAL; | |
220 | } | |
5e9cf5e1 | 221 | |
73a59c1c | 222 | /* |
5e802dfa | 223 | * ST (system timer) module supports both clockevents and clocksource. |
73a59c1c SP |
224 | */ |
225 | void __init at91rm9200_timer_init(void) | |
226 | { | |
454c46df JE |
227 | /* For device tree enabled device: initialize here */ |
228 | of_at91rm9200_st_init(); | |
229 | ||
5e802dfa | 230 | /* Disable all timer interrupts, and clear any pending ones */ |
5e9cf5e1 | 231 | at91_st_write(AT91_ST_IDR, |
5e802dfa | 232 | AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); |
9e1c0b2e | 233 | at91_st_read(AT91_ST_SR); |
73a59c1c | 234 | |
2a6f9902 | 235 | /* Make IRQs happen for the system timer */ |
454c46df | 236 | setup_irq(at91rm9200_timer_irq.irq, &at91rm9200_timer_irq); |
73a59c1c | 237 | |
5e802dfa DB |
238 | /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used |
239 | * directly for the clocksource and all clockevents, after adjusting | |
240 | * its prescaler from the 1 Hz default. | |
241 | */ | |
5e9cf5e1 | 242 | at91_st_write(AT91_ST_RTMR, 1); |
73a59c1c | 243 | |
5e802dfa | 244 | /* Setup timer clockevent, with minimum of two ticks (important!!) */ |
320ab2b0 | 245 | clkevt.cpumask = cpumask_of(0); |
1c283531 UKK |
246 | clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK, |
247 | 2, AT91_ST_ALMV); | |
2a6f9902 | 248 | |
5e802dfa | 249 | /* register clocksource */ |
132b1632 | 250 | clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK); |
73a59c1c | 251 | } |