[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-at91 / at91sam9263.c

/*
 * arch/arm/mach-at91/at91sam9263.c
 *
 *  Copyright (C) 2007 Atmel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/module.h>
#include <linux/pm.h>

#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91sam9263.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
#include <mach/at91_shdwc.h>

#include "soc.h"
#include "generic.h"
#include "clock.h"

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioCDE_clk = {
	.name		= "pioCDE_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_PIOCDE,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
	.name		= "mci0_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_MCI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
	.name		= "mci1_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_MCI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk can_clk = {
	.name		= "can_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_CAN,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
	.name		= "twi_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_TWI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
	.name		= "spi0_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_SPI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
	.name		= "spi1_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_SPI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
	.name		= "ac97_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_AC97C,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tcb_clk = {
	.name		= "tcb_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_TCB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
	.name		= "pwm_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_PWMC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
	.name		= "macb_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_EMAC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
	.name		= "dma_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_DMA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twodge_clk = {
	.name		= "2dge_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_2DGE,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udc_clk = {
	.name		= "udc_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_UDP,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
	.name		= "isi_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_ISI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
	.name		= "ohci_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_UHP,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioCDE_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&mmc0_clk,
	&mmc1_clk,
	&can_clk,
	&twi_clk,
	&spi0_clk,
	&spi1_clk,
	&ssc0_clk,
	&ssc1_clk,
	&ac97_clk,
	&tcb_clk,
	&pwm_clk,
	&macb_clk,
	&twodge_clk,
	&udc_clk,
	&isi_clk,
	&lcdc_clk,
	&dma_clk,
	&ohci_clk,
	// irq0 .. irq1
};

static struct clk_lookup periph_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
	/* fake hclk clock */
	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
};

/*
 * The four programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};
static struct clk pck2 = {
	.name		= "pck2",
	.pmc_mask	= AT91_PMC_PCK2,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 2,
};
static struct clk pck3 = {
	.name		= "pck3",
	.pmc_mask	= AT91_PMC_PCK3,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 3,
};

static void __init at91sam9263_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	clk_register(&pck0);
	clk_register(&pck1);
	clk_register(&pck2);
	clk_register(&pck3);
}

static struct clk_lookup console_clock_lookup;

void __init at91sam9263_set_console_clock(int id)
{
	if (id >= ARRAY_SIZE(usart_clocks_lookups))
		return;

	console_clock_lookup.con_id = "usart";
	console_clock_lookup.clk = usart_clocks_lookups[id].clk;
	clkdev_add(&console_clock_lookup);
}

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9263_gpio[] = {
	{
		.id		= AT91SAM9263_ID_PIOA,
		.offset		= AT91_PIOA,
		.clock		= &pioA_clk,
	}, {
		.id		= AT91SAM9263_ID_PIOB,
		.offset		= AT91_PIOB,
		.clock		= &pioB_clk,
	}, {
		.id		= AT91SAM9263_ID_PIOCDE,
		.offset		= AT91_PIOC,
		.clock		= &pioCDE_clk,
	}, {
		.id		= AT91SAM9263_ID_PIOCDE,
		.offset		= AT91_PIOD,
		.clock		= &pioCDE_clk,
	}, {
		.id		= AT91SAM9263_ID_PIOCDE,
		.offset		= AT91_PIOE,
		.clock		= &pioCDE_clk,
	}
};

static void at91sam9263_poweroff(void)
{
	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
}


/* --------------------------------------------------------------------
 *  AT91SAM9263 processor initialization
 * -------------------------------------------------------------------- */

static void __init at91sam9263_map_io(void)
{
	at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
	at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
}

static void __init at91sam9263_initialize(void)
{
	at91_arch_reset = at91sam9_alt_reset;
	pm_power_off = at91sam9263_poweroff;
	at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9263_gpio, 5);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller (FIQ) */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C, D and E */
	0,
	0,
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	0,	/* Multimedia Card Interface 0 */
	0,	/* Multimedia Card Interface 1 */
	3,	/* CAN */
	6,	/* Two-Wire Interface */
	5,	/* Serial Peripheral Interface 0 */
	5,	/* Serial Peripheral Interface 1 */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	5,	/* AC97 Controller */
	0,	/* Timer Counter 0, 1 and 2 */
	0,	/* Pulse Width Modulation Controller */
	3,	/* Ethernet */
	0,
	0,	/* 2D Graphic Engine */
	2,	/* USB Device Port */
	0,	/* Image Sensor Interface */
	3,	/* LDC Controller */
	0,	/* DMA Controller */
	0,
	2,	/* USB Host port */
	0,	/* Advanced Interrupt Controller (IRQ0) */
	0,	/* Advanced Interrupt Controller (IRQ1) */
};

struct at91_init_soc __initdata at91sam9263_soc = {
	.map_io = at91sam9263_map_io,
	.default_irq_priority = at91sam9263_default_irq_priority,
	.register_clocks = at91sam9263_register_clocks,
	.init = at91sam9263_initialize,
};
Commit	Line	Data
b2c65616 AV	1	/*
	2	* arch/arm/mach-at91/at91sam9263.c
	3	*
	4	* Copyright (C) 2007 Atmel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	*/
	12
	13	#include <linux/module.h>
3ef2fb42	14	#include <linux/pm.h>
b2c65616	15
80b02c17	16	#include <asm/irq.h>
b2c65616 AV	17	#include <asm/mach/arch.h>
b2c65616 AV	18	#include <asm/mach/map.h>
a09e64fb RK	19	#include <mach/at91sam9263.h>
	20	#include <mach/at91_pmc.h>
	21	#include <mach/at91_rstc.h>
	22	#include <mach/at91_shdwc.h>
b2c65616	23
21d08b9d	24	#include "soc.h"
b2c65616 AV	25	#include "generic.h"
	26	#include "clock.h"
	27
b2c65616 AV	28	/* --------------------------------------------------------------------
	29	* Clocks
	30	* -------------------------------------------------------------------- */
	31
	32	/*
	33	* The peripheral clocks.
	34	*/
	35	static struct clk pioA_clk = {
	36	.name = "pioA_clk",
	37	.pmc_mask = 1 << AT91SAM9263_ID_PIOA,
	38	.type = CLK_TYPE_PERIPHERAL,
	39	};
	40	static struct clk pioB_clk = {
	41	.name = "pioB_clk",
	42	.pmc_mask = 1 << AT91SAM9263_ID_PIOB,
	43	.type = CLK_TYPE_PERIPHERAL,
	44	};
	45	static struct clk pioCDE_clk = {
	46	.name = "pioCDE_clk",
	47	.pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
	48	.type = CLK_TYPE_PERIPHERAL,
	49	};
	50	static struct clk usart0_clk = {
	51	.name = "usart0_clk",
	52	.pmc_mask = 1 << AT91SAM9263_ID_US0,
	53	.type = CLK_TYPE_PERIPHERAL,
	54	};
	55	static struct clk usart1_clk = {
	56	.name = "usart1_clk",
	57	.pmc_mask = 1 << AT91SAM9263_ID_US1,
	58	.type = CLK_TYPE_PERIPHERAL,
	59	};
	60	static struct clk usart2_clk = {
	61	.name = "usart2_clk",
	62	.pmc_mask = 1 << AT91SAM9263_ID_US2,
	63	.type = CLK_TYPE_PERIPHERAL,
	64	};
	65	static struct clk mmc0_clk = {
	66	.name = "mci0_clk",
	67	.pmc_mask = 1 << AT91SAM9263_ID_MCI0,
	68	.type = CLK_TYPE_PERIPHERAL,
	69	};
	70	static struct clk mmc1_clk = {
	71	.name = "mci1_clk",
	72	.pmc_mask = 1 << AT91SAM9263_ID_MCI1,
	73	.type = CLK_TYPE_PERIPHERAL,
	74	};
e8788bab AV	75	static struct clk can_clk = {
	76	.name = "can_clk",
	77	.pmc_mask = 1 << AT91SAM9263_ID_CAN,
	78	.type = CLK_TYPE_PERIPHERAL,
	79	};
b2c65616 AV	80	static struct clk twi_clk = {
	81	.name = "twi_clk",
	82	.pmc_mask = 1 << AT91SAM9263_ID_TWI,
	83	.type = CLK_TYPE_PERIPHERAL,
	84	};
	85	static struct clk spi0_clk = {
	86	.name = "spi0_clk",
	87	.pmc_mask = 1 << AT91SAM9263_ID_SPI0,
	88	.type = CLK_TYPE_PERIPHERAL,
	89	};
	90	static struct clk spi1_clk = {
	91	.name = "spi1_clk",
	92	.pmc_mask = 1 << AT91SAM9263_ID_SPI1,
	93	.type = CLK_TYPE_PERIPHERAL,
	94	};
e8788bab AV	95	static struct clk ssc0_clk = {
	96	.name = "ssc0_clk",
	97	.pmc_mask = 1 << AT91SAM9263_ID_SSC0,
	98	.type = CLK_TYPE_PERIPHERAL,
	99	};
	100	static struct clk ssc1_clk = {
	101	.name = "ssc1_clk",
	102	.pmc_mask = 1 << AT91SAM9263_ID_SSC1,
	103	.type = CLK_TYPE_PERIPHERAL,
	104	};
	105	static struct clk ac97_clk = {
	106	.name = "ac97_clk",
	107	.pmc_mask = 1 << AT91SAM9263_ID_AC97C,
	108	.type = CLK_TYPE_PERIPHERAL,
	109	};
b2c65616 AV	110	static struct clk tcb_clk = {
	111	.name = "tcb_clk",
	112	.pmc_mask = 1 << AT91SAM9263_ID_TCB,
	113	.type = CLK_TYPE_PERIPHERAL,
	114	};
bb1ad68b AV	115	static struct clk pwm_clk = {
bb1ad68b AV	116	.name = "pwm_clk",
e8788bab AV	117	.pmc_mask = 1 << AT91SAM9263_ID_PWMC,
	118	.type = CLK_TYPE_PERIPHERAL,
	119	};
69b2e99c AV	120	static struct clk macb_clk = {
69b2e99c AV	121	.name = "macb_clk",
b2c65616 AV	122	.pmc_mask = 1 << AT91SAM9263_ID_EMAC,
	123	.type = CLK_TYPE_PERIPHERAL,
	124	};
e8788bab AV	125	static struct clk dma_clk = {
	126	.name = "dma_clk",
	127	.pmc_mask = 1 << AT91SAM9263_ID_DMA,
	128	.type = CLK_TYPE_PERIPHERAL,
	129	};
	130	static struct clk twodge_clk = {
	131	.name = "2dge_clk",
	132	.pmc_mask = 1 << AT91SAM9263_ID_2DGE,
	133	.type = CLK_TYPE_PERIPHERAL,
	134	};
b2c65616 AV	135	static struct clk udc_clk = {
	136	.name = "udc_clk",
	137	.pmc_mask = 1 << AT91SAM9263_ID_UDP,
	138	.type = CLK_TYPE_PERIPHERAL,
	139	};
	140	static struct clk isi_clk = {
	141	.name = "isi_clk",
	142	.pmc_mask = 1 << AT91SAM9263_ID_ISI,
	143	.type = CLK_TYPE_PERIPHERAL,
	144	};
	145	static struct clk lcdc_clk = {
	146	.name = "lcdc_clk",
7f6e2d99	147	.pmc_mask = 1 << AT91SAM9263_ID_LCDC,
b2c65616 AV	148	.type = CLK_TYPE_PERIPHERAL,
	149	};
	150	static struct clk ohci_clk = {
	151	.name = "ohci_clk",
	152	.pmc_mask = 1 << AT91SAM9263_ID_UHP,
	153	.type = CLK_TYPE_PERIPHERAL,
	154	};
	155
	156	static struct clk *periph_clocks[] __initdata = {
	157	&pioA_clk,
	158	&pioB_clk,
	159	&pioCDE_clk,
	160	&usart0_clk,
	161	&usart1_clk,
	162	&usart2_clk,
	163	&mmc0_clk,
	164	&mmc1_clk,
e8788bab	165	&can_clk,
b2c65616 AV	166	&twi_clk,
	167	&spi0_clk,
	168	&spi1_clk,
e8788bab AV	169	&ssc0_clk,
	170	&ssc1_clk,
	171	&ac97_clk,
b2c65616	172	&tcb_clk,
bb1ad68b	173	&pwm_clk,
69b2e99c	174	&macb_clk,
e8788bab	175	&twodge_clk,
b2c65616 AV	176	&udc_clk,
	177	&isi_clk,
	178	&lcdc_clk,
e8788bab	179	&dma_clk,
b2c65616 AV	180	&ohci_clk,
	181	// irq0 .. irq1
	182	};
	183
bd602995 JCPV	184	static struct clk_lookup periph_clocks_lookups[] = {
	185	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	186	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
	187	CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
	188	CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
	189	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	190	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	191	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
0af4316b JCPV	192	/* fake hclk clock */
0af4316b JCPV	193	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
bd602995 JCPV	194	};
	195
	196	static struct clk_lookup usart_clocks_lookups[] = {
	197	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	198	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	199	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	200	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	201	};
	202
b2c65616 AV	203	/*
	204	* The four programmable clocks.
	205	* You must configure pin multiplexing to bring these signals out.
	206	*/
	207	static struct clk pck0 = {
	208	.name = "pck0",
	209	.pmc_mask = AT91_PMC_PCK0,
	210	.type = CLK_TYPE_PROGRAMMABLE,
	211	.id = 0,
	212	};
	213	static struct clk pck1 = {
	214	.name = "pck1",
	215	.pmc_mask = AT91_PMC_PCK1,
	216	.type = CLK_TYPE_PROGRAMMABLE,
	217	.id = 1,
	218	};
	219	static struct clk pck2 = {
	220	.name = "pck2",
	221	.pmc_mask = AT91_PMC_PCK2,
	222	.type = CLK_TYPE_PROGRAMMABLE,
	223	.id = 2,
	224	};
	225	static struct clk pck3 = {
	226	.name = "pck3",
	227	.pmc_mask = AT91_PMC_PCK3,
	228	.type = CLK_TYPE_PROGRAMMABLE,
	229	.id = 3,
	230	};
	231
	232	static void __init at91sam9263_register_clocks(void)
	233	{
	234	int i;
	235
	236	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	237	clk_register(periph_clocks[i]);
	238
bd602995 JCPV	239	clkdev_add_table(periph_clocks_lookups,
	240	ARRAY_SIZE(periph_clocks_lookups));
	241	clkdev_add_table(usart_clocks_lookups,
	242	ARRAY_SIZE(usart_clocks_lookups));
	243
b2c65616 AV	244	clk_register(&pck0);
	245	clk_register(&pck1);
	246	clk_register(&pck2);
	247	clk_register(&pck3);
	248	}
	249
bd602995 JCPV	250	static struct clk_lookup console_clock_lookup;
	251
	252	void __init at91sam9263_set_console_clock(int id)
	253	{
	254	if (id >= ARRAY_SIZE(usart_clocks_lookups))
	255	return;
	256
	257	console_clock_lookup.con_id = "usart";
	258	console_clock_lookup.clk = usart_clocks_lookups[id].clk;
	259	clkdev_add(&console_clock_lookup);
	260	}
	261
b2c65616 AV	262	/* --------------------------------------------------------------------
	263	* GPIO
	264	* -------------------------------------------------------------------- */
	265
	266	static struct at91_gpio_bank at91sam9263_gpio[] = {
	267	{
	268	.id = AT91SAM9263_ID_PIOA,
	269	.offset = AT91_PIOA,
	270	.clock = &pioA_clk,
	271	}, {
	272	.id = AT91SAM9263_ID_PIOB,
	273	.offset = AT91_PIOB,
	274	.clock = &pioB_clk,
	275	}, {
	276	.id = AT91SAM9263_ID_PIOCDE,
	277	.offset = AT91_PIOC,
	278	.clock = &pioCDE_clk,
	279	}, {
	280	.id = AT91SAM9263_ID_PIOCDE,
	281	.offset = AT91_PIOD,
	282	.clock = &pioCDE_clk,
	283	}, {
	284	.id = AT91SAM9263_ID_PIOCDE,
	285	.offset = AT91_PIOE,
	286	.clock = &pioCDE_clk,
	287	}
	288	};
	289
3ef2fb42 AV	290	static void at91sam9263_poweroff(void)
	291	{
	292	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY \| AT91_SHDW_SHDW);
	293	}
	294
b2c65616 AV	295
	296	/* --------------------------------------------------------------------
	297	* AT91SAM9263 processor initialization
	298	* -------------------------------------------------------------------- */
	299
21d08b9d	300	static void __init at91sam9263_map_io(void)
b2c65616	301	{
f0051d82 JCPV	302	at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
f0051d82 JCPV	303	at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
1b021a3b	304	}
b2c65616	305
46539374	306	static void __init at91sam9263_initialize(void)
1b021a3b	307	{
bb413db5	308	at91_arch_reset = at91sam9_alt_reset;
3ef2fb42	309	pm_power_off = at91sam9263_poweroff;
b2c65616 AV	310	at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) \| (1 << AT91SAM9263_ID_IRQ1);
b2c65616 AV	311
b2c65616 AV	312	/* Register GPIO subsystem */
	313	at91_gpio_init(at91sam9263_gpio, 5);
	314	}
	315
	316	/* --------------------------------------------------------------------
	317	* Interrupt initialization
	318	* -------------------------------------------------------------------- */
	319
	320	/*
	321	* The default interrupt priority levels (0 = lowest, 7 = highest).
	322	*/
	323	static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
	324	7, /* Advanced Interrupt Controller (FIQ) */
	325	7, /* System Peripherals */
7cbed2b5 AV	326	1, /* Parallel IO Controller A */
	327	1, /* Parallel IO Controller B */
	328	1, /* Parallel IO Controller C, D and E */
b2c65616 AV	329	0,
b2c65616 AV	330	0,
7cbed2b5 AV	331	5, /* USART 0 */
	332	5, /* USART 1 */
	333	5, /* USART 2 */
b2c65616 AV	334	0, /* Multimedia Card Interface 0 */
b2c65616 AV	335	0, /* Multimedia Card Interface 1 */
7cbed2b5 AV	336	3, /* CAN */
	337	6, /* Two-Wire Interface */
	338	5, /* Serial Peripheral Interface 0 */
	339	5, /* Serial Peripheral Interface 1 */
	340	4, /* Serial Synchronous Controller 0 */
	341	4, /* Serial Synchronous Controller 1 */
	342	5, /* AC97 Controller */
b2c65616 AV	343	0, /* Timer Counter 0, 1 and 2 */
	344	0, /* Pulse Width Modulation Controller */
	345	3, /* Ethernet */
	346	0,
	347	0, /* 2D Graphic Engine */
7cbed2b5	348	2, /* USB Device Port */
b2c65616 AV	349	0, /* Image Sensor Interface */
	350	3, /* LDC Controller */
	351	0, /* DMA Controller */
	352	0,
7cbed2b5	353	2, /* USB Host port */
b2c65616 AV	354	0, /* Advanced Interrupt Controller (IRQ0) */
	355	0, /* Advanced Interrupt Controller (IRQ1) */
	356	};
	357
8c3583b6	358	struct at91_init_soc __initdata at91sam9263_soc = {
21d08b9d	359	.map_io = at91sam9263_map_io,
92100c12	360	.default_irq_priority = at91sam9263_default_irq_priority,
51ddec76	361	.register_clocks = at91sam9263_register_clocks,
21d08b9d JCPV	362	.init = at91sam9263_initialize,
21d08b9d JCPV	363	};