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Commit | Line | Data |
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1a0ed732 | 1 | /* |
ad48ce74 | 2 | * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x |
1a0ed732 AV |
3 | * |
4 | * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France | |
5 | * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France | |
ad48ce74 | 6 | * Converted to ClockSource/ClockEvents by David Brownell. |
1a0ed732 AV |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
52c3ffb0 | 12 | |
cffbfe63 MR |
13 | #define pr_fmt(fmt) "AT91: PIT: " fmt |
14 | ||
52c3ffb0 MR |
15 | #include <linux/clk.h> |
16 | #include <linux/clockchips.h> | |
1a0ed732 AV |
17 | #include <linux/interrupt.h> |
18 | #include <linux/irq.h> | |
19 | #include <linux/kernel.h> | |
23fa648f JCPV |
20 | #include <linux/of.h> |
21 | #include <linux/of_address.h> | |
22 | #include <linux/of_irq.h> | |
1a0ed732 | 23 | |
ac11a1d4 | 24 | #include <mach/hardware.h> |
1a0ed732 | 25 | |
ffe5cd8e | 26 | #define AT91_PIT_MR 0x00 /* Mode Register */ |
52c3ffb0 MR |
27 | #define AT91_PIT_PITIEN BIT(25) /* Timer Interrupt Enable */ |
28 | #define AT91_PIT_PITEN BIT(24) /* Timer Enabled */ | |
29 | #define AT91_PIT_PIV GENMASK(19, 0) /* Periodic Interval Value */ | |
ffe5cd8e JCPV |
30 | |
31 | #define AT91_PIT_SR 0x04 /* Status Register */ | |
52c3ffb0 | 32 | #define AT91_PIT_PITS BIT(0) /* Timer Status */ |
ffe5cd8e JCPV |
33 | |
34 | #define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */ | |
35 | #define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */ | |
52c3ffb0 MR |
36 | #define AT91_PIT_PICNT GENMASK(31, 20) /* Interval Counter */ |
37 | #define AT91_PIT_CPIV GENMASK(19, 0) /* Inverval Value */ | |
1a0ed732 AV |
38 | |
39 | #define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) | |
40 | #define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20) | |
41 | ||
ad48ce74 AV |
42 | static u32 pit_cycle; /* write-once */ |
43 | static u32 pit_cnt; /* access only w/system irq blocked */ | |
4ab0c599 | 44 | static void __iomem *pit_base_addr __read_mostly; |
7034be87 | 45 | static struct clk *mck; |
ad48ce74 | 46 | |
4ab0c599 JCPV |
47 | static inline unsigned int pit_read(unsigned int reg_offset) |
48 | { | |
49 | return __raw_readl(pit_base_addr + reg_offset); | |
50 | } | |
51 | ||
52 | static inline void pit_write(unsigned int reg_offset, unsigned long value) | |
53 | { | |
54 | __raw_writel(value, pit_base_addr + reg_offset); | |
55 | } | |
ad48ce74 | 56 | |
1a0ed732 | 57 | /* |
ad48ce74 AV |
58 | * Clocksource: just a monotonic counter of MCK/16 cycles. |
59 | * We don't care whether or not PIT irqs are enabled. | |
1a0ed732 | 60 | */ |
8e19608e | 61 | static cycle_t read_pit_clk(struct clocksource *cs) |
1a0ed732 | 62 | { |
ad48ce74 AV |
63 | unsigned long flags; |
64 | u32 elapsed; | |
65 | u32 t; | |
66 | ||
67 | raw_local_irq_save(flags); | |
68 | elapsed = pit_cnt; | |
4ab0c599 | 69 | t = pit_read(AT91_PIT_PIIR); |
ad48ce74 AV |
70 | raw_local_irq_restore(flags); |
71 | ||
72 | elapsed += PIT_PICNT(t) * pit_cycle; | |
73 | elapsed += PIT_CPIV(t); | |
74 | return elapsed; | |
75 | } | |
76 | ||
77 | static struct clocksource pit_clk = { | |
78 | .name = "pit", | |
79 | .rating = 175, | |
80 | .read = read_pit_clk, | |
ad48ce74 AV |
81 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
82 | }; | |
1a0ed732 | 83 | |
1a0ed732 | 84 | |
ad48ce74 AV |
85 | /* |
86 | * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16) | |
87 | */ | |
88 | static void | |
89 | pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) | |
90 | { | |
ad48ce74 AV |
91 | switch (mode) { |
92 | case CLOCK_EVT_MODE_PERIODIC: | |
501d7038 | 93 | /* update clocksource counter */ |
4ab0c599 JCPV |
94 | pit_cnt += pit_cycle * PIT_PICNT(pit_read(AT91_PIT_PIVR)); |
95 | pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN | |
ad48ce74 | 96 | | AT91_PIT_PITIEN); |
ad48ce74 AV |
97 | break; |
98 | case CLOCK_EVT_MODE_ONESHOT: | |
99 | BUG(); | |
100 | /* FALLTHROUGH */ | |
101 | case CLOCK_EVT_MODE_SHUTDOWN: | |
102 | case CLOCK_EVT_MODE_UNUSED: | |
103 | /* disable irq, leaving the clocksource active */ | |
4ab0c599 | 104 | pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); |
ad48ce74 AV |
105 | break; |
106 | case CLOCK_EVT_MODE_RESUME: | |
107 | break; | |
108 | } | |
1a0ed732 AV |
109 | } |
110 | ||
49356ae9 SW |
111 | static void at91sam926x_pit_suspend(struct clock_event_device *cedev) |
112 | { | |
113 | /* Disable timer */ | |
114 | pit_write(AT91_PIT_MR, 0); | |
115 | } | |
116 | ||
117 | static void at91sam926x_pit_reset(void) | |
118 | { | |
119 | /* Disable timer and irqs */ | |
120 | pit_write(AT91_PIT_MR, 0); | |
121 | ||
122 | /* Clear any pending interrupts, wait for PIT to stop counting */ | |
123 | while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0) | |
124 | cpu_relax(); | |
125 | ||
126 | /* Start PIT but don't enable IRQ */ | |
127 | pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); | |
128 | } | |
129 | ||
130 | static void at91sam926x_pit_resume(struct clock_event_device *cedev) | |
131 | { | |
132 | at91sam926x_pit_reset(); | |
133 | } | |
134 | ||
ad48ce74 AV |
135 | static struct clock_event_device pit_clkevt = { |
136 | .name = "pit", | |
137 | .features = CLOCK_EVT_FEAT_PERIODIC, | |
138 | .shift = 32, | |
139 | .rating = 100, | |
ad48ce74 | 140 | .set_mode = pit_clkevt_mode, |
49356ae9 SW |
141 | .suspend = at91sam926x_pit_suspend, |
142 | .resume = at91sam926x_pit_resume, | |
ad48ce74 AV |
143 | }; |
144 | ||
145 | ||
1a0ed732 AV |
146 | /* |
147 | * IRQ handler for the timer. | |
148 | */ | |
ad48ce74 | 149 | static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id) |
1a0ed732 | 150 | { |
501d7038 UKK |
151 | /* |
152 | * irqs should be disabled here, but as the irq is shared they are only | |
153 | * guaranteed to be off if the timer irq is registered first. | |
154 | */ | |
155 | WARN_ON_ONCE(!irqs_disabled()); | |
1a0ed732 | 156 | |
ad48ce74 AV |
157 | /* The PIT interrupt may be disabled, and is shared */ |
158 | if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC) | |
4ab0c599 | 159 | && (pit_read(AT91_PIT_SR) & AT91_PIT_PITS)) { |
ad48ce74 AV |
160 | unsigned nr_ticks; |
161 | ||
162 | /* Get number of ticks performed before irq, and ack it */ | |
4ab0c599 | 163 | nr_ticks = PIT_PICNT(pit_read(AT91_PIT_PIVR)); |
1a0ed732 | 164 | do { |
ad48ce74 AV |
165 | pit_cnt += pit_cycle; |
166 | pit_clkevt.event_handler(&pit_clkevt); | |
1a0ed732 AV |
167 | nr_ticks--; |
168 | } while (nr_ticks); | |
169 | ||
1a0ed732 | 170 | return IRQ_HANDLED; |
ad48ce74 AV |
171 | } |
172 | ||
173 | return IRQ_NONE; | |
1a0ed732 AV |
174 | } |
175 | ||
1a0ed732 | 176 | /* |
ad48ce74 | 177 | * Set up both clocksource and clockevent support. |
1a0ed732 | 178 | */ |
7f282e01 | 179 | static void __init at91sam926x_pit_common_init(unsigned int pit_irq) |
1a0ed732 | 180 | { |
ad48ce74 AV |
181 | unsigned long pit_rate; |
182 | unsigned bits; | |
986c2657 | 183 | int ret; |
ad48ce74 AV |
184 | |
185 | /* | |
186 | * Use our actual MCK to figure out how many MCK/16 ticks per | |
187 | * 1/HZ period (instead of a compile-time constant LATCH). | |
188 | */ | |
7034be87 | 189 | pit_rate = clk_get_rate(mck) / 16; |
2d7fdbe2 | 190 | pit_cycle = DIV_ROUND_CLOSEST(pit_rate, HZ); |
ad48ce74 | 191 | WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0); |
1a0ed732 | 192 | |
ad48ce74 AV |
193 | /* Initialize and enable the timer */ |
194 | at91sam926x_pit_reset(); | |
195 | ||
196 | /* | |
197 | * Register clocksource. The high order bits of PIV are unused, | |
198 | * so this isn't a 32-bit counter unless we get clockevent irqs. | |
199 | */ | |
ad48ce74 AV |
200 | bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */; |
201 | pit_clk.mask = CLOCKSOURCE_MASK(bits); | |
132b1632 | 202 | clocksource_register_hz(&pit_clk, pit_rate); |
ad48ce74 AV |
203 | |
204 | /* Set up irq handler */ | |
7f282e01 MR |
205 | ret = request_irq(pit_irq, at91sam926x_pit_interrupt, |
206 | IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL, | |
207 | "at91_tick", pit_base_addr); | |
986c2657 | 208 | if (ret) |
cffbfe63 | 209 | panic(pr_fmt("Unable to setup IRQ\n")); |
ad48ce74 AV |
210 | |
211 | /* Set up and register clockevents */ | |
212 | pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift); | |
320ab2b0 | 213 | pit_clkevt.cpumask = cpumask_of(0); |
ad48ce74 | 214 | clockevents_register_device(&pit_clkevt); |
1a0ed732 AV |
215 | } |
216 | ||
f807a89c MR |
217 | static void __init at91sam926x_pit_dt_init(struct device_node *node) |
218 | { | |
219 | unsigned int irq; | |
220 | ||
221 | pit_base_addr = of_iomap(node, 0); | |
222 | if (!pit_base_addr) | |
cffbfe63 | 223 | panic(pr_fmt("Could not map PIT address\n")); |
f807a89c MR |
224 | |
225 | mck = of_clk_get(node, 0); | |
226 | if (IS_ERR(mck)) | |
227 | /* Fallback on clkdev for !CCF-based boards */ | |
228 | mck = clk_get(NULL, "mck"); | |
229 | ||
230 | if (IS_ERR(mck)) | |
cffbfe63 | 231 | panic(pr_fmt("Unable to get mck clk\n")); |
f807a89c MR |
232 | |
233 | /* Get the interrupts property */ | |
234 | irq = irq_of_parse_and_map(node, 0); | |
a981b29f | 235 | if (!irq) |
cffbfe63 | 236 | panic(pr_fmt("Unable to get IRQ from DT\n")); |
f807a89c | 237 | |
7f282e01 | 238 | at91sam926x_pit_common_init(irq); |
f807a89c MR |
239 | } |
240 | CLOCKSOURCE_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit", | |
241 | at91sam926x_pit_dt_init); | |
242 | ||
243 | void __init at91sam926x_pit_init(void) | |
244 | { | |
245 | mck = clk_get(NULL, "mck"); | |
246 | if (IS_ERR(mck)) | |
cffbfe63 | 247 | panic(pr_fmt("Unable to get mck clk\n")); |
f807a89c | 248 | |
7f282e01 | 249 | at91sam926x_pit_common_init(NR_IRQS_LEGACY + AT91_ID_SYS); |
f807a89c MR |
250 | } |
251 | ||
4ab0c599 JCPV |
252 | void __init at91sam926x_ioremap_pit(u32 addr) |
253 | { | |
a7d84d73 | 254 | if (of_have_populated_dt()) |
23fa648f | 255 | return; |
a7d84d73 | 256 | |
4ab0c599 JCPV |
257 | pit_base_addr = ioremap(addr, 16); |
258 | ||
259 | if (!pit_base_addr) | |
cffbfe63 | 260 | panic(pr_fmt("Impossible to ioremap PIT\n")); |
1a0ed732 | 261 | } |