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877d7720 AV |
1 | /* |
2 | * Copyright (C) 2007 Atmel Corporation | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file COPYING in the main directory of this archive for | |
6 | * more details. | |
7 | */ | |
8 | ||
9 | #include <asm/mach/arch.h> | |
10 | #include <asm/mach/map.h> | |
11 | ||
c6686ff9 | 12 | #include <linux/dma-mapping.h> |
2f8163ba | 13 | #include <linux/gpio.h> |
877d7720 | 14 | #include <linux/platform_device.h> |
f230d3f5 | 15 | #include <linux/i2c-gpio.h> |
877d7720 | 16 | |
f230d3f5 | 17 | #include <linux/fb.h> |
877d7720 AV |
18 | #include <video/atmel_lcdc.h> |
19 | ||
a09e64fb | 20 | #include <mach/board.h> |
a09e64fb RK |
21 | #include <mach/at91sam9rl.h> |
22 | #include <mach/at91sam9rl_matrix.h> | |
4342d647 | 23 | #include <mach/at91_matrix.h> |
a09e64fb | 24 | #include <mach/at91sam9_smc.h> |
7cdc39ee | 25 | #include <linux/platform_data/dma-atmel.h> |
877d7720 AV |
26 | |
27 | #include "generic.h" | |
28 | ||
877d7720 | 29 | |
6ff89e9d NF |
30 | /* -------------------------------------------------------------------- |
31 | * HDMAC - AHB DMA Controller | |
32 | * -------------------------------------------------------------------- */ | |
33 | ||
34 | #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE) | |
35 | static u64 hdmac_dmamask = DMA_BIT_MASK(32); | |
36 | ||
6ff89e9d NF |
37 | static struct resource hdmac_resources[] = { |
38 | [0] = { | |
9627b200 JCPV |
39 | .start = AT91SAM9RL_BASE_DMA, |
40 | .end = AT91SAM9RL_BASE_DMA + SZ_512 - 1, | |
6ff89e9d NF |
41 | .flags = IORESOURCE_MEM, |
42 | }, | |
43 | [2] = { | |
8fe82a55 LD |
44 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA, |
45 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA, | |
6ff89e9d NF |
46 | .flags = IORESOURCE_IRQ, |
47 | }, | |
48 | }; | |
49 | ||
50 | static struct platform_device at_hdmac_device = { | |
bdad0b9a | 51 | .name = "at91sam9rl_dma", |
6ff89e9d NF |
52 | .id = -1, |
53 | .dev = { | |
54 | .dma_mask = &hdmac_dmamask, | |
55 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
6ff89e9d NF |
56 | }, |
57 | .resource = hdmac_resources, | |
58 | .num_resources = ARRAY_SIZE(hdmac_resources), | |
59 | }; | |
60 | ||
61 | void __init at91_add_device_hdmac(void) | |
62 | { | |
6ff89e9d NF |
63 | platform_device_register(&at_hdmac_device); |
64 | } | |
65 | #else | |
66 | void __init at91_add_device_hdmac(void) {} | |
67 | #endif | |
68 | ||
ba45ca43 NF |
69 | /* -------------------------------------------------------------------- |
70 | * USB HS Device (Gadget) | |
71 | * -------------------------------------------------------------------- */ | |
72 | ||
dd0b3825 | 73 | #if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE) |
ba45ca43 NF |
74 | |
75 | static struct resource usba_udc_resources[] = { | |
76 | [0] = { | |
77 | .start = AT91SAM9RL_UDPHS_FIFO, | |
78 | .end = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1, | |
79 | .flags = IORESOURCE_MEM, | |
80 | }, | |
81 | [1] = { | |
82 | .start = AT91SAM9RL_BASE_UDPHS, | |
83 | .end = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1, | |
84 | .flags = IORESOURCE_MEM, | |
85 | }, | |
86 | [2] = { | |
8fe82a55 LD |
87 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS, |
88 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS, | |
ba45ca43 NF |
89 | .flags = IORESOURCE_IRQ, |
90 | }, | |
91 | }; | |
92 | ||
93 | #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \ | |
94 | [idx] = { \ | |
95 | .name = nam, \ | |
96 | .index = idx, \ | |
97 | .fifo_size = maxpkt, \ | |
98 | .nr_banks = maxbk, \ | |
99 | .can_dma = dma, \ | |
100 | .can_isoc = isoc, \ | |
101 | } | |
102 | ||
103 | static struct usba_ep_data usba_udc_ep[] __initdata = { | |
104 | EP("ep0", 0, 64, 1, 0, 0), | |
105 | EP("ep1", 1, 1024, 2, 1, 1), | |
106 | EP("ep2", 2, 1024, 2, 1, 1), | |
107 | EP("ep3", 3, 1024, 3, 1, 0), | |
108 | EP("ep4", 4, 1024, 3, 1, 0), | |
109 | EP("ep5", 5, 1024, 3, 1, 1), | |
110 | EP("ep6", 6, 1024, 3, 1, 1), | |
111 | }; | |
112 | ||
113 | #undef EP | |
114 | ||
115 | /* | |
116 | * pdata doesn't have room for any endpoints, so we need to | |
117 | * append room for the ones we need right after it. | |
118 | */ | |
119 | static struct { | |
120 | struct usba_platform_data pdata; | |
121 | struct usba_ep_data ep[7]; | |
122 | } usba_udc_data; | |
123 | ||
124 | static struct platform_device at91_usba_udc_device = { | |
125 | .name = "atmel_usba_udc", | |
126 | .id = -1, | |
127 | .dev = { | |
128 | .platform_data = &usba_udc_data.pdata, | |
129 | }, | |
130 | .resource = usba_udc_resources, | |
131 | .num_resources = ARRAY_SIZE(usba_udc_resources), | |
132 | }; | |
133 | ||
134 | void __init at91_add_device_usba(struct usba_platform_data *data) | |
135 | { | |
136 | /* | |
137 | * Invalid pins are 0 on AT91, but the usba driver is shared | |
138 | * with AVR32, which use negative values instead. Once/if | |
139 | * gpio_is_valid() is ported to AT91, revisit this code. | |
140 | */ | |
141 | usba_udc_data.pdata.vbus_pin = -EINVAL; | |
142 | usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep); | |
6eab04a8 | 143 | memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep)); |
ba45ca43 | 144 | |
cc9f9aef | 145 | if (data && gpio_is_valid(data->vbus_pin)) { |
ba45ca43 NF |
146 | at91_set_gpio_input(data->vbus_pin, 0); |
147 | at91_set_deglitch(data->vbus_pin, 1); | |
148 | usba_udc_data.pdata.vbus_pin = data->vbus_pin; | |
149 | } | |
150 | ||
151 | /* Pullup pin is handled internally by USB device peripheral */ | |
152 | ||
ba45ca43 NF |
153 | platform_device_register(&at91_usba_udc_device); |
154 | } | |
155 | #else | |
156 | void __init at91_add_device_usba(struct usba_platform_data *data) {} | |
157 | #endif | |
158 | ||
159 | ||
877d7720 AV |
160 | /* -------------------------------------------------------------------- |
161 | * MMC / SD | |
162 | * -------------------------------------------------------------------- */ | |
163 | ||
4cf3326a | 164 | #if IS_ENABLED(CONFIG_MMC_ATMELMCI) |
c6686ff9 | 165 | static u64 mmc_dmamask = DMA_BIT_MASK(32); |
4cf3326a | 166 | static struct mci_platform_data mmc_data; |
877d7720 AV |
167 | |
168 | static struct resource mmc_resources[] = { | |
169 | [0] = { | |
170 | .start = AT91SAM9RL_BASE_MCI, | |
171 | .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1, | |
172 | .flags = IORESOURCE_MEM, | |
173 | }, | |
174 | [1] = { | |
8fe82a55 LD |
175 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI, |
176 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI, | |
877d7720 AV |
177 | .flags = IORESOURCE_IRQ, |
178 | }, | |
179 | }; | |
180 | ||
181 | static struct platform_device at91sam9rl_mmc_device = { | |
4cf3326a | 182 | .name = "atmel_mci", |
877d7720 AV |
183 | .id = -1, |
184 | .dev = { | |
185 | .dma_mask = &mmc_dmamask, | |
c6686ff9 | 186 | .coherent_dma_mask = DMA_BIT_MASK(32), |
877d7720 AV |
187 | .platform_data = &mmc_data, |
188 | }, | |
189 | .resource = mmc_resources, | |
190 | .num_resources = ARRAY_SIZE(mmc_resources), | |
191 | }; | |
192 | ||
4cf3326a | 193 | void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) |
877d7720 AV |
194 | { |
195 | if (!data) | |
196 | return; | |
197 | ||
4cf3326a LD |
198 | if (data->slot[0].bus_width) { |
199 | /* input/irq */ | |
200 | if (gpio_is_valid(data->slot[0].detect_pin)) { | |
201 | at91_set_gpio_input(data->slot[0].detect_pin, 1); | |
202 | at91_set_deglitch(data->slot[0].detect_pin, 1); | |
203 | } | |
204 | if (gpio_is_valid(data->slot[0].wp_pin)) | |
205 | at91_set_gpio_input(data->slot[0].wp_pin, 1); | |
206 | ||
207 | /* CLK */ | |
208 | at91_set_A_periph(AT91_PIN_PA2, 0); | |
209 | ||
210 | /* CMD */ | |
211 | at91_set_A_periph(AT91_PIN_PA1, 1); | |
212 | ||
213 | /* DAT0, maybe DAT1..DAT3 */ | |
214 | at91_set_A_periph(AT91_PIN_PA0, 1); | |
215 | if (data->slot[0].bus_width == 4) { | |
216 | at91_set_A_periph(AT91_PIN_PA3, 1); | |
217 | at91_set_A_periph(AT91_PIN_PA4, 1); | |
218 | at91_set_A_periph(AT91_PIN_PA5, 1); | |
219 | } | |
220 | ||
221 | mmc_data = *data; | |
222 | platform_device_register(&at91sam9rl_mmc_device); | |
877d7720 | 223 | } |
877d7720 AV |
224 | } |
225 | #else | |
4cf3326a | 226 | void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {} |
877d7720 AV |
227 | #endif |
228 | ||
229 | ||
230 | /* -------------------------------------------------------------------- | |
231 | * NAND / SmartMedia | |
232 | * -------------------------------------------------------------------- */ | |
233 | ||
f6ed6f78 | 234 | #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE) |
3c3796cc | 235 | static struct atmel_nand_data nand_data; |
877d7720 AV |
236 | |
237 | #define NAND_BASE AT91_CHIPSELECT_3 | |
238 | ||
239 | static struct resource nand_resources[] = { | |
d7a2415f | 240 | [0] = { |
877d7720 AV |
241 | .start = NAND_BASE, |
242 | .end = NAND_BASE + SZ_256M - 1, | |
243 | .flags = IORESOURCE_MEM, | |
d7a2415f AV |
244 | }, |
245 | [1] = { | |
d28edd1b JCPV |
246 | .start = AT91SAM9RL_BASE_ECC, |
247 | .end = AT91SAM9RL_BASE_ECC + SZ_512 - 1, | |
d7a2415f | 248 | .flags = IORESOURCE_MEM, |
877d7720 AV |
249 | } |
250 | }; | |
251 | ||
3c3796cc HS |
252 | static struct platform_device atmel_nand_device = { |
253 | .name = "atmel_nand", | |
877d7720 AV |
254 | .id = -1, |
255 | .dev = { | |
256 | .platform_data = &nand_data, | |
257 | }, | |
258 | .resource = nand_resources, | |
259 | .num_resources = ARRAY_SIZE(nand_resources), | |
260 | }; | |
261 | ||
3c3796cc | 262 | void __init at91_add_device_nand(struct atmel_nand_data *data) |
877d7720 AV |
263 | { |
264 | unsigned long csa; | |
265 | ||
266 | if (!data) | |
267 | return; | |
268 | ||
4342d647 JCPV |
269 | csa = at91_matrix_read(AT91_MATRIX_EBICSA); |
270 | at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); | |
877d7720 | 271 | |
877d7720 | 272 | /* enable pin */ |
cc9f9aef | 273 | if (gpio_is_valid(data->enable_pin)) |
877d7720 AV |
274 | at91_set_gpio_output(data->enable_pin, 1); |
275 | ||
276 | /* ready/busy pin */ | |
cc9f9aef | 277 | if (gpio_is_valid(data->rdy_pin)) |
877d7720 AV |
278 | at91_set_gpio_input(data->rdy_pin, 1); |
279 | ||
280 | /* card detect pin */ | |
cc9f9aef | 281 | if (gpio_is_valid(data->det_pin)) |
877d7720 AV |
282 | at91_set_gpio_input(data->det_pin, 1); |
283 | ||
284 | at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */ | |
285 | at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */ | |
286 | ||
287 | nand_data = *data; | |
3c3796cc | 288 | platform_device_register(&atmel_nand_device); |
877d7720 AV |
289 | } |
290 | ||
291 | #else | |
3c3796cc | 292 | void __init at91_add_device_nand(struct atmel_nand_data *data) {} |
877d7720 AV |
293 | #endif |
294 | ||
295 | ||
296 | /* -------------------------------------------------------------------- | |
297 | * TWI (i2c) | |
298 | * -------------------------------------------------------------------- */ | |
299 | ||
f230d3f5 AV |
300 | /* |
301 | * Prefer the GPIO code since the TWI controller isn't robust | |
302 | * (gets overruns and underruns under load) and can only issue | |
303 | * repeated STARTs in one scenario (the driver doesn't yet handle them). | |
304 | */ | |
305 | #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) | |
306 | ||
307 | static struct i2c_gpio_platform_data pdata = { | |
308 | .sda_pin = AT91_PIN_PA23, | |
309 | .sda_is_open_drain = 1, | |
310 | .scl_pin = AT91_PIN_PA24, | |
311 | .scl_is_open_drain = 1, | |
312 | .udelay = 2, /* ~100 kHz */ | |
313 | }; | |
314 | ||
315 | static struct platform_device at91sam9rl_twi_device = { | |
316 | .name = "i2c-gpio", | |
7840487c | 317 | .id = 0, |
f230d3f5 AV |
318 | .dev.platform_data = &pdata, |
319 | }; | |
320 | ||
321 | void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) | |
322 | { | |
323 | at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */ | |
324 | at91_set_multi_drive(AT91_PIN_PA23, 1); | |
325 | ||
326 | at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */ | |
327 | at91_set_multi_drive(AT91_PIN_PA24, 1); | |
328 | ||
329 | i2c_register_board_info(0, devices, nr_devices); | |
330 | platform_device_register(&at91sam9rl_twi_device); | |
331 | } | |
332 | ||
333 | #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) | |
877d7720 AV |
334 | |
335 | static struct resource twi_resources[] = { | |
336 | [0] = { | |
337 | .start = AT91SAM9RL_BASE_TWI0, | |
338 | .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1, | |
339 | .flags = IORESOURCE_MEM, | |
340 | }, | |
341 | [1] = { | |
8fe82a55 LD |
342 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0, |
343 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0, | |
877d7720 AV |
344 | .flags = IORESOURCE_IRQ, |
345 | }, | |
346 | }; | |
347 | ||
348 | static struct platform_device at91sam9rl_twi_device = { | |
fac368a0 | 349 | .name = "i2c-at91sam9g20", |
302090a6 | 350 | .id = 0, |
877d7720 AV |
351 | .resource = twi_resources, |
352 | .num_resources = ARRAY_SIZE(twi_resources), | |
353 | }; | |
354 | ||
f230d3f5 | 355 | void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) |
877d7720 AV |
356 | { |
357 | /* pins used for TWI interface */ | |
358 | at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */ | |
359 | at91_set_multi_drive(AT91_PIN_PA23, 1); | |
360 | ||
361 | at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */ | |
362 | at91_set_multi_drive(AT91_PIN_PA24, 1); | |
363 | ||
f230d3f5 | 364 | i2c_register_board_info(0, devices, nr_devices); |
877d7720 AV |
365 | platform_device_register(&at91sam9rl_twi_device); |
366 | } | |
367 | #else | |
f230d3f5 | 368 | void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {} |
877d7720 AV |
369 | #endif |
370 | ||
371 | ||
372 | /* -------------------------------------------------------------------- | |
373 | * SPI | |
374 | * -------------------------------------------------------------------- */ | |
375 | ||
376 | #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) | |
c6686ff9 | 377 | static u64 spi_dmamask = DMA_BIT_MASK(32); |
877d7720 AV |
378 | |
379 | static struct resource spi_resources[] = { | |
380 | [0] = { | |
381 | .start = AT91SAM9RL_BASE_SPI, | |
382 | .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1, | |
383 | .flags = IORESOURCE_MEM, | |
384 | }, | |
385 | [1] = { | |
8fe82a55 LD |
386 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI, |
387 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI, | |
877d7720 AV |
388 | .flags = IORESOURCE_IRQ, |
389 | }, | |
390 | }; | |
391 | ||
392 | static struct platform_device at91sam9rl_spi_device = { | |
393 | .name = "atmel_spi", | |
394 | .id = 0, | |
395 | .dev = { | |
396 | .dma_mask = &spi_dmamask, | |
c6686ff9 | 397 | .coherent_dma_mask = DMA_BIT_MASK(32), |
877d7720 AV |
398 | }, |
399 | .resource = spi_resources, | |
400 | .num_resources = ARRAY_SIZE(spi_resources), | |
401 | }; | |
402 | ||
403 | static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 }; | |
404 | ||
405 | ||
406 | void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) | |
407 | { | |
408 | int i; | |
409 | unsigned long cs_pin; | |
410 | ||
411 | at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */ | |
412 | at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */ | |
413 | at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */ | |
414 | ||
415 | /* Enable SPI chip-selects */ | |
416 | for (i = 0; i < nr_devices; i++) { | |
417 | if (devices[i].controller_data) | |
418 | cs_pin = (unsigned long) devices[i].controller_data; | |
419 | else | |
420 | cs_pin = spi_standard_cs[devices[i].chip_select]; | |
421 | ||
0c2c1f62 NF |
422 | if (!gpio_is_valid(cs_pin)) |
423 | continue; | |
424 | ||
877d7720 AV |
425 | /* enable chip-select pin */ |
426 | at91_set_gpio_output(cs_pin, 1); | |
427 | ||
428 | /* pass chip-select pin to driver */ | |
429 | devices[i].controller_data = (void *) cs_pin; | |
430 | } | |
431 | ||
432 | spi_register_board_info(devices, nr_devices); | |
433 | platform_device_register(&at91sam9rl_spi_device); | |
434 | } | |
435 | #else | |
436 | void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} | |
437 | #endif | |
438 | ||
439 | ||
439a3307 NF |
440 | /* -------------------------------------------------------------------- |
441 | * AC97 | |
442 | * -------------------------------------------------------------------- */ | |
443 | ||
444 | #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE) | |
445 | static u64 ac97_dmamask = DMA_BIT_MASK(32); | |
446 | static struct ac97c_platform_data ac97_data; | |
447 | ||
448 | static struct resource ac97_resources[] = { | |
449 | [0] = { | |
450 | .start = AT91SAM9RL_BASE_AC97C, | |
451 | .end = AT91SAM9RL_BASE_AC97C + SZ_16K - 1, | |
452 | .flags = IORESOURCE_MEM, | |
453 | }, | |
454 | [1] = { | |
8fe82a55 LD |
455 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C, |
456 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C, | |
439a3307 NF |
457 | .flags = IORESOURCE_IRQ, |
458 | }, | |
459 | }; | |
460 | ||
461 | static struct platform_device at91sam9rl_ac97_device = { | |
462 | .name = "atmel_ac97c", | |
463 | .id = 0, | |
464 | .dev = { | |
465 | .dma_mask = &ac97_dmamask, | |
466 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
467 | .platform_data = &ac97_data, | |
468 | }, | |
469 | .resource = ac97_resources, | |
470 | .num_resources = ARRAY_SIZE(ac97_resources), | |
471 | }; | |
472 | ||
473 | void __init at91_add_device_ac97(struct ac97c_platform_data *data) | |
474 | { | |
475 | if (!data) | |
476 | return; | |
477 | ||
478 | at91_set_A_periph(AT91_PIN_PD1, 0); /* AC97FS */ | |
479 | at91_set_A_periph(AT91_PIN_PD2, 0); /* AC97CK */ | |
480 | at91_set_A_periph(AT91_PIN_PD3, 0); /* AC97TX */ | |
481 | at91_set_A_periph(AT91_PIN_PD4, 0); /* AC97RX */ | |
482 | ||
483 | /* reset */ | |
cc9f9aef | 484 | if (gpio_is_valid(data->reset_pin)) |
439a3307 NF |
485 | at91_set_gpio_output(data->reset_pin, 0); |
486 | ||
487 | ac97_data = *data; | |
488 | platform_device_register(&at91sam9rl_ac97_device); | |
489 | } | |
490 | #else | |
491 | void __init at91_add_device_ac97(struct ac97c_platform_data *data) {} | |
492 | #endif | |
493 | ||
494 | ||
877d7720 AV |
495 | /* -------------------------------------------------------------------- |
496 | * LCD Controller | |
497 | * -------------------------------------------------------------------- */ | |
498 | ||
499 | #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) | |
c6686ff9 | 500 | static u64 lcdc_dmamask = DMA_BIT_MASK(32); |
877d7720 AV |
501 | static struct atmel_lcdfb_info lcdc_data; |
502 | ||
503 | static struct resource lcdc_resources[] = { | |
504 | [0] = { | |
505 | .start = AT91SAM9RL_LCDC_BASE, | |
506 | .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1, | |
507 | .flags = IORESOURCE_MEM, | |
508 | }, | |
509 | [1] = { | |
8fe82a55 LD |
510 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC, |
511 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC, | |
877d7720 AV |
512 | .flags = IORESOURCE_IRQ, |
513 | }, | |
877d7720 AV |
514 | }; |
515 | ||
516 | static struct platform_device at91_lcdc_device = { | |
517 | .name = "atmel_lcdfb", | |
518 | .id = 0, | |
519 | .dev = { | |
520 | .dma_mask = &lcdc_dmamask, | |
c6686ff9 | 521 | .coherent_dma_mask = DMA_BIT_MASK(32), |
877d7720 AV |
522 | .platform_data = &lcdc_data, |
523 | }, | |
524 | .resource = lcdc_resources, | |
525 | .num_resources = ARRAY_SIZE(lcdc_resources), | |
526 | }; | |
527 | ||
528 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) | |
529 | { | |
530 | if (!data) { | |
531 | return; | |
532 | } | |
533 | ||
534 | at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */ | |
535 | at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */ | |
536 | at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */ | |
537 | at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */ | |
538 | at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */ | |
539 | at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */ | |
540 | at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */ | |
541 | at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */ | |
542 | at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */ | |
543 | at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */ | |
544 | at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */ | |
545 | at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */ | |
546 | at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */ | |
547 | at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */ | |
548 | at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */ | |
549 | at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */ | |
550 | at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */ | |
551 | at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */ | |
552 | at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */ | |
553 | at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */ | |
554 | at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */ | |
555 | ||
556 | lcdc_data = *data; | |
557 | platform_device_register(&at91_lcdc_device); | |
558 | } | |
559 | #else | |
560 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} | |
561 | #endif | |
562 | ||
563 | ||
e5f40bfa AV |
564 | /* -------------------------------------------------------------------- |
565 | * Timer/Counter block | |
566 | * -------------------------------------------------------------------- */ | |
567 | ||
568 | #ifdef CONFIG_ATMEL_TCLIB | |
569 | ||
570 | static struct resource tcb_resources[] = { | |
571 | [0] = { | |
572 | .start = AT91SAM9RL_BASE_TCB0, | |
573 | .end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1, | |
574 | .flags = IORESOURCE_MEM, | |
575 | }, | |
576 | [1] = { | |
8fe82a55 LD |
577 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0, |
578 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0, | |
e5f40bfa AV |
579 | .flags = IORESOURCE_IRQ, |
580 | }, | |
581 | [2] = { | |
8fe82a55 LD |
582 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1, |
583 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1, | |
e5f40bfa AV |
584 | .flags = IORESOURCE_IRQ, |
585 | }, | |
586 | [3] = { | |
8fe82a55 LD |
587 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2, |
588 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2, | |
e5f40bfa AV |
589 | .flags = IORESOURCE_IRQ, |
590 | }, | |
591 | }; | |
592 | ||
593 | static struct platform_device at91sam9rl_tcb_device = { | |
594 | .name = "atmel_tcb", | |
595 | .id = 0, | |
596 | .resource = tcb_resources, | |
597 | .num_resources = ARRAY_SIZE(tcb_resources), | |
598 | }; | |
599 | ||
600 | static void __init at91_add_device_tc(void) | |
601 | { | |
e5f40bfa AV |
602 | platform_device_register(&at91sam9rl_tcb_device); |
603 | } | |
604 | #else | |
605 | static void __init at91_add_device_tc(void) { } | |
606 | #endif | |
607 | ||
608 | ||
f7647e63 AV |
609 | /* -------------------------------------------------------------------- |
610 | * Touchscreen | |
611 | * -------------------------------------------------------------------- */ | |
612 | ||
613 | #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE) | |
614 | static u64 tsadcc_dmamask = DMA_BIT_MASK(32); | |
423c9b0d | 615 | static struct at91_tsadcc_data tsadcc_data; |
f7647e63 AV |
616 | |
617 | static struct resource tsadcc_resources[] = { | |
618 | [0] = { | |
619 | .start = AT91SAM9RL_BASE_TSC, | |
620 | .end = AT91SAM9RL_BASE_TSC + SZ_16K - 1, | |
621 | .flags = IORESOURCE_MEM, | |
622 | }, | |
623 | [1] = { | |
8fe82a55 LD |
624 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC, |
625 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC, | |
f7647e63 AV |
626 | .flags = IORESOURCE_IRQ, |
627 | } | |
628 | }; | |
629 | ||
630 | static struct platform_device at91sam9rl_tsadcc_device = { | |
631 | .name = "atmel_tsadcc", | |
632 | .id = -1, | |
633 | .dev = { | |
634 | .dma_mask = &tsadcc_dmamask, | |
635 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
423c9b0d | 636 | .platform_data = &tsadcc_data, |
f7647e63 AV |
637 | }, |
638 | .resource = tsadcc_resources, | |
639 | .num_resources = ARRAY_SIZE(tsadcc_resources), | |
640 | }; | |
641 | ||
423c9b0d | 642 | void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) |
f7647e63 | 643 | { |
423c9b0d NF |
644 | if (!data) |
645 | return; | |
646 | ||
f7647e63 AV |
647 | at91_set_A_periph(AT91_PIN_PA17, 0); /* AD0_XR */ |
648 | at91_set_A_periph(AT91_PIN_PA18, 0); /* AD1_XL */ | |
649 | at91_set_A_periph(AT91_PIN_PA19, 0); /* AD2_YT */ | |
650 | at91_set_A_periph(AT91_PIN_PA20, 0); /* AD3_TB */ | |
651 | ||
423c9b0d | 652 | tsadcc_data = *data; |
f7647e63 AV |
653 | platform_device_register(&at91sam9rl_tsadcc_device); |
654 | } | |
655 | #else | |
423c9b0d | 656 | void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {} |
f7647e63 AV |
657 | #endif |
658 | ||
659 | ||
884f5a6a AV |
660 | /* -------------------------------------------------------------------- |
661 | * RTC | |
662 | * -------------------------------------------------------------------- */ | |
663 | ||
664 | #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE) | |
665 | static struct platform_device at91sam9rl_rtc_device = { | |
666 | .name = "at91_rtc", | |
667 | .id = -1, | |
668 | .num_resources = 0, | |
669 | }; | |
670 | ||
671 | static void __init at91_add_device_rtc(void) | |
672 | { | |
673 | platform_device_register(&at91sam9rl_rtc_device); | |
674 | } | |
675 | #else | |
676 | static void __init at91_add_device_rtc(void) {} | |
677 | #endif | |
678 | ||
679 | ||
680 | /* -------------------------------------------------------------------- | |
681 | * RTT | |
682 | * -------------------------------------------------------------------- */ | |
683 | ||
684 | static struct resource rtt_resources[] = { | |
685 | { | |
eab5fd67 JCPV |
686 | .start = AT91SAM9RL_BASE_RTT, |
687 | .end = AT91SAM9RL_BASE_RTT + SZ_16 - 1, | |
884f5a6a | 688 | .flags = IORESOURCE_MEM, |
b3af8b49 JCPV |
689 | }, { |
690 | .flags = IORESOURCE_MEM, | |
e402af6c LD |
691 | }, { |
692 | .flags = IORESOURCE_IRQ, | |
884f5a6a AV |
693 | } |
694 | }; | |
695 | ||
696 | static struct platform_device at91sam9rl_rtt_device = { | |
697 | .name = "at91_rtt", | |
4fd9212c | 698 | .id = 0, |
884f5a6a | 699 | .resource = rtt_resources, |
884f5a6a AV |
700 | }; |
701 | ||
205056a3 JCPV |
702 | #if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9) |
703 | static void __init at91_add_device_rtt_rtc(void) | |
704 | { | |
705 | at91sam9rl_rtt_device.name = "rtc-at91sam9"; | |
b3af8b49 JCPV |
706 | /* |
707 | * The second resource is needed: | |
708 | * GPBR will serve as the storage for RTC time offset | |
709 | */ | |
e402af6c | 710 | at91sam9rl_rtt_device.num_resources = 3; |
b3af8b49 JCPV |
711 | rtt_resources[1].start = AT91SAM9RL_BASE_GPBR + |
712 | 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR; | |
713 | rtt_resources[1].end = rtt_resources[1].start + 3; | |
e402af6c LD |
714 | rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS; |
715 | rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS; | |
205056a3 JCPV |
716 | } |
717 | #else | |
b3af8b49 JCPV |
718 | static void __init at91_add_device_rtt_rtc(void) |
719 | { | |
720 | /* Only one resource is needed: RTT not used as RTC */ | |
721 | at91sam9rl_rtt_device.num_resources = 1; | |
722 | } | |
205056a3 JCPV |
723 | #endif |
724 | ||
884f5a6a AV |
725 | static void __init at91_add_device_rtt(void) |
726 | { | |
205056a3 | 727 | at91_add_device_rtt_rtc(); |
884f5a6a AV |
728 | platform_device_register(&at91sam9rl_rtt_device); |
729 | } | |
730 | ||
731 | ||
732 | /* -------------------------------------------------------------------- | |
733 | * Watchdog | |
734 | * -------------------------------------------------------------------- */ | |
735 | ||
2af29b78 | 736 | #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE) |
c1c30a29 JCPV |
737 | static struct resource wdt_resources[] = { |
738 | { | |
739 | .start = AT91SAM9RL_BASE_WDT, | |
740 | .end = AT91SAM9RL_BASE_WDT + SZ_16 - 1, | |
741 | .flags = IORESOURCE_MEM, | |
742 | } | |
743 | }; | |
744 | ||
884f5a6a AV |
745 | static struct platform_device at91sam9rl_wdt_device = { |
746 | .name = "at91_wdt", | |
747 | .id = -1, | |
c1c30a29 JCPV |
748 | .resource = wdt_resources, |
749 | .num_resources = ARRAY_SIZE(wdt_resources), | |
884f5a6a AV |
750 | }; |
751 | ||
752 | static void __init at91_add_device_watchdog(void) | |
753 | { | |
754 | platform_device_register(&at91sam9rl_wdt_device); | |
755 | } | |
756 | #else | |
757 | static void __init at91_add_device_watchdog(void) {} | |
758 | #endif | |
759 | ||
760 | ||
bb1ad68b AV |
761 | /* -------------------------------------------------------------------- |
762 | * PWM | |
763 | * --------------------------------------------------------------------*/ | |
764 | ||
765 | #if defined(CONFIG_ATMEL_PWM) | |
766 | static u32 pwm_mask; | |
767 | ||
768 | static struct resource pwm_resources[] = { | |
769 | [0] = { | |
770 | .start = AT91SAM9RL_BASE_PWMC, | |
771 | .end = AT91SAM9RL_BASE_PWMC + SZ_16K - 1, | |
772 | .flags = IORESOURCE_MEM, | |
773 | }, | |
774 | [1] = { | |
8fe82a55 LD |
775 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC, |
776 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC, | |
bb1ad68b AV |
777 | .flags = IORESOURCE_IRQ, |
778 | }, | |
779 | }; | |
780 | ||
781 | static struct platform_device at91sam9rl_pwm0_device = { | |
782 | .name = "atmel_pwm", | |
783 | .id = -1, | |
784 | .dev = { | |
785 | .platform_data = &pwm_mask, | |
786 | }, | |
787 | .resource = pwm_resources, | |
788 | .num_resources = ARRAY_SIZE(pwm_resources), | |
789 | }; | |
790 | ||
791 | void __init at91_add_device_pwm(u32 mask) | |
792 | { | |
793 | if (mask & (1 << AT91_PWM0)) | |
794 | at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM0 */ | |
795 | ||
796 | if (mask & (1 << AT91_PWM1)) | |
797 | at91_set_B_periph(AT91_PIN_PB9, 1); /* enable PWM1 */ | |
798 | ||
799 | if (mask & (1 << AT91_PWM2)) | |
800 | at91_set_B_periph(AT91_PIN_PD5, 1); /* enable PWM2 */ | |
801 | ||
802 | if (mask & (1 << AT91_PWM3)) | |
803 | at91_set_B_periph(AT91_PIN_PD8, 1); /* enable PWM3 */ | |
804 | ||
805 | pwm_mask = mask; | |
806 | ||
807 | platform_device_register(&at91sam9rl_pwm0_device); | |
808 | } | |
809 | #else | |
810 | void __init at91_add_device_pwm(u32 mask) {} | |
811 | #endif | |
812 | ||
813 | ||
bfbc3266 AV |
814 | /* -------------------------------------------------------------------- |
815 | * SSC -- Synchronous Serial Controller | |
816 | * -------------------------------------------------------------------- */ | |
817 | ||
818 | #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE) | |
819 | static u64 ssc0_dmamask = DMA_BIT_MASK(32); | |
820 | ||
821 | static struct resource ssc0_resources[] = { | |
822 | [0] = { | |
823 | .start = AT91SAM9RL_BASE_SSC0, | |
824 | .end = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1, | |
825 | .flags = IORESOURCE_MEM, | |
826 | }, | |
827 | [1] = { | |
8fe82a55 LD |
828 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0, |
829 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0, | |
bfbc3266 AV |
830 | .flags = IORESOURCE_IRQ, |
831 | }, | |
832 | }; | |
833 | ||
834 | static struct platform_device at91sam9rl_ssc0_device = { | |
636036d2 | 835 | .name = "at91rm9200_ssc", |
bfbc3266 AV |
836 | .id = 0, |
837 | .dev = { | |
838 | .dma_mask = &ssc0_dmamask, | |
839 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
840 | }, | |
841 | .resource = ssc0_resources, | |
842 | .num_resources = ARRAY_SIZE(ssc0_resources), | |
843 | }; | |
844 | ||
845 | static inline void configure_ssc0_pins(unsigned pins) | |
846 | { | |
847 | if (pins & ATMEL_SSC_TF) | |
848 | at91_set_A_periph(AT91_PIN_PC0, 1); | |
849 | if (pins & ATMEL_SSC_TK) | |
850 | at91_set_A_periph(AT91_PIN_PC1, 1); | |
851 | if (pins & ATMEL_SSC_TD) | |
852 | at91_set_A_periph(AT91_PIN_PA15, 1); | |
853 | if (pins & ATMEL_SSC_RD) | |
854 | at91_set_A_periph(AT91_PIN_PA16, 1); | |
855 | if (pins & ATMEL_SSC_RK) | |
856 | at91_set_B_periph(AT91_PIN_PA10, 1); | |
857 | if (pins & ATMEL_SSC_RF) | |
858 | at91_set_B_periph(AT91_PIN_PA22, 1); | |
859 | } | |
860 | ||
861 | static u64 ssc1_dmamask = DMA_BIT_MASK(32); | |
862 | ||
863 | static struct resource ssc1_resources[] = { | |
864 | [0] = { | |
865 | .start = AT91SAM9RL_BASE_SSC1, | |
866 | .end = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1, | |
867 | .flags = IORESOURCE_MEM, | |
868 | }, | |
869 | [1] = { | |
8fe82a55 LD |
870 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1, |
871 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1, | |
bfbc3266 AV |
872 | .flags = IORESOURCE_IRQ, |
873 | }, | |
874 | }; | |
875 | ||
876 | static struct platform_device at91sam9rl_ssc1_device = { | |
636036d2 | 877 | .name = "at91rm9200_ssc", |
bfbc3266 AV |
878 | .id = 1, |
879 | .dev = { | |
880 | .dma_mask = &ssc1_dmamask, | |
881 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
882 | }, | |
883 | .resource = ssc1_resources, | |
884 | .num_resources = ARRAY_SIZE(ssc1_resources), | |
885 | }; | |
886 | ||
887 | static inline void configure_ssc1_pins(unsigned pins) | |
888 | { | |
889 | if (pins & ATMEL_SSC_TF) | |
890 | at91_set_B_periph(AT91_PIN_PA29, 1); | |
891 | if (pins & ATMEL_SSC_TK) | |
892 | at91_set_B_periph(AT91_PIN_PA30, 1); | |
893 | if (pins & ATMEL_SSC_TD) | |
894 | at91_set_B_periph(AT91_PIN_PA13, 1); | |
895 | if (pins & ATMEL_SSC_RD) | |
896 | at91_set_B_periph(AT91_PIN_PA14, 1); | |
897 | if (pins & ATMEL_SSC_RK) | |
898 | at91_set_B_periph(AT91_PIN_PA9, 1); | |
899 | if (pins & ATMEL_SSC_RF) | |
900 | at91_set_B_periph(AT91_PIN_PA8, 1); | |
901 | } | |
902 | ||
903 | /* | |
bfbc3266 AV |
904 | * SSC controllers are accessed through library code, instead of any |
905 | * kind of all-singing/all-dancing driver. For example one could be | |
906 | * used by a particular I2S audio codec's driver, while another one | |
907 | * on the same system might be used by a custom data capture driver. | |
908 | */ | |
909 | void __init at91_add_device_ssc(unsigned id, unsigned pins) | |
910 | { | |
911 | struct platform_device *pdev; | |
912 | ||
913 | /* | |
914 | * NOTE: caller is responsible for passing information matching | |
915 | * "pins" to whatever will be using each particular controller. | |
916 | */ | |
917 | switch (id) { | |
918 | case AT91SAM9RL_ID_SSC0: | |
919 | pdev = &at91sam9rl_ssc0_device; | |
920 | configure_ssc0_pins(pins); | |
bfbc3266 AV |
921 | break; |
922 | case AT91SAM9RL_ID_SSC1: | |
923 | pdev = &at91sam9rl_ssc1_device; | |
924 | configure_ssc1_pins(pins); | |
bfbc3266 AV |
925 | break; |
926 | default: | |
927 | return; | |
928 | } | |
929 | ||
930 | platform_device_register(pdev); | |
931 | } | |
932 | ||
933 | #else | |
934 | void __init at91_add_device_ssc(unsigned id, unsigned pins) {} | |
935 | #endif | |
936 | ||
937 | ||
877d7720 AV |
938 | /* -------------------------------------------------------------------- |
939 | * UART | |
940 | * -------------------------------------------------------------------- */ | |
941 | ||
942 | #if defined(CONFIG_SERIAL_ATMEL) | |
943 | static struct resource dbgu_resources[] = { | |
944 | [0] = { | |
13079a73 JCPV |
945 | .start = AT91SAM9RL_BASE_DBGU, |
946 | .end = AT91SAM9RL_BASE_DBGU + SZ_512 - 1, | |
877d7720 AV |
947 | .flags = IORESOURCE_MEM, |
948 | }, | |
949 | [1] = { | |
8fe82a55 LD |
950 | .start = NR_IRQS_LEGACY + AT91_ID_SYS, |
951 | .end = NR_IRQS_LEGACY + AT91_ID_SYS, | |
877d7720 AV |
952 | .flags = IORESOURCE_IRQ, |
953 | }, | |
954 | }; | |
955 | ||
956 | static struct atmel_uart_data dbgu_data = { | |
957 | .use_dma_tx = 0, | |
958 | .use_dma_rx = 0, /* DBGU not capable of receive DMA */ | |
877d7720 AV |
959 | }; |
960 | ||
c6686ff9 AV |
961 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); |
962 | ||
877d7720 AV |
963 | static struct platform_device at91sam9rl_dbgu_device = { |
964 | .name = "atmel_usart", | |
965 | .id = 0, | |
966 | .dev = { | |
c6686ff9 AV |
967 | .dma_mask = &dbgu_dmamask, |
968 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
969 | .platform_data = &dbgu_data, | |
877d7720 AV |
970 | }, |
971 | .resource = dbgu_resources, | |
972 | .num_resources = ARRAY_SIZE(dbgu_resources), | |
973 | }; | |
974 | ||
975 | static inline void configure_dbgu_pins(void) | |
976 | { | |
977 | at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */ | |
978 | at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */ | |
979 | } | |
980 | ||
981 | static struct resource uart0_resources[] = { | |
982 | [0] = { | |
983 | .start = AT91SAM9RL_BASE_US0, | |
984 | .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1, | |
985 | .flags = IORESOURCE_MEM, | |
986 | }, | |
987 | [1] = { | |
8fe82a55 LD |
988 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0, |
989 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0, | |
877d7720 AV |
990 | .flags = IORESOURCE_IRQ, |
991 | }, | |
992 | }; | |
993 | ||
994 | static struct atmel_uart_data uart0_data = { | |
995 | .use_dma_tx = 1, | |
996 | .use_dma_rx = 1, | |
997 | }; | |
998 | ||
c6686ff9 AV |
999 | static u64 uart0_dmamask = DMA_BIT_MASK(32); |
1000 | ||
877d7720 AV |
1001 | static struct platform_device at91sam9rl_uart0_device = { |
1002 | .name = "atmel_usart", | |
1003 | .id = 1, | |
1004 | .dev = { | |
c6686ff9 AV |
1005 | .dma_mask = &uart0_dmamask, |
1006 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1007 | .platform_data = &uart0_data, | |
877d7720 AV |
1008 | }, |
1009 | .resource = uart0_resources, | |
1010 | .num_resources = ARRAY_SIZE(uart0_resources), | |
1011 | }; | |
1012 | ||
c8f385a6 | 1013 | static inline void configure_usart0_pins(unsigned pins) |
877d7720 AV |
1014 | { |
1015 | at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */ | |
1016 | at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */ | |
c8f385a6 AV |
1017 | |
1018 | if (pins & ATMEL_UART_RTS) | |
1019 | at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */ | |
1020 | if (pins & ATMEL_UART_CTS) | |
1021 | at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */ | |
1022 | if (pins & ATMEL_UART_DSR) | |
1023 | at91_set_A_periph(AT91_PIN_PD14, 0); /* DSR0 */ | |
1024 | if (pins & ATMEL_UART_DTR) | |
1025 | at91_set_A_periph(AT91_PIN_PD15, 0); /* DTR0 */ | |
1026 | if (pins & ATMEL_UART_DCD) | |
1027 | at91_set_A_periph(AT91_PIN_PD16, 0); /* DCD0 */ | |
1028 | if (pins & ATMEL_UART_RI) | |
1029 | at91_set_A_periph(AT91_PIN_PD17, 0); /* RI0 */ | |
877d7720 AV |
1030 | } |
1031 | ||
1032 | static struct resource uart1_resources[] = { | |
1033 | [0] = { | |
1034 | .start = AT91SAM9RL_BASE_US1, | |
1035 | .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1, | |
1036 | .flags = IORESOURCE_MEM, | |
1037 | }, | |
1038 | [1] = { | |
8fe82a55 LD |
1039 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1, |
1040 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1, | |
877d7720 AV |
1041 | .flags = IORESOURCE_IRQ, |
1042 | }, | |
1043 | }; | |
1044 | ||
1045 | static struct atmel_uart_data uart1_data = { | |
1046 | .use_dma_tx = 1, | |
1047 | .use_dma_rx = 1, | |
1048 | }; | |
1049 | ||
c6686ff9 AV |
1050 | static u64 uart1_dmamask = DMA_BIT_MASK(32); |
1051 | ||
877d7720 AV |
1052 | static struct platform_device at91sam9rl_uart1_device = { |
1053 | .name = "atmel_usart", | |
1054 | .id = 2, | |
1055 | .dev = { | |
c6686ff9 AV |
1056 | .dma_mask = &uart1_dmamask, |
1057 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1058 | .platform_data = &uart1_data, | |
877d7720 AV |
1059 | }, |
1060 | .resource = uart1_resources, | |
1061 | .num_resources = ARRAY_SIZE(uart1_resources), | |
1062 | }; | |
1063 | ||
c8f385a6 | 1064 | static inline void configure_usart1_pins(unsigned pins) |
877d7720 AV |
1065 | { |
1066 | at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */ | |
1067 | at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */ | |
c8f385a6 AV |
1068 | |
1069 | if (pins & ATMEL_UART_RTS) | |
1070 | at91_set_B_periph(AT91_PIN_PA18, 0); /* RTS1 */ | |
1071 | if (pins & ATMEL_UART_CTS) | |
1072 | at91_set_B_periph(AT91_PIN_PA19, 0); /* CTS1 */ | |
877d7720 AV |
1073 | } |
1074 | ||
1075 | static struct resource uart2_resources[] = { | |
1076 | [0] = { | |
1077 | .start = AT91SAM9RL_BASE_US2, | |
1078 | .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1, | |
1079 | .flags = IORESOURCE_MEM, | |
1080 | }, | |
1081 | [1] = { | |
8fe82a55 LD |
1082 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2, |
1083 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2, | |
877d7720 AV |
1084 | .flags = IORESOURCE_IRQ, |
1085 | }, | |
1086 | }; | |
1087 | ||
1088 | static struct atmel_uart_data uart2_data = { | |
1089 | .use_dma_tx = 1, | |
1090 | .use_dma_rx = 1, | |
1091 | }; | |
1092 | ||
c6686ff9 AV |
1093 | static u64 uart2_dmamask = DMA_BIT_MASK(32); |
1094 | ||
877d7720 AV |
1095 | static struct platform_device at91sam9rl_uart2_device = { |
1096 | .name = "atmel_usart", | |
1097 | .id = 3, | |
1098 | .dev = { | |
c6686ff9 AV |
1099 | .dma_mask = &uart2_dmamask, |
1100 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1101 | .platform_data = &uart2_data, | |
877d7720 AV |
1102 | }, |
1103 | .resource = uart2_resources, | |
1104 | .num_resources = ARRAY_SIZE(uart2_resources), | |
1105 | }; | |
1106 | ||
c8f385a6 | 1107 | static inline void configure_usart2_pins(unsigned pins) |
877d7720 AV |
1108 | { |
1109 | at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */ | |
1110 | at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */ | |
c8f385a6 AV |
1111 | |
1112 | if (pins & ATMEL_UART_RTS) | |
1113 | at91_set_A_periph(AT91_PIN_PA29, 0); /* RTS2 */ | |
1114 | if (pins & ATMEL_UART_CTS) | |
1115 | at91_set_A_periph(AT91_PIN_PA30, 0); /* CTS2 */ | |
877d7720 AV |
1116 | } |
1117 | ||
1118 | static struct resource uart3_resources[] = { | |
1119 | [0] = { | |
1120 | .start = AT91SAM9RL_BASE_US3, | |
1121 | .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1, | |
1122 | .flags = IORESOURCE_MEM, | |
1123 | }, | |
1124 | [1] = { | |
8fe82a55 LD |
1125 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3, |
1126 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3, | |
877d7720 AV |
1127 | .flags = IORESOURCE_IRQ, |
1128 | }, | |
1129 | }; | |
1130 | ||
1131 | static struct atmel_uart_data uart3_data = { | |
1132 | .use_dma_tx = 1, | |
1133 | .use_dma_rx = 1, | |
1134 | }; | |
1135 | ||
c6686ff9 AV |
1136 | static u64 uart3_dmamask = DMA_BIT_MASK(32); |
1137 | ||
877d7720 AV |
1138 | static struct platform_device at91sam9rl_uart3_device = { |
1139 | .name = "atmel_usart", | |
1140 | .id = 4, | |
1141 | .dev = { | |
c6686ff9 AV |
1142 | .dma_mask = &uart3_dmamask, |
1143 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1144 | .platform_data = &uart3_data, | |
877d7720 AV |
1145 | }, |
1146 | .resource = uart3_resources, | |
1147 | .num_resources = ARRAY_SIZE(uart3_resources), | |
1148 | }; | |
1149 | ||
c8f385a6 | 1150 | static inline void configure_usart3_pins(unsigned pins) |
877d7720 AV |
1151 | { |
1152 | at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */ | |
1153 | at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */ | |
c8f385a6 AV |
1154 | |
1155 | if (pins & ATMEL_UART_RTS) | |
1156 | at91_set_B_periph(AT91_PIN_PD4, 0); /* RTS3 */ | |
1157 | if (pins & ATMEL_UART_CTS) | |
1158 | at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */ | |
877d7720 AV |
1159 | } |
1160 | ||
11aadac4 | 1161 | static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ |
877d7720 | 1162 | |
c8f385a6 AV |
1163 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) |
1164 | { | |
1165 | struct platform_device *pdev; | |
2b348e2f | 1166 | struct atmel_uart_data *pdata; |
c8f385a6 AV |
1167 | |
1168 | switch (id) { | |
1169 | case 0: /* DBGU */ | |
1170 | pdev = &at91sam9rl_dbgu_device; | |
1171 | configure_dbgu_pins(); | |
c8f385a6 AV |
1172 | break; |
1173 | case AT91SAM9RL_ID_US0: | |
1174 | pdev = &at91sam9rl_uart0_device; | |
1175 | configure_usart0_pins(pins); | |
c8f385a6 AV |
1176 | break; |
1177 | case AT91SAM9RL_ID_US1: | |
1178 | pdev = &at91sam9rl_uart1_device; | |
1179 | configure_usart1_pins(pins); | |
c8f385a6 AV |
1180 | break; |
1181 | case AT91SAM9RL_ID_US2: | |
1182 | pdev = &at91sam9rl_uart2_device; | |
1183 | configure_usart2_pins(pins); | |
c8f385a6 AV |
1184 | break; |
1185 | case AT91SAM9RL_ID_US3: | |
1186 | pdev = &at91sam9rl_uart3_device; | |
1187 | configure_usart3_pins(pins); | |
c8f385a6 AV |
1188 | break; |
1189 | default: | |
1190 | return; | |
1191 | } | |
2b348e2f JCPV |
1192 | pdata = pdev->dev.platform_data; |
1193 | pdata->num = portnr; /* update to mapped ID */ | |
c8f385a6 AV |
1194 | |
1195 | if (portnr < ATMEL_MAX_UART) | |
1196 | at91_uarts[portnr] = pdev; | |
1197 | } | |
1198 | ||
877d7720 AV |
1199 | void __init at91_add_device_serial(void) |
1200 | { | |
1201 | int i; | |
1202 | ||
1203 | for (i = 0; i < ATMEL_MAX_UART; i++) { | |
1204 | if (at91_uarts[i]) | |
1205 | platform_device_register(at91_uarts[i]); | |
1206 | } | |
1207 | } | |
1208 | #else | |
c8f385a6 | 1209 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} |
877d7720 AV |
1210 | void __init at91_add_device_serial(void) {} |
1211 | #endif | |
1212 | ||
1213 | ||
1214 | /* -------------------------------------------------------------------- */ | |
1215 | ||
1216 | /* | |
1217 | * These devices are always present and don't need any board-specific | |
1218 | * setup. | |
1219 | */ | |
1220 | static int __init at91_add_standard_devices(void) | |
1221 | { | |
6ff89e9d | 1222 | at91_add_device_hdmac(); |
884f5a6a AV |
1223 | at91_add_device_rtc(); |
1224 | at91_add_device_rtt(); | |
1225 | at91_add_device_watchdog(); | |
e5f40bfa | 1226 | at91_add_device_tc(); |
877d7720 AV |
1227 | return 0; |
1228 | } | |
1229 | ||
1230 | arch_initcall(at91_add_standard_devices); |