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Merge branch 'sbp2-spindown' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee139...
[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-at91 / at91sam9rl_devices.c
CommitLineData
877d7720
AV		 1/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive for
6 * more details.
7 */
8
9#include <asm/mach/arch.h>
10#include <asm/mach/map.h>
11
c6686ff9 12#include <linux/dma-mapping.h>
877d7720 13#include <linux/platform_device.h>
f230d3f5 14#include <linux/i2c-gpio.h>
877d7720 15
f230d3f5 16#include <linux/fb.h>
877d7720
AV		 17#include <video/atmel_lcdc.h>
18
19#include <asm/arch/board.h>
20#include <asm/arch/gpio.h>
21#include <asm/arch/at91sam9rl.h>
22#include <asm/arch/at91sam9rl_matrix.h>
b78eabde 23#include <asm/arch/at91sam9_smc.h>
877d7720
AV		 24
25#include "generic.h"
26
877d7720 27
ba45ca43
NF		 28/* --------------------------------------------------------------------
29 * USB HS Device (Gadget)
30 * -------------------------------------------------------------------- */
31
32#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
33
34static struct resource usba_udc_resources[] = {
35 [0] = {
36 .start = AT91SAM9RL_UDPHS_FIFO,
37 .end = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1,
38 .flags = IORESOURCE_MEM,
39 },
40 [1] = {
41 .start = AT91SAM9RL_BASE_UDPHS,
42 .end = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1,
43 .flags = IORESOURCE_MEM,
44 },
45 [2] = {
46 .start = AT91SAM9RL_ID_UDPHS,
47 .end = AT91SAM9RL_ID_UDPHS,
48 .flags = IORESOURCE_IRQ,
49 },
50};
51
52#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
53 [idx] = { \
54 .name = nam, \
55 .index = idx, \
56 .fifo_size = maxpkt, \
57 .nr_banks = maxbk, \
58 .can_dma = dma, \
59 .can_isoc = isoc, \
60 }
61
62static struct usba_ep_data usba_udc_ep[] __initdata = {
63 EP("ep0", 0, 64, 1, 0, 0),
64 EP("ep1", 1, 1024, 2, 1, 1),
65 EP("ep2", 2, 1024, 2, 1, 1),
66 EP("ep3", 3, 1024, 3, 1, 0),
67 EP("ep4", 4, 1024, 3, 1, 0),
68 EP("ep5", 5, 1024, 3, 1, 1),
69 EP("ep6", 6, 1024, 3, 1, 1),
70};
71
72#undef EP
73
74/*
75 * pdata doesn't have room for any endpoints, so we need to
76 * append room for the ones we need right after it.
77 */
78static struct {
79 struct usba_platform_data pdata;
80 struct usba_ep_data ep[7];
81} usba_udc_data;
82
83static struct platform_device at91_usba_udc_device = {
84 .name = "atmel_usba_udc",
85 .id = -1,
86 .dev = {
87 .platform_data = &usba_udc_data.pdata,
88 },
89 .resource = usba_udc_resources,
90 .num_resources = ARRAY_SIZE(usba_udc_resources),
91};
92
93void __init at91_add_device_usba(struct usba_platform_data *data)
94{
95 /*
96 * Invalid pins are 0 on AT91, but the usba driver is shared
97 * with AVR32, which use negative values instead. Once/if
98 * gpio_is_valid() is ported to AT91, revisit this code.
99 */
100 usba_udc_data.pdata.vbus_pin = -EINVAL;
101 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
102 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
103
104 if (data && data->vbus_pin > 0) {
105 at91_set_gpio_input(data->vbus_pin, 0);
106 at91_set_deglitch(data->vbus_pin, 1);
107 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
108 }
109
110 /* Pullup pin is handled internally by USB device peripheral */
111
112 /* Clocks */
113 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
114 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
115
116 platform_device_register(&at91_usba_udc_device);
117}
118#else
119void __init at91_add_device_usba(struct usba_platform_data *data) {}
120#endif
121
122
877d7720
AV		 123/* --------------------------------------------------------------------
124 * MMC / SD
125 * -------------------------------------------------------------------- */
126
127#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
c6686ff9 128static u64 mmc_dmamask = DMA_BIT_MASK(32);
877d7720
AV		 129static struct at91_mmc_data mmc_data;
130
131static struct resource mmc_resources[] = {
132 [0] = {
133 .start = AT91SAM9RL_BASE_MCI,
134 .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
135 .flags = IORESOURCE_MEM,
136 },
137 [1] = {
138 .start = AT91SAM9RL_ID_MCI,
139 .end = AT91SAM9RL_ID_MCI,
140 .flags = IORESOURCE_IRQ,
141 },
142};
143
144static struct platform_device at91sam9rl_mmc_device = {
145 .name = "at91_mci",
146 .id = -1,
147 .dev = {
148 .dma_mask = &mmc_dmamask,
c6686ff9 149 .coherent_dma_mask = DMA_BIT_MASK(32),
877d7720
AV		 150 .platform_data = &mmc_data,
151 },
152 .resource = mmc_resources,
153 .num_resources = ARRAY_SIZE(mmc_resources),
154};
155
156void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
157{
158 if (!data)
159 return;
160
161 /* input/irq */
162 if (data->det_pin) {
163 at91_set_gpio_input(data->det_pin, 1);
164 at91_set_deglitch(data->det_pin, 1);
165 }
166 if (data->wp_pin)
167 at91_set_gpio_input(data->wp_pin, 1);
168 if (data->vcc_pin)
169 at91_set_gpio_output(data->vcc_pin, 0);
170
171 /* CLK */
172 at91_set_A_periph(AT91_PIN_PA2, 0);
173
174 /* CMD */
175 at91_set_A_periph(AT91_PIN_PA1, 1);
176
177 /* DAT0, maybe DAT1..DAT3 */
178 at91_set_A_periph(AT91_PIN_PA0, 1);
179 if (data->wire4) {
180 at91_set_A_periph(AT91_PIN_PA3, 1);
181 at91_set_A_periph(AT91_PIN_PA4, 1);
182 at91_set_A_periph(AT91_PIN_PA5, 1);
183 }
184
185 mmc_data = *data;
186 platform_device_register(&at91sam9rl_mmc_device);
187}
188#else
189void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
190#endif
191
192
193/* --------------------------------------------------------------------
194 * NAND / SmartMedia
195 * -------------------------------------------------------------------- */
196
197#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
198static struct at91_nand_data nand_data;
199
200#define NAND_BASE AT91_CHIPSELECT_3
201
202static struct resource nand_resources[] = {
d7a2415f 203 [0] = {
877d7720
AV		 204 .start = NAND_BASE,
205 .end = NAND_BASE + SZ_256M - 1,
206 .flags = IORESOURCE_MEM,
d7a2415f
AV		 207 },
208 [1] = {
209 .start = AT91_BASE_SYS + AT91_ECC,
210 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
211 .flags = IORESOURCE_MEM,
877d7720
AV		 212 }
213};
214
215static struct platform_device at91_nand_device = {
216 .name = "at91_nand",
217 .id = -1,
218 .dev = {
219 .platform_data = &nand_data,
220 },
221 .resource = nand_resources,
222 .num_resources = ARRAY_SIZE(nand_resources),
223};
224
225void __init at91_add_device_nand(struct at91_nand_data *data)
226{
227 unsigned long csa;
228
229 if (!data)
230 return;
231
232 csa = at91_sys_read(AT91_MATRIX_EBICSA);
233 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
234
235 /* set the bus interface characteristics */
16074b66
PV		 236 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
237 | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
877d7720 238
16074b66
PV		 239 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
240 | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
877d7720 241
16074b66 242 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
877d7720 243
16074b66 244 at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
877d7720
AV		 245
246 /* enable pin */
247 if (data->enable_pin)
248 at91_set_gpio_output(data->enable_pin, 1);
249
250 /* ready/busy pin */
251 if (data->rdy_pin)
252 at91_set_gpio_input(data->rdy_pin, 1);
253
254 /* card detect pin */
255 if (data->det_pin)
256 at91_set_gpio_input(data->det_pin, 1);
257
258 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
259 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
260
261 nand_data = *data;
262 platform_device_register(&at91_nand_device);
263}
264
265#else
266void __init at91_add_device_nand(struct at91_nand_data *data) {}
267#endif
268
269
270/* --------------------------------------------------------------------
271 * TWI (i2c)
272 * -------------------------------------------------------------------- */
273
f230d3f5
AV		 274/*
275 * Prefer the GPIO code since the TWI controller isn't robust
276 * (gets overruns and underruns under load) and can only issue
277 * repeated STARTs in one scenario (the driver doesn't yet handle them).
278 */
279#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
280
281static struct i2c_gpio_platform_data pdata = {
282 .sda_pin = AT91_PIN_PA23,
283 .sda_is_open_drain = 1,
284 .scl_pin = AT91_PIN_PA24,
285 .scl_is_open_drain = 1,
286 .udelay = 2, /* ~100 kHz */
287};
288
289static struct platform_device at91sam9rl_twi_device = {
290 .name = "i2c-gpio",
291 .id = -1,
292 .dev.platform_data = &pdata,
293};
294
295void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
296{
297 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
298 at91_set_multi_drive(AT91_PIN_PA23, 1);
299
300 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
301 at91_set_multi_drive(AT91_PIN_PA24, 1);
302
303 i2c_register_board_info(0, devices, nr_devices);
304 platform_device_register(&at91sam9rl_twi_device);
305}
306
307#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
877d7720
AV		 308
309static struct resource twi_resources[] = {
310 [0] = {
311 .start = AT91SAM9RL_BASE_TWI0,
312 .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
313 .flags = IORESOURCE_MEM,
314 },
315 [1] = {
316 .start = AT91SAM9RL_ID_TWI0,
317 .end = AT91SAM9RL_ID_TWI0,
318 .flags = IORESOURCE_IRQ,
319 },
320};
321
322static struct platform_device at91sam9rl_twi_device = {
323 .name = "at91_i2c",
324 .id = -1,
325 .resource = twi_resources,
326 .num_resources = ARRAY_SIZE(twi_resources),
327};
328
f230d3f5 329void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
877d7720
AV		 330{
331 /* pins used for TWI interface */
332 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
333 at91_set_multi_drive(AT91_PIN_PA23, 1);
334
335 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
336 at91_set_multi_drive(AT91_PIN_PA24, 1);
337
f230d3f5 338 i2c_register_board_info(0, devices, nr_devices);
877d7720
AV		 339 platform_device_register(&at91sam9rl_twi_device);
340}
341#else
f230d3f5 342void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
877d7720
AV		 343#endif
344
345
346/* --------------------------------------------------------------------
347 * SPI
348 * -------------------------------------------------------------------- */
349
350#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
c6686ff9 351static u64 spi_dmamask = DMA_BIT_MASK(32);
877d7720
AV		 352
353static struct resource spi_resources[] = {
354 [0] = {
355 .start = AT91SAM9RL_BASE_SPI,
356 .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
357 .flags = IORESOURCE_MEM,
358 },
359 [1] = {
360 .start = AT91SAM9RL_ID_SPI,
361 .end = AT91SAM9RL_ID_SPI,
362 .flags = IORESOURCE_IRQ,
363 },
364};
365
366static struct platform_device at91sam9rl_spi_device = {
367 .name = "atmel_spi",
368 .id = 0,
369 .dev = {
370 .dma_mask = &spi_dmamask,
c6686ff9 371 .coherent_dma_mask = DMA_BIT_MASK(32),
877d7720
AV		 372 },
373 .resource = spi_resources,
374 .num_resources = ARRAY_SIZE(spi_resources),
375};
376
377static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
378
379
380void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
381{
382 int i;
383 unsigned long cs_pin;
384
385 at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
386 at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
387 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
388
389 /* Enable SPI chip-selects */
390 for (i = 0; i < nr_devices; i++) {
391 if (devices[i].controller_data)
392 cs_pin = (unsigned long) devices[i].controller_data;
393 else
394 cs_pin = spi_standard_cs[devices[i].chip_select];
395
396 /* enable chip-select pin */
397 at91_set_gpio_output(cs_pin, 1);
398
399 /* pass chip-select pin to driver */
400 devices[i].controller_data = (void *) cs_pin;
401 }
402
403 spi_register_board_info(devices, nr_devices);
404 platform_device_register(&at91sam9rl_spi_device);
405}
406#else
407void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
408#endif
409
410
411/* --------------------------------------------------------------------
412 * LCD Controller
413 * -------------------------------------------------------------------- */
414
415#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
c6686ff9 416static u64 lcdc_dmamask = DMA_BIT_MASK(32);
877d7720
AV		 417static struct atmel_lcdfb_info lcdc_data;
418
419static struct resource lcdc_resources[] = {
420 [0] = {
421 .start = AT91SAM9RL_LCDC_BASE,
422 .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
423 .flags = IORESOURCE_MEM,
424 },
425 [1] = {
426 .start = AT91SAM9RL_ID_LCDC,
427 .end = AT91SAM9RL_ID_LCDC,
428 .flags = IORESOURCE_IRQ,
429 },
877d7720
AV		 430};
431
432static struct platform_device at91_lcdc_device = {
433 .name = "atmel_lcdfb",
434 .id = 0,
435 .dev = {
436 .dma_mask = &lcdc_dmamask,
c6686ff9 437 .coherent_dma_mask = DMA_BIT_MASK(32),
877d7720
AV		 438 .platform_data = &lcdc_data,
439 },
440 .resource = lcdc_resources,
441 .num_resources = ARRAY_SIZE(lcdc_resources),
442};
443
444void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
445{
446 if (!data) {
447 return;
448 }
449
450 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
451 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
452 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
453 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
454 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
455 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
456 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
457 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
458 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
459 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
460 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
461 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
462 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
463 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
464 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
465 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
466 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
467 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
468 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
469 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
470 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
471
472 lcdc_data = *data;
473 platform_device_register(&at91_lcdc_device);
474}
475#else
476void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
477#endif
478
479
e5f40bfa
AV		 480/* --------------------------------------------------------------------
481 * Timer/Counter block
482 * -------------------------------------------------------------------- */
483
484#ifdef CONFIG_ATMEL_TCLIB
485
486static struct resource tcb_resources[] = {
487 [0] = {
488 .start = AT91SAM9RL_BASE_TCB0,
489 .end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
490 .flags = IORESOURCE_MEM,
491 },
492 [1] = {
493 .start = AT91SAM9RL_ID_TC0,
494 .end = AT91SAM9RL_ID_TC0,
495 .flags = IORESOURCE_IRQ,
496 },
497 [2] = {
498 .start = AT91SAM9RL_ID_TC1,
499 .end = AT91SAM9RL_ID_TC1,
500 .flags = IORESOURCE_IRQ,
501 },
502 [3] = {
503 .start = AT91SAM9RL_ID_TC2,
504 .end = AT91SAM9RL_ID_TC2,
505 .flags = IORESOURCE_IRQ,
506 },
507};
508
509static struct platform_device at91sam9rl_tcb_device = {
510 .name = "atmel_tcb",
511 .id = 0,
512 .resource = tcb_resources,
513 .num_resources = ARRAY_SIZE(tcb_resources),
514};
515
516static void __init at91_add_device_tc(void)
517{
518 /* this chip has a separate clock and irq for each TC channel */
519 at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk");
520 at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk");
521 at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk");
522 platform_device_register(&at91sam9rl_tcb_device);
523}
524#else
525static void __init at91_add_device_tc(void) { }
526#endif
527
528
884f5a6a
AV		 529/* --------------------------------------------------------------------
530 * RTC
531 * -------------------------------------------------------------------- */
532
533#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
534static struct platform_device at91sam9rl_rtc_device = {
535 .name = "at91_rtc",
536 .id = -1,
537 .num_resources = 0,
538};
539
540static void __init at91_add_device_rtc(void)
541{
542 platform_device_register(&at91sam9rl_rtc_device);
543}
544#else
545static void __init at91_add_device_rtc(void) {}
546#endif
547
548
549/* --------------------------------------------------------------------
550 * RTT
551 * -------------------------------------------------------------------- */
552
553static struct resource rtt_resources[] = {
554 {
555 .start = AT91_BASE_SYS + AT91_RTT,
556 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
557 .flags = IORESOURCE_MEM,
558 }
559};
560
561static struct platform_device at91sam9rl_rtt_device = {
562 .name = "at91_rtt",
4fd9212c 563 .id = 0,
884f5a6a
AV		 564 .resource = rtt_resources,
565 .num_resources = ARRAY_SIZE(rtt_resources),
566};
567
568static void __init at91_add_device_rtt(void)
569{
570 platform_device_register(&at91sam9rl_rtt_device);
571}
572
573
574/* --------------------------------------------------------------------
575 * Watchdog
576 * -------------------------------------------------------------------- */
577
578#if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
579static struct platform_device at91sam9rl_wdt_device = {
580 .name = "at91_wdt",
581 .id = -1,
582 .num_resources = 0,
583};
584
585static void __init at91_add_device_watchdog(void)
586{
587 platform_device_register(&at91sam9rl_wdt_device);
588}
589#else
590static void __init at91_add_device_watchdog(void) {}
591#endif
592
593
bfbc3266
AV		 594/* --------------------------------------------------------------------
595 * SSC -- Synchronous Serial Controller
596 * -------------------------------------------------------------------- */
597
598#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
599static u64 ssc0_dmamask = DMA_BIT_MASK(32);
600
601static struct resource ssc0_resources[] = {
602 [0] = {
603 .start = AT91SAM9RL_BASE_SSC0,
604 .end = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1,
605 .flags = IORESOURCE_MEM,
606 },
607 [1] = {
608 .start = AT91SAM9RL_ID_SSC0,
609 .end = AT91SAM9RL_ID_SSC0,
610 .flags = IORESOURCE_IRQ,
611 },
612};
613
614static struct platform_device at91sam9rl_ssc0_device = {
615 .name = "ssc",
616 .id = 0,
617 .dev = {
618 .dma_mask = &ssc0_dmamask,
619 .coherent_dma_mask = DMA_BIT_MASK(32),
620 },
621 .resource = ssc0_resources,
622 .num_resources = ARRAY_SIZE(ssc0_resources),
623};
624
625static inline void configure_ssc0_pins(unsigned pins)
626{
627 if (pins & ATMEL_SSC_TF)
628 at91_set_A_periph(AT91_PIN_PC0, 1);
629 if (pins & ATMEL_SSC_TK)
630 at91_set_A_periph(AT91_PIN_PC1, 1);
631 if (pins & ATMEL_SSC_TD)
632 at91_set_A_periph(AT91_PIN_PA15, 1);
633 if (pins & ATMEL_SSC_RD)
634 at91_set_A_periph(AT91_PIN_PA16, 1);
635 if (pins & ATMEL_SSC_RK)
636 at91_set_B_periph(AT91_PIN_PA10, 1);
637 if (pins & ATMEL_SSC_RF)
638 at91_set_B_periph(AT91_PIN_PA22, 1);
639}
640
641static u64 ssc1_dmamask = DMA_BIT_MASK(32);
642
643static struct resource ssc1_resources[] = {
644 [0] = {
645 .start = AT91SAM9RL_BASE_SSC1,
646 .end = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1,
647 .flags = IORESOURCE_MEM,
648 },
649 [1] = {
650 .start = AT91SAM9RL_ID_SSC1,
651 .end = AT91SAM9RL_ID_SSC1,
652 .flags = IORESOURCE_IRQ,
653 },
654};
655
656static struct platform_device at91sam9rl_ssc1_device = {
657 .name = "ssc",
658 .id = 1,
659 .dev = {
660 .dma_mask = &ssc1_dmamask,
661 .coherent_dma_mask = DMA_BIT_MASK(32),
662 },
663 .resource = ssc1_resources,
664 .num_resources = ARRAY_SIZE(ssc1_resources),
665};
666
667static inline void configure_ssc1_pins(unsigned pins)
668{
669 if (pins & ATMEL_SSC_TF)
670 at91_set_B_periph(AT91_PIN_PA29, 1);
671 if (pins & ATMEL_SSC_TK)
672 at91_set_B_periph(AT91_PIN_PA30, 1);
673 if (pins & ATMEL_SSC_TD)
674 at91_set_B_periph(AT91_PIN_PA13, 1);
675 if (pins & ATMEL_SSC_RD)
676 at91_set_B_periph(AT91_PIN_PA14, 1);
677 if (pins & ATMEL_SSC_RK)
678 at91_set_B_periph(AT91_PIN_PA9, 1);
679 if (pins & ATMEL_SSC_RF)
680 at91_set_B_periph(AT91_PIN_PA8, 1);
681}
682
683/*
bfbc3266
AV		 684 * SSC controllers are accessed through library code, instead of any
685 * kind of all-singing/all-dancing driver. For example one could be
686 * used by a particular I2S audio codec's driver, while another one
687 * on the same system might be used by a custom data capture driver.
688 */
689void __init at91_add_device_ssc(unsigned id, unsigned pins)
690{
691 struct platform_device *pdev;
692
693 /*
694 * NOTE: caller is responsible for passing information matching
695 * "pins" to whatever will be using each particular controller.
696 */
697 switch (id) {
698 case AT91SAM9RL_ID_SSC0:
699 pdev = &at91sam9rl_ssc0_device;
700 configure_ssc0_pins(pins);
701 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
702 break;
703 case AT91SAM9RL_ID_SSC1:
704 pdev = &at91sam9rl_ssc1_device;
705 configure_ssc1_pins(pins);
706 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
707 break;
708 default:
709 return;
710 }
711
712 platform_device_register(pdev);
713}
714
715#else
716void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
717#endif
718
719
877d7720
AV		 720/* --------------------------------------------------------------------
721 * UART
722 * -------------------------------------------------------------------- */
723
724#if defined(CONFIG_SERIAL_ATMEL)
725static struct resource dbgu_resources[] = {
726 [0] = {
727 .start = AT91_VA_BASE_SYS + AT91_DBGU,
728 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
729 .flags = IORESOURCE_MEM,
730 },
731 [1] = {
732 .start = AT91_ID_SYS,
733 .end = AT91_ID_SYS,
734 .flags = IORESOURCE_IRQ,
735 },
736};
737
738static struct atmel_uart_data dbgu_data = {
739 .use_dma_tx = 0,
740 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
741 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
742};
743
c6686ff9
AV		 744static u64 dbgu_dmamask = DMA_BIT_MASK(32);
745
877d7720
AV		 746static struct platform_device at91sam9rl_dbgu_device = {
747 .name = "atmel_usart",
748 .id = 0,
749 .dev = {
c6686ff9
AV		 750 .dma_mask = &dbgu_dmamask,
751 .coherent_dma_mask = DMA_BIT_MASK(32),
752 .platform_data = &dbgu_data,
877d7720
AV		 753 },
754 .resource = dbgu_resources,
755 .num_resources = ARRAY_SIZE(dbgu_resources),
756};
757
758static inline void configure_dbgu_pins(void)
759{
760 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
761 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
762}
763
764static struct resource uart0_resources[] = {
765 [0] = {
766 .start = AT91SAM9RL_BASE_US0,
767 .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
768 .flags = IORESOURCE_MEM,
769 },
770 [1] = {
771 .start = AT91SAM9RL_ID_US0,
772 .end = AT91SAM9RL_ID_US0,
773 .flags = IORESOURCE_IRQ,
774 },
775};
776
777static struct atmel_uart_data uart0_data = {
778 .use_dma_tx = 1,
779 .use_dma_rx = 1,
780};
781
c6686ff9
AV		 782static u64 uart0_dmamask = DMA_BIT_MASK(32);
783
877d7720
AV		 784static struct platform_device at91sam9rl_uart0_device = {
785 .name = "atmel_usart",
786 .id = 1,
787 .dev = {
c6686ff9
AV		 788 .dma_mask = &uart0_dmamask,
789 .coherent_dma_mask = DMA_BIT_MASK(32),
790 .platform_data = &uart0_data,
877d7720
AV		 791 },
792 .resource = uart0_resources,
793 .num_resources = ARRAY_SIZE(uart0_resources),
794};
795
c8f385a6 796static inline void configure_usart0_pins(unsigned pins)
877d7720
AV		 797{
798 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
799 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
c8f385a6
AV		 800
801 if (pins & ATMEL_UART_RTS)
802 at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
803 if (pins & ATMEL_UART_CTS)
804 at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
805 if (pins & ATMEL_UART_DSR)
806 at91_set_A_periph(AT91_PIN_PD14, 0); /* DSR0 */
807 if (pins & ATMEL_UART_DTR)
808 at91_set_A_periph(AT91_PIN_PD15, 0); /* DTR0 */
809 if (pins & ATMEL_UART_DCD)
810 at91_set_A_periph(AT91_PIN_PD16, 0); /* DCD0 */
811 if (pins & ATMEL_UART_RI)
812 at91_set_A_periph(AT91_PIN_PD17, 0); /* RI0 */
877d7720
AV		 813}
814
815static struct resource uart1_resources[] = {
816 [0] = {
817 .start = AT91SAM9RL_BASE_US1,
818 .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
819 .flags = IORESOURCE_MEM,
820 },
821 [1] = {
822 .start = AT91SAM9RL_ID_US1,
823 .end = AT91SAM9RL_ID_US1,
824 .flags = IORESOURCE_IRQ,
825 },
826};
827
828static struct atmel_uart_data uart1_data = {
829 .use_dma_tx = 1,
830 .use_dma_rx = 1,
831};
832
c6686ff9
AV		 833static u64 uart1_dmamask = DMA_BIT_MASK(32);
834
877d7720
AV		 835static struct platform_device at91sam9rl_uart1_device = {
836 .name = "atmel_usart",
837 .id = 2,
838 .dev = {
c6686ff9
AV		 839 .dma_mask = &uart1_dmamask,
840 .coherent_dma_mask = DMA_BIT_MASK(32),
841 .platform_data = &uart1_data,
877d7720
AV		 842 },
843 .resource = uart1_resources,
844 .num_resources = ARRAY_SIZE(uart1_resources),
845};
846
c8f385a6 847static inline void configure_usart1_pins(unsigned pins)
877d7720
AV		 848{
849 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
850 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
c8f385a6
AV		 851
852 if (pins & ATMEL_UART_RTS)
853 at91_set_B_periph(AT91_PIN_PA18, 0); /* RTS1 */
854 if (pins & ATMEL_UART_CTS)
855 at91_set_B_periph(AT91_PIN_PA19, 0); /* CTS1 */
877d7720
AV		 856}
857
858static struct resource uart2_resources[] = {
859 [0] = {
860 .start = AT91SAM9RL_BASE_US2,
861 .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
862 .flags = IORESOURCE_MEM,
863 },
864 [1] = {
865 .start = AT91SAM9RL_ID_US2,
866 .end = AT91SAM9RL_ID_US2,
867 .flags = IORESOURCE_IRQ,
868 },
869};
870
871static struct atmel_uart_data uart2_data = {
872 .use_dma_tx = 1,
873 .use_dma_rx = 1,
874};
875
c6686ff9
AV		 876static u64 uart2_dmamask = DMA_BIT_MASK(32);
877
877d7720
AV		 878static struct platform_device at91sam9rl_uart2_device = {
879 .name = "atmel_usart",
880 .id = 3,
881 .dev = {
c6686ff9
AV		 882 .dma_mask = &uart2_dmamask,
883 .coherent_dma_mask = DMA_BIT_MASK(32),
884 .platform_data = &uart2_data,
877d7720
AV		 885 },
886 .resource = uart2_resources,
887 .num_resources = ARRAY_SIZE(uart2_resources),
888};
889
c8f385a6 890static inline void configure_usart2_pins(unsigned pins)
877d7720
AV		 891{
892 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
893 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
c8f385a6
AV		 894
895 if (pins & ATMEL_UART_RTS)
896 at91_set_A_periph(AT91_PIN_PA29, 0); /* RTS2 */
897 if (pins & ATMEL_UART_CTS)
898 at91_set_A_periph(AT91_PIN_PA30, 0); /* CTS2 */
877d7720
AV		 899}
900
901static struct resource uart3_resources[] = {
902 [0] = {
903 .start = AT91SAM9RL_BASE_US3,
904 .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
905 .flags = IORESOURCE_MEM,
906 },
907 [1] = {
908 .start = AT91SAM9RL_ID_US3,
909 .end = AT91SAM9RL_ID_US3,
910 .flags = IORESOURCE_IRQ,
911 },
912};
913
914static struct atmel_uart_data uart3_data = {
915 .use_dma_tx = 1,
916 .use_dma_rx = 1,
917};
918
c6686ff9
AV		 919static u64 uart3_dmamask = DMA_BIT_MASK(32);
920
877d7720
AV		 921static struct platform_device at91sam9rl_uart3_device = {
922 .name = "atmel_usart",
923 .id = 4,
924 .dev = {
c6686ff9
AV		 925 .dma_mask = &uart3_dmamask,
926 .coherent_dma_mask = DMA_BIT_MASK(32),
927 .platform_data = &uart3_data,
877d7720
AV		 928 },
929 .resource = uart3_resources,
930 .num_resources = ARRAY_SIZE(uart3_resources),
931};
932
c8f385a6 933static inline void configure_usart3_pins(unsigned pins)
877d7720
AV		 934{
935 at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
936 at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */
c8f385a6
AV		 937
938 if (pins & ATMEL_UART_RTS)
939 at91_set_B_periph(AT91_PIN_PD4, 0); /* RTS3 */
940 if (pins & ATMEL_UART_CTS)
941 at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */
877d7720
AV		 942}
943
11aadac4 944static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
877d7720
AV		 945struct platform_device *atmel_default_console_device; /* the serial console device */
946
c8f385a6
AV		 947void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
948{
949 struct platform_device *pdev;
950
951 switch (id) {
952 case 0: /* DBGU */
953 pdev = &at91sam9rl_dbgu_device;
954 configure_dbgu_pins();
955 at91_clock_associate("mck", &pdev->dev, "usart");
956 break;
957 case AT91SAM9RL_ID_US0:
958 pdev = &at91sam9rl_uart0_device;
959 configure_usart0_pins(pins);
960 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
961 break;
962 case AT91SAM9RL_ID_US1:
963 pdev = &at91sam9rl_uart1_device;
964 configure_usart1_pins(pins);
965 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
966 break;
967 case AT91SAM9RL_ID_US2:
968 pdev = &at91sam9rl_uart2_device;
969 configure_usart2_pins(pins);
970 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
971 break;
972 case AT91SAM9RL_ID_US3:
973 pdev = &at91sam9rl_uart3_device;
974 configure_usart3_pins(pins);
975 at91_clock_associate("usart3_clk", &pdev->dev, "usart");
976 break;
977 default:
978 return;
979 }
980 pdev->id = portnr; /* update to mapped ID */
981
982 if (portnr < ATMEL_MAX_UART)
983 at91_uarts[portnr] = pdev;
984}
985
986void __init at91_set_serial_console(unsigned portnr)
987{
988 if (portnr < ATMEL_MAX_UART)
989 atmel_default_console_device = at91_uarts[portnr];
c8f385a6
AV		 990}
991
877d7720
AV		 992void __init at91_add_device_serial(void)
993{
994 int i;
995
996 for (i = 0; i < ATMEL_MAX_UART; i++) {
997 if (at91_uarts[i])
998 platform_device_register(at91_uarts[i]);
999 }
11aadac4
AV		 1000
1001 if (!atmel_default_console_device)
1002 printk(KERN_INFO "AT91: No default serial console defined.\n");
877d7720
AV		 1003}
1004#else
c8f385a6
AV		 1005void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1006void __init at91_set_serial_console(unsigned portnr) {}
877d7720
AV		 1007void __init at91_add_device_serial(void) {}
1008#endif
1009
1010
1011/* -------------------------------------------------------------------- */
1012
1013/*
1014 * These devices are always present and don't need any board-specific
1015 * setup.
1016 */
1017static int __init at91_add_standard_devices(void)
1018{
884f5a6a
AV		 1019 at91_add_device_rtc();
1020 at91_add_device_rtt();
1021 at91_add_device_watchdog();
e5f40bfa 1022 at91_add_device_tc();
877d7720
AV		 1023 return 0;
1024}
1025
1026arch_initcall(at91_add_standard_devices);
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