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Commit | Line | Data |
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73a59c1c | 1 | /* |
9d041268 | 2 | * linux/arch/arm/mach-at91/gpio.c |
73a59c1c SP |
3 | * |
4 | * Copyright (C) 2005 HP Labs | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
f2173834 | 12 | #include <linux/clk.h> |
73a59c1c | 13 | #include <linux/errno.h> |
07d265dd TG |
14 | #include <linux/interrupt.h> |
15 | #include <linux/irq.h> | |
73a59c1c SP |
16 | #include <linux/kernel.h> |
17 | #include <linux/list.h> | |
18 | #include <linux/module.h> | |
19 | ||
20 | #include <asm/io.h> | |
ea75ee9a | 21 | #include <asm/hardware.h> |
55d8baee | 22 | #include <asm/arch/at91_pio.h> |
73a59c1c SP |
23 | #include <asm/arch/gpio.h> |
24 | ||
f2173834 AV |
25 | #include "generic.h" |
26 | ||
27 | ||
28 | static struct at91_gpio_bank *gpio; | |
29 | static int gpio_banks; | |
30 | ||
73a59c1c SP |
31 | |
32 | static inline void __iomem *pin_to_controller(unsigned pin) | |
33 | { | |
34 | void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS; | |
35 | ||
36 | pin -= PIN_BASE; | |
37 | pin /= 32; | |
f2173834 AV |
38 | if (likely(pin < gpio_banks)) |
39 | return sys_base + gpio[pin].offset; | |
73a59c1c SP |
40 | |
41 | return NULL; | |
42 | } | |
43 | ||
44 | static inline unsigned pin_to_mask(unsigned pin) | |
45 | { | |
46 | pin -= PIN_BASE; | |
47 | return 1 << (pin % 32); | |
48 | } | |
49 | ||
50 | ||
51 | /*--------------------------------------------------------------------------*/ | |
52 | ||
53 | /* Not all hardware capabilities are exposed through these calls; they | |
54 | * only encapsulate the most common features and modes. (So if you | |
55 | * want to change signals in groups, do it directly.) | |
56 | * | |
57 | * Bootloaders will usually handle some of the pin multiplexing setup. | |
58 | * The intent is certainly that by the time Linux is fully booted, all | |
59 | * pins should have been fully initialized. These setup calls should | |
60 | * only be used by board setup routines, or possibly in driver probe(). | |
61 | * | |
62 | * For bootloaders doing all that setup, these calls could be inlined | |
63 | * as NOPs so Linux won't duplicate any setup code | |
64 | */ | |
65 | ||
66 | ||
a31c4eea DB |
67 | /* |
68 | * mux the pin to the "GPIO" peripheral role. | |
69 | */ | |
70 | int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup) | |
71 | { | |
72 | void __iomem *pio = pin_to_controller(pin); | |
73 | unsigned mask = pin_to_mask(pin); | |
74 | ||
75 | if (!pio) | |
76 | return -EINVAL; | |
77 | __raw_writel(mask, pio + PIO_IDR); | |
78 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
79 | __raw_writel(mask, pio + PIO_PER); | |
80 | return 0; | |
81 | } | |
82 | EXPORT_SYMBOL(at91_set_GPIO_periph); | |
83 | ||
84 | ||
73a59c1c SP |
85 | /* |
86 | * mux the pin to the "A" internal peripheral role. | |
87 | */ | |
88 | int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup) | |
89 | { | |
90 | void __iomem *pio = pin_to_controller(pin); | |
91 | unsigned mask = pin_to_mask(pin); | |
92 | ||
93 | if (!pio) | |
94 | return -EINVAL; | |
95 | ||
96 | __raw_writel(mask, pio + PIO_IDR); | |
97 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
98 | __raw_writel(mask, pio + PIO_ASR); | |
99 | __raw_writel(mask, pio + PIO_PDR); | |
100 | return 0; | |
101 | } | |
102 | EXPORT_SYMBOL(at91_set_A_periph); | |
103 | ||
104 | ||
105 | /* | |
106 | * mux the pin to the "B" internal peripheral role. | |
107 | */ | |
108 | int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup) | |
109 | { | |
110 | void __iomem *pio = pin_to_controller(pin); | |
111 | unsigned mask = pin_to_mask(pin); | |
112 | ||
113 | if (!pio) | |
114 | return -EINVAL; | |
115 | ||
116 | __raw_writel(mask, pio + PIO_IDR); | |
117 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
118 | __raw_writel(mask, pio + PIO_BSR); | |
119 | __raw_writel(mask, pio + PIO_PDR); | |
120 | return 0; | |
121 | } | |
122 | EXPORT_SYMBOL(at91_set_B_periph); | |
123 | ||
124 | ||
125 | /* | |
126 | * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and | |
127 | * configure it for an input. | |
128 | */ | |
129 | int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup) | |
130 | { | |
131 | void __iomem *pio = pin_to_controller(pin); | |
132 | unsigned mask = pin_to_mask(pin); | |
133 | ||
134 | if (!pio) | |
135 | return -EINVAL; | |
136 | ||
137 | __raw_writel(mask, pio + PIO_IDR); | |
138 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
139 | __raw_writel(mask, pio + PIO_ODR); | |
140 | __raw_writel(mask, pio + PIO_PER); | |
141 | return 0; | |
142 | } | |
143 | EXPORT_SYMBOL(at91_set_gpio_input); | |
144 | ||
145 | ||
146 | /* | |
147 | * mux the pin to the gpio controller (instead of "A" or "B" peripheral), | |
148 | * and configure it for an output. | |
149 | */ | |
150 | int __init_or_module at91_set_gpio_output(unsigned pin, int value) | |
151 | { | |
152 | void __iomem *pio = pin_to_controller(pin); | |
153 | unsigned mask = pin_to_mask(pin); | |
154 | ||
155 | if (!pio) | |
156 | return -EINVAL; | |
157 | ||
158 | __raw_writel(mask, pio + PIO_IDR); | |
159 | __raw_writel(mask, pio + PIO_PUDR); | |
160 | __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); | |
161 | __raw_writel(mask, pio + PIO_OER); | |
162 | __raw_writel(mask, pio + PIO_PER); | |
163 | return 0; | |
164 | } | |
165 | EXPORT_SYMBOL(at91_set_gpio_output); | |
166 | ||
167 | ||
168 | /* | |
169 | * enable/disable the glitch filter; mostly used with IRQ handling. | |
170 | */ | |
171 | int __init_or_module at91_set_deglitch(unsigned pin, int is_on) | |
172 | { | |
173 | void __iomem *pio = pin_to_controller(pin); | |
174 | unsigned mask = pin_to_mask(pin); | |
175 | ||
176 | if (!pio) | |
177 | return -EINVAL; | |
178 | __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); | |
179 | return 0; | |
180 | } | |
181 | EXPORT_SYMBOL(at91_set_deglitch); | |
182 | ||
df666b9c AV |
183 | /* |
184 | * enable/disable the multi-driver; This is only valid for output and | |
185 | * allows the output pin to run as an open collector output. | |
186 | */ | |
187 | int __init_or_module at91_set_multi_drive(unsigned pin, int is_on) | |
188 | { | |
189 | void __iomem *pio = pin_to_controller(pin); | |
190 | unsigned mask = pin_to_mask(pin); | |
191 | ||
192 | if (!pio) | |
193 | return -EINVAL; | |
194 | ||
195 | __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR)); | |
196 | return 0; | |
197 | } | |
198 | EXPORT_SYMBOL(at91_set_multi_drive); | |
199 | ||
73a59c1c SP |
200 | /*--------------------------------------------------------------------------*/ |
201 | ||
a31c4eea DB |
202 | /* new-style GPIO calls; these expect at91_set_GPIO_periph to have been |
203 | * called, and maybe at91_set_multi_drive() for putout pins. | |
204 | */ | |
205 | ||
206 | int gpio_direction_input(unsigned pin) | |
207 | { | |
208 | void __iomem *pio = pin_to_controller(pin); | |
209 | unsigned mask = pin_to_mask(pin); | |
210 | ||
211 | if (!pio || !(__raw_readl(pio + PIO_PSR) & mask)) | |
212 | return -EINVAL; | |
0ebffe39 | 213 | __raw_writel(mask, pio + PIO_ODR); |
a31c4eea DB |
214 | return 0; |
215 | } | |
216 | EXPORT_SYMBOL(gpio_direction_input); | |
217 | ||
28735a72 | 218 | int gpio_direction_output(unsigned pin, int value) |
a31c4eea DB |
219 | { |
220 | void __iomem *pio = pin_to_controller(pin); | |
221 | unsigned mask = pin_to_mask(pin); | |
222 | ||
223 | if (!pio || !(__raw_readl(pio + PIO_PSR) & mask)) | |
224 | return -EINVAL; | |
28735a72 | 225 | __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); |
a31c4eea DB |
226 | __raw_writel(mask, pio + PIO_OER); |
227 | return 0; | |
228 | } | |
229 | EXPORT_SYMBOL(gpio_direction_output); | |
230 | ||
231 | /*--------------------------------------------------------------------------*/ | |
232 | ||
73a59c1c SP |
233 | /* |
234 | * assuming the pin is muxed as a gpio output, set its value. | |
235 | */ | |
236 | int at91_set_gpio_value(unsigned pin, int value) | |
237 | { | |
238 | void __iomem *pio = pin_to_controller(pin); | |
239 | unsigned mask = pin_to_mask(pin); | |
240 | ||
241 | if (!pio) | |
242 | return -EINVAL; | |
243 | __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); | |
244 | return 0; | |
245 | } | |
246 | EXPORT_SYMBOL(at91_set_gpio_value); | |
247 | ||
248 | ||
249 | /* | |
250 | * read the pin's value (works even if it's not muxed as a gpio). | |
251 | */ | |
252 | int at91_get_gpio_value(unsigned pin) | |
253 | { | |
254 | void __iomem *pio = pin_to_controller(pin); | |
255 | unsigned mask = pin_to_mask(pin); | |
256 | u32 pdsr; | |
257 | ||
258 | if (!pio) | |
259 | return -EINVAL; | |
260 | pdsr = __raw_readl(pio + PIO_PDSR); | |
261 | return (pdsr & mask) != 0; | |
262 | } | |
263 | EXPORT_SYMBOL(at91_get_gpio_value); | |
264 | ||
265 | /*--------------------------------------------------------------------------*/ | |
266 | ||
814138ff AV |
267 | #ifdef CONFIG_PM |
268 | ||
f2173834 AV |
269 | static u32 wakeups[MAX_GPIO_BANKS]; |
270 | static u32 backups[MAX_GPIO_BANKS]; | |
814138ff AV |
271 | |
272 | static int gpio_irq_set_wake(unsigned pin, unsigned state) | |
273 | { | |
274 | unsigned mask = pin_to_mask(pin); | |
3ea163e4 | 275 | unsigned bank = (pin - PIN_BASE) / 32; |
814138ff | 276 | |
3ea163e4 | 277 | if (unlikely(bank >= MAX_GPIO_BANKS)) |
814138ff AV |
278 | return -EINVAL; |
279 | ||
280 | if (state) | |
3ea163e4 | 281 | wakeups[bank] |= mask; |
814138ff | 282 | else |
3ea163e4 AV |
283 | wakeups[bank] &= ~mask; |
284 | ||
285 | set_irq_wake(gpio[bank].id, state); | |
814138ff AV |
286 | |
287 | return 0; | |
288 | } | |
289 | ||
290 | void at91_gpio_suspend(void) | |
291 | { | |
292 | int i; | |
293 | ||
f2173834 AV |
294 | for (i = 0; i < gpio_banks; i++) { |
295 | u32 pio = gpio[i].offset; | |
814138ff | 296 | |
814138ff | 297 | backups[i] = at91_sys_read(pio + PIO_IMR); |
f2173834 AV |
298 | at91_sys_write(pio + PIO_IDR, backups[i]); |
299 | at91_sys_write(pio + PIO_IER, wakeups[i]); | |
814138ff | 300 | |
3ea163e4 AV |
301 | if (!wakeups[i]) |
302 | clk_disable(gpio[i].clock); | |
303 | else { | |
814138ff | 304 | #ifdef CONFIG_PM_DEBUG |
3ea163e4 | 305 | printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]); |
814138ff AV |
306 | #endif |
307 | } | |
308 | } | |
309 | } | |
310 | ||
311 | void at91_gpio_resume(void) | |
312 | { | |
313 | int i; | |
314 | ||
f2173834 AV |
315 | for (i = 0; i < gpio_banks; i++) { |
316 | u32 pio = gpio[i].offset; | |
814138ff | 317 | |
3ea163e4 AV |
318 | if (!wakeups[i]) |
319 | clk_enable(gpio[i].clock); | |
320 | ||
f2173834 AV |
321 | at91_sys_write(pio + PIO_IDR, wakeups[i]); |
322 | at91_sys_write(pio + PIO_IER, backups[i]); | |
f2173834 | 323 | } |
814138ff AV |
324 | } |
325 | ||
326 | #else | |
327 | #define gpio_irq_set_wake NULL | |
328 | #endif | |
329 | ||
73a59c1c SP |
330 | |
331 | /* Several AIC controller irqs are dispatched through this GPIO handler. | |
332 | * To use any AT91_PIN_* as an externally triggered IRQ, first call | |
333 | * at91_set_gpio_input() then maybe enable its glitch filter. | |
334 | * Then just request_irq() with the pin ID; it works like any ARM IRQ | |
335 | * handler, though it always triggers on rising and falling edges. | |
336 | * | |
337 | * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after | |
338 | * configuring them with at91_set_a_periph() or at91_set_b_periph(). | |
339 | * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. | |
340 | */ | |
341 | ||
342 | static void gpio_irq_mask(unsigned pin) | |
343 | { | |
344 | void __iomem *pio = pin_to_controller(pin); | |
345 | unsigned mask = pin_to_mask(pin); | |
346 | ||
347 | if (pio) | |
348 | __raw_writel(mask, pio + PIO_IDR); | |
349 | } | |
350 | ||
351 | static void gpio_irq_unmask(unsigned pin) | |
352 | { | |
353 | void __iomem *pio = pin_to_controller(pin); | |
354 | unsigned mask = pin_to_mask(pin); | |
355 | ||
356 | if (pio) | |
357 | __raw_writel(mask, pio + PIO_IER); | |
358 | } | |
359 | ||
360 | static int gpio_irq_type(unsigned pin, unsigned type) | |
361 | { | |
362 | return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL; | |
363 | } | |
364 | ||
38c677cb DB |
365 | static struct irq_chip gpio_irqchip = { |
366 | .name = "GPIO", | |
73a59c1c SP |
367 | .mask = gpio_irq_mask, |
368 | .unmask = gpio_irq_unmask, | |
369 | .set_type = gpio_irq_type, | |
814138ff | 370 | .set_wake = gpio_irq_set_wake, |
73a59c1c SP |
371 | }; |
372 | ||
10dd5ce2 | 373 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
73a59c1c SP |
374 | { |
375 | unsigned pin; | |
10dd5ce2 | 376 | struct irq_desc *gpio; |
73a59c1c SP |
377 | void __iomem *pio; |
378 | u32 isr; | |
379 | ||
07d265dd | 380 | pio = get_irq_chip_data(irq); |
73a59c1c SP |
381 | |
382 | /* temporarily mask (level sensitive) parent IRQ */ | |
383 | desc->chip->ack(irq); | |
384 | for (;;) { | |
814138ff | 385 | /* reading ISR acks the pending (edge triggered) GPIO interrupt */ |
73a59c1c SP |
386 | isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); |
387 | if (!isr) | |
388 | break; | |
389 | ||
07d265dd | 390 | pin = (unsigned) get_irq_data(irq); |
73a59c1c SP |
391 | gpio = &irq_desc[pin]; |
392 | ||
393 | while (isr) { | |
abbea718 | 394 | if (isr & 1) { |
07d265dd | 395 | if (unlikely(gpio->depth)) { |
abbea718 AV |
396 | /* |
397 | * The core ARM interrupt handler lazily disables IRQs so | |
398 | * another IRQ must be generated before it actually gets | |
399 | * here to be disabled on the GPIO controller. | |
400 | */ | |
401 | gpio_irq_mask(pin); | |
402 | } | |
403 | else | |
0cd61b68 | 404 | desc_handle_irq(pin, gpio); |
abbea718 | 405 | } |
73a59c1c SP |
406 | pin++; |
407 | gpio++; | |
408 | isr >>= 1; | |
409 | } | |
410 | } | |
411 | desc->chip->unmask(irq); | |
412 | /* now it may re-trigger */ | |
413 | } | |
414 | ||
f2173834 AV |
415 | /*--------------------------------------------------------------------------*/ |
416 | ||
417 | /* | |
418 | * Called from the processor-specific init to enable GPIO interrupt support. | |
419 | */ | |
420 | void __init at91_gpio_irq_setup(void) | |
73a59c1c | 421 | { |
f2173834 | 422 | unsigned pioc, pin; |
73a59c1c | 423 | |
f2173834 AV |
424 | for (pioc = 0, pin = PIN_BASE; |
425 | pioc < gpio_banks; | |
426 | pioc++) { | |
73a59c1c | 427 | void __iomem *controller; |
f2173834 | 428 | unsigned id = gpio[pioc].id; |
73a59c1c SP |
429 | unsigned i; |
430 | ||
f2173834 AV |
431 | clk_enable(gpio[pioc].clock); /* enable PIO controller's clock */ |
432 | ||
433 | controller = (void __iomem *) AT91_VA_BASE_SYS + gpio[pioc].offset; | |
73a59c1c SP |
434 | __raw_writel(~0, controller + PIO_IDR); |
435 | ||
436 | set_irq_data(id, (void *) pin); | |
10dd5ce2 | 437 | set_irq_chip_data(id, controller); |
73a59c1c SP |
438 | |
439 | for (i = 0; i < 32; i++, pin++) { | |
814138ff AV |
440 | /* |
441 | * Can use the "simple" and not "edge" handler since it's | |
3a4fa0a2 | 442 | * shorter, and the AIC handles interrupts sanely. |
814138ff | 443 | */ |
73a59c1c | 444 | set_irq_chip(pin, &gpio_irqchip); |
10dd5ce2 | 445 | set_irq_handler(pin, handle_simple_irq); |
73a59c1c SP |
446 | set_irq_flags(pin, IRQF_VALID); |
447 | } | |
448 | ||
449 | set_irq_chained_handler(id, gpio_irq_handler); | |
73a59c1c | 450 | } |
f2173834 AV |
451 | pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); |
452 | } | |
453 | ||
454 | /* | |
455 | * Called from the processor-specific init to enable GPIO pin support. | |
456 | */ | |
457 | void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) | |
458 | { | |
459 | BUG_ON(nr_banks > MAX_GPIO_BANKS); | |
460 | ||
461 | gpio = data; | |
462 | gpio_banks = nr_banks; | |
73a59c1c | 463 | } |