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Commit | Line | Data |
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73a59c1c | 1 | /* |
9d041268 | 2 | * linux/arch/arm/mach-at91/gpio.c |
73a59c1c SP |
3 | * |
4 | * Copyright (C) 2005 HP Labs | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
f2173834 | 12 | #include <linux/clk.h> |
73a59c1c | 13 | #include <linux/errno.h> |
07d265dd TG |
14 | #include <linux/interrupt.h> |
15 | #include <linux/irq.h> | |
b66545e7 AV |
16 | #include <linux/debugfs.h> |
17 | #include <linux/seq_file.h> | |
73a59c1c SP |
18 | #include <linux/kernel.h> |
19 | #include <linux/list.h> | |
20 | #include <linux/module.h> | |
fced80c7 | 21 | #include <linux/io.h> |
73a59c1c | 22 | |
a09e64fb RK |
23 | #include <mach/hardware.h> |
24 | #include <mach/at91_pio.h> | |
25 | #include <mach/gpio.h> | |
73a59c1c | 26 | |
f373e8c0 RM |
27 | #include <asm/gpio.h> |
28 | ||
f2173834 AV |
29 | #include "generic.h" |
30 | ||
f373e8c0 RM |
31 | struct at91_gpio_chip { |
32 | struct gpio_chip chip; | |
33 | struct at91_gpio_chip *next; /* Bank sharing same clock */ | |
34 | struct at91_gpio_bank *bank; /* Bank definition */ | |
35 | void __iomem *regbase; /* Base of register bank */ | |
36 | }; | |
f2173834 | 37 | |
f373e8c0 RM |
38 | #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) |
39 | ||
40 | static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip); | |
41 | static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val); | |
42 | static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset); | |
43 | static int at91_gpiolib_direction_output(struct gpio_chip *chip, | |
44 | unsigned offset, int val); | |
45 | static int at91_gpiolib_direction_input(struct gpio_chip *chip, | |
46 | unsigned offset); | |
f373e8c0 RM |
47 | |
48 | #define AT91_GPIO_CHIP(name, base_gpio, nr_gpio) \ | |
49 | { \ | |
50 | .chip = { \ | |
51 | .label = name, \ | |
f373e8c0 RM |
52 | .direction_input = at91_gpiolib_direction_input, \ |
53 | .direction_output = at91_gpiolib_direction_output, \ | |
54 | .get = at91_gpiolib_get, \ | |
55 | .set = at91_gpiolib_set, \ | |
56 | .dbg_show = at91_gpiolib_dbg_show, \ | |
57 | .base = base_gpio, \ | |
58 | .ngpio = nr_gpio, \ | |
59 | }, \ | |
60 | } | |
f2173834 | 61 | |
f373e8c0 RM |
62 | static struct at91_gpio_chip gpio_chip[] = { |
63 | AT91_GPIO_CHIP("A", 0x00 + PIN_BASE, 32), | |
64 | AT91_GPIO_CHIP("B", 0x20 + PIN_BASE, 32), | |
65 | AT91_GPIO_CHIP("C", 0x40 + PIN_BASE, 32), | |
66 | AT91_GPIO_CHIP("D", 0x60 + PIN_BASE, 32), | |
67 | AT91_GPIO_CHIP("E", 0x80 + PIN_BASE, 32), | |
68 | }; | |
69 | ||
70 | static int gpio_banks; | |
73a59c1c SP |
71 | |
72 | static inline void __iomem *pin_to_controller(unsigned pin) | |
73 | { | |
73a59c1c SP |
74 | pin -= PIN_BASE; |
75 | pin /= 32; | |
f2173834 | 76 | if (likely(pin < gpio_banks)) |
f373e8c0 | 77 | return gpio_chip[pin].regbase; |
73a59c1c SP |
78 | |
79 | return NULL; | |
80 | } | |
81 | ||
82 | static inline unsigned pin_to_mask(unsigned pin) | |
83 | { | |
84 | pin -= PIN_BASE; | |
85 | return 1 << (pin % 32); | |
86 | } | |
87 | ||
88 | ||
89 | /*--------------------------------------------------------------------------*/ | |
90 | ||
91 | /* Not all hardware capabilities are exposed through these calls; they | |
92 | * only encapsulate the most common features and modes. (So if you | |
93 | * want to change signals in groups, do it directly.) | |
94 | * | |
95 | * Bootloaders will usually handle some of the pin multiplexing setup. | |
96 | * The intent is certainly that by the time Linux is fully booted, all | |
97 | * pins should have been fully initialized. These setup calls should | |
98 | * only be used by board setup routines, or possibly in driver probe(). | |
99 | * | |
100 | * For bootloaders doing all that setup, these calls could be inlined | |
101 | * as NOPs so Linux won't duplicate any setup code | |
102 | */ | |
103 | ||
104 | ||
a31c4eea DB |
105 | /* |
106 | * mux the pin to the "GPIO" peripheral role. | |
107 | */ | |
108 | int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup) | |
109 | { | |
110 | void __iomem *pio = pin_to_controller(pin); | |
111 | unsigned mask = pin_to_mask(pin); | |
112 | ||
113 | if (!pio) | |
114 | return -EINVAL; | |
115 | __raw_writel(mask, pio + PIO_IDR); | |
116 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
117 | __raw_writel(mask, pio + PIO_PER); | |
118 | return 0; | |
119 | } | |
120 | EXPORT_SYMBOL(at91_set_GPIO_periph); | |
121 | ||
122 | ||
73a59c1c SP |
123 | /* |
124 | * mux the pin to the "A" internal peripheral role. | |
125 | */ | |
126 | int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup) | |
127 | { | |
128 | void __iomem *pio = pin_to_controller(pin); | |
129 | unsigned mask = pin_to_mask(pin); | |
130 | ||
131 | if (!pio) | |
132 | return -EINVAL; | |
133 | ||
134 | __raw_writel(mask, pio + PIO_IDR); | |
135 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
136 | __raw_writel(mask, pio + PIO_ASR); | |
137 | __raw_writel(mask, pio + PIO_PDR); | |
138 | return 0; | |
139 | } | |
140 | EXPORT_SYMBOL(at91_set_A_periph); | |
141 | ||
142 | ||
143 | /* | |
144 | * mux the pin to the "B" internal peripheral role. | |
145 | */ | |
146 | int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup) | |
147 | { | |
148 | void __iomem *pio = pin_to_controller(pin); | |
149 | unsigned mask = pin_to_mask(pin); | |
150 | ||
151 | if (!pio) | |
152 | return -EINVAL; | |
153 | ||
154 | __raw_writel(mask, pio + PIO_IDR); | |
155 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
156 | __raw_writel(mask, pio + PIO_BSR); | |
157 | __raw_writel(mask, pio + PIO_PDR); | |
158 | return 0; | |
159 | } | |
160 | EXPORT_SYMBOL(at91_set_B_periph); | |
161 | ||
162 | ||
163 | /* | |
164 | * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and | |
165 | * configure it for an input. | |
166 | */ | |
167 | int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup) | |
168 | { | |
169 | void __iomem *pio = pin_to_controller(pin); | |
170 | unsigned mask = pin_to_mask(pin); | |
171 | ||
172 | if (!pio) | |
173 | return -EINVAL; | |
174 | ||
175 | __raw_writel(mask, pio + PIO_IDR); | |
176 | __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); | |
177 | __raw_writel(mask, pio + PIO_ODR); | |
178 | __raw_writel(mask, pio + PIO_PER); | |
179 | return 0; | |
180 | } | |
181 | EXPORT_SYMBOL(at91_set_gpio_input); | |
182 | ||
183 | ||
184 | /* | |
185 | * mux the pin to the gpio controller (instead of "A" or "B" peripheral), | |
186 | * and configure it for an output. | |
187 | */ | |
188 | int __init_or_module at91_set_gpio_output(unsigned pin, int value) | |
189 | { | |
190 | void __iomem *pio = pin_to_controller(pin); | |
191 | unsigned mask = pin_to_mask(pin); | |
192 | ||
193 | if (!pio) | |
194 | return -EINVAL; | |
195 | ||
196 | __raw_writel(mask, pio + PIO_IDR); | |
197 | __raw_writel(mask, pio + PIO_PUDR); | |
198 | __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); | |
199 | __raw_writel(mask, pio + PIO_OER); | |
200 | __raw_writel(mask, pio + PIO_PER); | |
201 | return 0; | |
202 | } | |
203 | EXPORT_SYMBOL(at91_set_gpio_output); | |
204 | ||
205 | ||
206 | /* | |
207 | * enable/disable the glitch filter; mostly used with IRQ handling. | |
208 | */ | |
209 | int __init_or_module at91_set_deglitch(unsigned pin, int is_on) | |
210 | { | |
211 | void __iomem *pio = pin_to_controller(pin); | |
212 | unsigned mask = pin_to_mask(pin); | |
213 | ||
214 | if (!pio) | |
215 | return -EINVAL; | |
216 | __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); | |
217 | return 0; | |
218 | } | |
219 | EXPORT_SYMBOL(at91_set_deglitch); | |
220 | ||
df666b9c AV |
221 | /* |
222 | * enable/disable the multi-driver; This is only valid for output and | |
223 | * allows the output pin to run as an open collector output. | |
224 | */ | |
225 | int __init_or_module at91_set_multi_drive(unsigned pin, int is_on) | |
226 | { | |
227 | void __iomem *pio = pin_to_controller(pin); | |
228 | unsigned mask = pin_to_mask(pin); | |
229 | ||
230 | if (!pio) | |
231 | return -EINVAL; | |
232 | ||
233 | __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR)); | |
234 | return 0; | |
235 | } | |
236 | EXPORT_SYMBOL(at91_set_multi_drive); | |
237 | ||
73a59c1c SP |
238 | /* |
239 | * assuming the pin is muxed as a gpio output, set its value. | |
240 | */ | |
241 | int at91_set_gpio_value(unsigned pin, int value) | |
242 | { | |
243 | void __iomem *pio = pin_to_controller(pin); | |
244 | unsigned mask = pin_to_mask(pin); | |
245 | ||
246 | if (!pio) | |
247 | return -EINVAL; | |
248 | __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); | |
249 | return 0; | |
250 | } | |
251 | EXPORT_SYMBOL(at91_set_gpio_value); | |
252 | ||
253 | ||
254 | /* | |
255 | * read the pin's value (works even if it's not muxed as a gpio). | |
256 | */ | |
257 | int at91_get_gpio_value(unsigned pin) | |
258 | { | |
259 | void __iomem *pio = pin_to_controller(pin); | |
260 | unsigned mask = pin_to_mask(pin); | |
261 | u32 pdsr; | |
262 | ||
263 | if (!pio) | |
264 | return -EINVAL; | |
265 | pdsr = __raw_readl(pio + PIO_PDSR); | |
266 | return (pdsr & mask) != 0; | |
267 | } | |
268 | EXPORT_SYMBOL(at91_get_gpio_value); | |
269 | ||
270 | /*--------------------------------------------------------------------------*/ | |
271 | ||
814138ff AV |
272 | #ifdef CONFIG_PM |
273 | ||
f2173834 AV |
274 | static u32 wakeups[MAX_GPIO_BANKS]; |
275 | static u32 backups[MAX_GPIO_BANKS]; | |
814138ff | 276 | |
da0f9403 | 277 | static int gpio_irq_set_wake(struct irq_data *d, unsigned state) |
814138ff | 278 | { |
da0f9403 LB |
279 | unsigned mask = pin_to_mask(d->irq); |
280 | unsigned bank = (d->irq - PIN_BASE) / 32; | |
814138ff | 281 | |
3ea163e4 | 282 | if (unlikely(bank >= MAX_GPIO_BANKS)) |
814138ff AV |
283 | return -EINVAL; |
284 | ||
285 | if (state) | |
3ea163e4 | 286 | wakeups[bank] |= mask; |
814138ff | 287 | else |
3ea163e4 AV |
288 | wakeups[bank] &= ~mask; |
289 | ||
6845664a | 290 | irq_set_irq_wake(gpio_chip[bank].bank->id, state); |
814138ff AV |
291 | |
292 | return 0; | |
293 | } | |
294 | ||
295 | void at91_gpio_suspend(void) | |
296 | { | |
297 | int i; | |
298 | ||
f2173834 | 299 | for (i = 0; i < gpio_banks; i++) { |
f373e8c0 | 300 | void __iomem *pio = gpio_chip[i].regbase; |
814138ff | 301 | |
e83aff58 DB |
302 | backups[i] = __raw_readl(pio + PIO_IMR); |
303 | __raw_writel(backups[i], pio + PIO_IDR); | |
304 | __raw_writel(wakeups[i], pio + PIO_IER); | |
814138ff | 305 | |
3ea163e4 | 306 | if (!wakeups[i]) |
f373e8c0 | 307 | clk_disable(gpio_chip[i].bank->clock); |
3ea163e4 | 308 | else { |
814138ff | 309 | #ifdef CONFIG_PM_DEBUG |
3ea163e4 | 310 | printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]); |
814138ff AV |
311 | #endif |
312 | } | |
313 | } | |
314 | } | |
315 | ||
316 | void at91_gpio_resume(void) | |
317 | { | |
318 | int i; | |
319 | ||
f2173834 | 320 | for (i = 0; i < gpio_banks; i++) { |
f373e8c0 | 321 | void __iomem *pio = gpio_chip[i].regbase; |
814138ff | 322 | |
3ea163e4 | 323 | if (!wakeups[i]) |
f373e8c0 | 324 | clk_enable(gpio_chip[i].bank->clock); |
3ea163e4 | 325 | |
e83aff58 DB |
326 | __raw_writel(wakeups[i], pio + PIO_IDR); |
327 | __raw_writel(backups[i], pio + PIO_IER); | |
f2173834 | 328 | } |
814138ff AV |
329 | } |
330 | ||
331 | #else | |
332 | #define gpio_irq_set_wake NULL | |
333 | #endif | |
334 | ||
73a59c1c SP |
335 | |
336 | /* Several AIC controller irqs are dispatched through this GPIO handler. | |
337 | * To use any AT91_PIN_* as an externally triggered IRQ, first call | |
338 | * at91_set_gpio_input() then maybe enable its glitch filter. | |
339 | * Then just request_irq() with the pin ID; it works like any ARM IRQ | |
340 | * handler, though it always triggers on rising and falling edges. | |
341 | * | |
342 | * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after | |
343 | * configuring them with at91_set_a_periph() or at91_set_b_periph(). | |
344 | * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. | |
345 | */ | |
346 | ||
da0f9403 | 347 | static void gpio_irq_mask(struct irq_data *d) |
73a59c1c | 348 | { |
da0f9403 LB |
349 | void __iomem *pio = pin_to_controller(d->irq); |
350 | unsigned mask = pin_to_mask(d->irq); | |
73a59c1c SP |
351 | |
352 | if (pio) | |
353 | __raw_writel(mask, pio + PIO_IDR); | |
354 | } | |
355 | ||
da0f9403 | 356 | static void gpio_irq_unmask(struct irq_data *d) |
73a59c1c | 357 | { |
da0f9403 LB |
358 | void __iomem *pio = pin_to_controller(d->irq); |
359 | unsigned mask = pin_to_mask(d->irq); | |
73a59c1c SP |
360 | |
361 | if (pio) | |
362 | __raw_writel(mask, pio + PIO_IER); | |
363 | } | |
364 | ||
da0f9403 | 365 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
73a59c1c | 366 | { |
e83aff58 DB |
367 | switch (type) { |
368 | case IRQ_TYPE_NONE: | |
369 | case IRQ_TYPE_EDGE_BOTH: | |
370 | return 0; | |
371 | default: | |
372 | return -EINVAL; | |
373 | } | |
73a59c1c SP |
374 | } |
375 | ||
38c677cb DB |
376 | static struct irq_chip gpio_irqchip = { |
377 | .name = "GPIO", | |
ac93cdbd | 378 | .irq_disable = gpio_irq_mask, |
da0f9403 LB |
379 | .irq_mask = gpio_irq_mask, |
380 | .irq_unmask = gpio_irq_unmask, | |
381 | .irq_set_type = gpio_irq_type, | |
382 | .irq_set_wake = gpio_irq_set_wake, | |
73a59c1c SP |
383 | }; |
384 | ||
10dd5ce2 | 385 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
73a59c1c SP |
386 | { |
387 | unsigned pin; | |
ac93cdbd TG |
388 | struct irq_data *idata = irq_desc_get_irq_data(desc); |
389 | struct irq_chip *chip = irq_data_get_irq_chip(idata); | |
390 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); | |
391 | void __iomem *pio = at91_gpio->regbase; | |
73a59c1c SP |
392 | u32 isr; |
393 | ||
73a59c1c | 394 | /* temporarily mask (level sensitive) parent IRQ */ |
ac93cdbd | 395 | chip->irq_ack(idata); |
73a59c1c | 396 | for (;;) { |
e83aff58 DB |
397 | /* Reading ISR acks pending (edge triggered) GPIO interrupts. |
398 | * When there none are pending, we're finished unless we need | |
399 | * to process multiple banks (like ID_PIOCDE on sam9263). | |
400 | */ | |
73a59c1c | 401 | isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); |
e83aff58 | 402 | if (!isr) { |
f373e8c0 | 403 | if (!at91_gpio->next) |
e83aff58 | 404 | break; |
f373e8c0 RM |
405 | at91_gpio = at91_gpio->next; |
406 | pio = at91_gpio->regbase; | |
e83aff58 DB |
407 | continue; |
408 | } | |
73a59c1c | 409 | |
f373e8c0 | 410 | pin = at91_gpio->chip.base; |
73a59c1c SP |
411 | |
412 | while (isr) { | |
ac93cdbd TG |
413 | if (isr & 1) |
414 | generic_handle_irq(pin); | |
73a59c1c | 415 | pin++; |
73a59c1c SP |
416 | isr >>= 1; |
417 | } | |
418 | } | |
ac93cdbd | 419 | chip->irq_unmask(idata); |
73a59c1c SP |
420 | /* now it may re-trigger */ |
421 | } | |
422 | ||
f2173834 AV |
423 | /*--------------------------------------------------------------------------*/ |
424 | ||
b66545e7 AV |
425 | #ifdef CONFIG_DEBUG_FS |
426 | ||
427 | static int at91_gpio_show(struct seq_file *s, void *unused) | |
428 | { | |
429 | int bank, j; | |
430 | ||
431 | /* print heading */ | |
432 | seq_printf(s, "Pin\t"); | |
433 | for (bank = 0; bank < gpio_banks; bank++) { | |
434 | seq_printf(s, "PIO%c\t", 'A' + bank); | |
435 | }; | |
436 | seq_printf(s, "\n\n"); | |
437 | ||
438 | /* print pin status */ | |
439 | for (j = 0; j < 32; j++) { | |
440 | seq_printf(s, "%i:\t", j); | |
441 | ||
442 | for (bank = 0; bank < gpio_banks; bank++) { | |
443 | unsigned pin = PIN_BASE + (32 * bank) + j; | |
444 | void __iomem *pio = pin_to_controller(pin); | |
445 | unsigned mask = pin_to_mask(pin); | |
446 | ||
447 | if (__raw_readl(pio + PIO_PSR) & mask) | |
448 | seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0"); | |
449 | else | |
450 | seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A"); | |
451 | ||
452 | seq_printf(s, "\t"); | |
453 | } | |
454 | ||
455 | seq_printf(s, "\n"); | |
456 | } | |
457 | ||
458 | return 0; | |
459 | } | |
460 | ||
461 | static int at91_gpio_open(struct inode *inode, struct file *file) | |
462 | { | |
463 | return single_open(file, at91_gpio_show, NULL); | |
464 | } | |
465 | ||
466 | static const struct file_operations at91_gpio_operations = { | |
467 | .open = at91_gpio_open, | |
468 | .read = seq_read, | |
469 | .llseek = seq_lseek, | |
470 | .release = single_release, | |
471 | }; | |
472 | ||
473 | static int __init at91_gpio_debugfs_init(void) | |
474 | { | |
475 | /* /sys/kernel/debug/at91_gpio */ | |
476 | (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations); | |
477 | return 0; | |
478 | } | |
479 | postcore_initcall(at91_gpio_debugfs_init); | |
480 | ||
481 | #endif | |
482 | ||
483 | /*--------------------------------------------------------------------------*/ | |
484 | ||
2b768b6c AV |
485 | /* |
486 | * This lock class tells lockdep that GPIO irqs are in a different | |
37aca70c DB |
487 | * category than their parents, so it won't report false recursion. |
488 | */ | |
489 | static struct lock_class_key gpio_lock_class; | |
490 | ||
f2173834 AV |
491 | /* |
492 | * Called from the processor-specific init to enable GPIO interrupt support. | |
493 | */ | |
494 | void __init at91_gpio_irq_setup(void) | |
73a59c1c | 495 | { |
e83aff58 | 496 | unsigned pioc, pin; |
f373e8c0 | 497 | struct at91_gpio_chip *this, *prev; |
73a59c1c | 498 | |
f373e8c0 | 499 | for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL; |
e83aff58 DB |
500 | pioc++ < gpio_banks; |
501 | prev = this, this++) { | |
f373e8c0 | 502 | unsigned id = this->bank->id; |
73a59c1c SP |
503 | unsigned i; |
504 | ||
e83aff58 | 505 | __raw_writel(~0, this->regbase + PIO_IDR); |
73a59c1c | 506 | |
f373e8c0 | 507 | for (i = 0, pin = this->chip.base; i < 32; i++, pin++) { |
1475b85d | 508 | irq_set_lockdep_class(pin, &gpio_lock_class); |
37aca70c | 509 | |
814138ff AV |
510 | /* |
511 | * Can use the "simple" and not "edge" handler since it's | |
3a4fa0a2 | 512 | * shorter, and the AIC handles interrupts sanely. |
814138ff | 513 | */ |
6845664a TG |
514 | irq_set_chip(pin, &gpio_irqchip); |
515 | irq_set_handler(pin, handle_simple_irq); | |
73a59c1c SP |
516 | set_irq_flags(pin, IRQF_VALID); |
517 | } | |
518 | ||
e83aff58 DB |
519 | /* The toplevel handler handles one bank of GPIOs, except |
520 | * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in | |
521 | * the list, so we only set up that handler. | |
522 | */ | |
523 | if (prev && prev->next == this) | |
524 | continue; | |
525 | ||
6845664a TG |
526 | irq_set_chip_data(id, this); |
527 | irq_set_chained_handler(id, gpio_irq_handler); | |
73a59c1c | 528 | } |
f2173834 AV |
529 | pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); |
530 | } | |
531 | ||
f373e8c0 RM |
532 | /* gpiolib support */ |
533 | static int at91_gpiolib_direction_input(struct gpio_chip *chip, | |
534 | unsigned offset) | |
535 | { | |
536 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
537 | void __iomem *pio = at91_gpio->regbase; | |
538 | unsigned mask = 1 << offset; | |
539 | ||
540 | __raw_writel(mask, pio + PIO_ODR); | |
541 | return 0; | |
542 | } | |
543 | ||
544 | static int at91_gpiolib_direction_output(struct gpio_chip *chip, | |
545 | unsigned offset, int val) | |
546 | { | |
547 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
548 | void __iomem *pio = at91_gpio->regbase; | |
549 | unsigned mask = 1 << offset; | |
550 | ||
551 | __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
552 | __raw_writel(mask, pio + PIO_OER); | |
553 | return 0; | |
554 | } | |
555 | ||
556 | static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset) | |
557 | { | |
558 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
559 | void __iomem *pio = at91_gpio->regbase; | |
560 | unsigned mask = 1 << offset; | |
561 | u32 pdsr; | |
562 | ||
563 | pdsr = __raw_readl(pio + PIO_PDSR); | |
564 | return (pdsr & mask) != 0; | |
565 | } | |
566 | ||
567 | static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val) | |
568 | { | |
569 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
570 | void __iomem *pio = at91_gpio->regbase; | |
571 | unsigned mask = 1 << offset; | |
572 | ||
573 | __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
574 | } | |
575 | ||
f373e8c0 RM |
576 | static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip) |
577 | { | |
578 | int i; | |
579 | ||
580 | for (i = 0; i < chip->ngpio; i++) { | |
581 | unsigned pin = chip->base + i; | |
582 | void __iomem *pio = pin_to_controller(pin); | |
583 | unsigned mask = pin_to_mask(pin); | |
584 | const char *gpio_label; | |
585 | ||
586 | gpio_label = gpiochip_is_requested(chip, i); | |
587 | if (gpio_label) { | |
588 | seq_printf(s, "[%s] GPIO%s%d: ", | |
589 | gpio_label, chip->label, i); | |
590 | if (__raw_readl(pio + PIO_PSR) & mask) | |
591 | seq_printf(s, "[gpio] %s\n", | |
592 | at91_get_gpio_value(pin) ? | |
593 | "set" : "clear"); | |
594 | else | |
595 | seq_printf(s, "[periph %s]\n", | |
596 | __raw_readl(pio + PIO_ABSR) & | |
597 | mask ? "B" : "A"); | |
598 | } | |
599 | } | |
600 | } | |
601 | ||
f2173834 AV |
602 | /* |
603 | * Called from the processor-specific init to enable GPIO pin support. | |
604 | */ | |
605 | void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) | |
606 | { | |
e83aff58 | 607 | unsigned i; |
f373e8c0 | 608 | struct at91_gpio_chip *at91_gpio, *last = NULL; |
e83aff58 | 609 | |
f2173834 AV |
610 | BUG_ON(nr_banks > MAX_GPIO_BANKS); |
611 | ||
f2173834 | 612 | gpio_banks = nr_banks; |
e83aff58 | 613 | |
f373e8c0 RM |
614 | for (i = 0; i < nr_banks; i++) { |
615 | at91_gpio = &gpio_chip[i]; | |
616 | ||
617 | at91_gpio->bank = &data[i]; | |
618 | at91_gpio->chip.base = PIN_BASE + i * 32; | |
619 | at91_gpio->regbase = at91_gpio->bank->offset + | |
620 | (void __iomem *)AT91_VA_BASE_SYS; | |
e83aff58 | 621 | |
2b768b6c | 622 | /* enable PIO controller's clock */ |
97fb44eb | 623 | clk_enable(at91_gpio->bank->clock); |
2b768b6c | 624 | |
e83aff58 | 625 | /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */ |
f373e8c0 RM |
626 | if (last && last->bank->id == at91_gpio->bank->id) |
627 | last->next = at91_gpio; | |
628 | last = at91_gpio; | |
629 | ||
630 | gpiochip_add(&at91_gpio->chip); | |
e83aff58 | 631 | } |
73a59c1c | 632 | } |