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f363c407 JCPV |
1 | /* |
2 | * Header file for the Atmel RAM Controller | |
3 | * | |
4 | * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
5 | * | |
6 | * Under GPLv2 only | |
7 | */ | |
8 | ||
9 | #ifndef __AT91_RAMC_H__ | |
10 | #define __AT91_RAMC_H__ | |
11 | ||
12 | #ifndef __ASSEMBLY__ | |
13 | extern void __iomem *at91_ramc_base[]; | |
14 | ||
15 | #define at91_ramc_read(id, field) \ | |
16 | __raw_readl(at91_ramc_base[id] + field) | |
17 | ||
18 | #define at91_ramc_write(id, field, value) \ | |
19 | __raw_writel(value, at91_ramc_base[id] + field) | |
20 | #else | |
21 | .extern at91_ramc_base | |
22 | #endif | |
23 | ||
fb7e197b JCPV |
24 | #define AT91_MEMCTRL_MC 0 |
25 | #define AT91_MEMCTRL_SDRAMC 1 | |
26 | #define AT91_MEMCTRL_DDRSDR 2 | |
27 | ||
f0a0a58e AB |
28 | #include <soc/at91/at91rm9200_sdramc.h> |
29 | #include <soc/at91/at91sam9_ddrsdr.h> | |
30 | #include <soc/at91/at91sam9_sdramc.h> | |
f363c407 JCPV |
31 | |
32 | #endif /* __AT91_RAMC_H__ */ |