[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-at91 / include / mach / at91_st.h

/*
 * arch/arm/mach-at91/include/mach/at91_st.h
 *
 * Copyright (C) 2005 Ivan Kokshaysky
 * Copyright (C) SAN People
 *
 * System Timer (ST) - System peripherals registers.
 * Based on AT91RM9200 datasheet revision E.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef AT91_ST_H
#define AT91_ST_H

#ifndef __ASSEMBLY__
extern void __iomem *at91_st_base;

#define at91_st_read(field) \
	__raw_readl(at91_st_base + field)

#define at91_st_write(field, value) \
	__raw_writel(value, at91_st_base + field)
#else
.extern at91_st_base
#endif

#define	AT91_ST_CR		0x00			/* Control Register */
#define 	AT91_ST_WDRST		(1 << 0)		/* Watchdog Timer Restart */

#define	AT91_ST_PIMR		0x04			/* Period Interval Mode Register */
#define		AT91_ST_PIV		(0xffff <<  0)		/* Period Interval Value */

#define	AT91_ST_WDMR		0x08			/* Watchdog Mode Register */
#define		AT91_ST_WDV		(0xffff <<  0)		/* Watchdog Counter Value */
#define		AT91_ST_RSTEN		(1	<< 16)		/* Reset Enable */
#define		AT91_ST_EXTEN		(1	<< 17)		/* External Signal Assertion Enable */

#define	AT91_ST_RTMR		0x0c			/* Real-time Mode Register */
#define		AT91_ST_RTPRES		(0xffff <<  0)		/* Real-time Prescalar Value */

#define	AT91_ST_SR		0x10			/* Status Register */
#define		AT91_ST_PITS		(1 << 0)		/* Period Interval Timer Status */
#define		AT91_ST_WDOVF		(1 << 1) 		/* Watchdog Overflow */
#define		AT91_ST_RTTINC		(1 << 2) 		/* Real-time Timer Increment */
#define		AT91_ST_ALMS		(1 << 3) 		/* Alarm Status */

#define	AT91_ST_IER		0x14			/* Interrupt Enable Register */
#define	AT91_ST_IDR		0x18			/* Interrupt Disable Register */
#define	AT91_ST_IMR		0x1c			/* Interrupt Mask Register */

#define	AT91_ST_RTAR		0x20			/* Real-time Alarm Register */
#define		AT91_ST_ALMV		(0xfffff << 0)		/* Alarm Value */

#define	AT91_ST_CRTR		0x24			/* Current Real-time Register */
#define		AT91_ST_CRTV		(0xfffff << 0)		/* Current Real-Time Value */

#endif
Commit	Line	Data
6171de8f	1	/*
a09e64fb	2	* arch/arm/mach-at91/include/mach/at91_st.h
6171de8f AV	3	*
	4	* Copyright (C) 2005 Ivan Kokshaysky
	5	* Copyright (C) SAN People
	6	*
	7	* System Timer (ST) - System peripherals registers.
	8	* Based on AT91RM9200 datasheet revision E.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*/
	15
	16	#ifndef AT91_ST_H
	17	#define AT91_ST_H
	18
5e9cf5e1 JCPV	19	#ifndef __ASSEMBLY__
	20	extern void __iomem *at91_st_base;
	21
	22	#define at91_st_read(field) \
	23	__raw_readl(at91_st_base + field)
	24
	25	#define at91_st_write(field, value) \
3aa630b3	26	__raw_writel(value, at91_st_base + field)
5e9cf5e1 JCPV	27	#else
	28	.extern at91_st_base
	29	#endif
	30
	31	#define AT91_ST_CR 0x00 /* Control Register */
6171de8f AV	32	#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
6171de8f AV	33
5e9cf5e1	34	#define AT91_ST_PIMR 0x04 /* Period Interval Mode Register */
6171de8f AV	35	#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
6171de8f AV	36
5e9cf5e1	37	#define AT91_ST_WDMR 0x08 /* Watchdog Mode Register */
6171de8f AV	38	#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
	39	#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
	40	#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
	41
5e9cf5e1	42	#define AT91_ST_RTMR 0x0c /* Real-time Mode Register */
6171de8f AV	43	#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
6171de8f AV	44
5e9cf5e1	45	#define AT91_ST_SR 0x10 /* Status Register */
6171de8f AV	46	#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
	47	#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
	48	#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
	49	#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
	50
5e9cf5e1 JCPV	51	#define AT91_ST_IER 0x14 /* Interrupt Enable Register */
	52	#define AT91_ST_IDR 0x18 /* Interrupt Disable Register */
	53	#define AT91_ST_IMR 0x1c /* Interrupt Mask Register */
6171de8f	54
5e9cf5e1	55	#define AT91_ST_RTAR 0x20 /* Real-time Alarm Register */
6171de8f AV	56	#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
6171de8f AV	57
5e9cf5e1	58	#define AT91_ST_CRTR 0x24 /* Current Real-time Register */
6171de8f AV	59	#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
	60
	61	#endif