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73a59c1c | 1 | /* |
8fc5ffa0 | 2 | * linux/arch/arm/mach-at91rm9200/at91rm9200_time.c |
73a59c1c SP |
3 | * |
4 | * Copyright (C) 2003 SAN People | |
5 | * Copyright (C) 2003 ATMEL | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
73a59c1c SP |
22 | #include <linux/init.h> |
23 | #include <linux/interrupt.h> | |
07d265dd | 24 | #include <linux/irq.h> |
73a59c1c SP |
25 | #include <linux/kernel.h> |
26 | #include <linux/sched.h> | |
27 | #include <linux/time.h> | |
28 | ||
29 | #include <asm/hardware.h> | |
30 | #include <asm/io.h> | |
73a59c1c SP |
31 | #include <asm/mach/time.h> |
32 | ||
55d8baee AV |
33 | #include <asm/arch/at91_st.h> |
34 | ||
963151f2 AV |
35 | static unsigned long last_crtr; |
36 | ||
73a59c1c SP |
37 | /* |
38 | * The ST_CRTR is updated asynchronously to the master clock. It is therefore | |
39 | * necessary to read it twice (with the same value) to ensure accuracy. | |
40 | */ | |
41 | static inline unsigned long read_CRTR(void) { | |
42 | unsigned long x1, x2; | |
43 | ||
44 | do { | |
45 | x1 = at91_sys_read(AT91_ST_CRTR); | |
46 | x2 = at91_sys_read(AT91_ST_CRTR); | |
47 | } while (x1 != x2); | |
48 | ||
49 | return x1; | |
50 | } | |
51 | ||
52 | /* | |
53 | * Returns number of microseconds since last timer interrupt. Note that interrupts | |
54 | * will have been disabled by do_gettimeofday() | |
55 | * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy. | |
56 | * 'tick' is usecs per jiffy (linux/timex.h). | |
57 | */ | |
58 | static unsigned long at91rm9200_gettimeoffset(void) | |
59 | { | |
60 | unsigned long elapsed; | |
61 | ||
963151f2 | 62 | elapsed = (read_CRTR() - last_crtr) & AT91_ST_ALMV; |
73a59c1c SP |
63 | |
64 | return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH; | |
65 | } | |
66 | ||
67 | /* | |
68 | * IRQ handler for the timer. | |
69 | */ | |
0cd61b68 | 70 | static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) |
73a59c1c | 71 | { |
73a59c1c SP |
72 | if (at91_sys_read(AT91_ST_SR) & AT91_ST_PITS) { /* This is a shared interrupt */ |
73 | write_seqlock(&xtime_lock); | |
74 | ||
963151f2 | 75 | while (((read_CRTR() - last_crtr) & AT91_ST_ALMV) >= LATCH) { |
0cd61b68 | 76 | timer_tick(); |
963151f2 | 77 | last_crtr = (last_crtr + LATCH) & AT91_ST_ALMV; |
39806805 | 78 | } |
73a59c1c SP |
79 | |
80 | write_sequnlock(&xtime_lock); | |
81 | ||
82 | return IRQ_HANDLED; | |
83 | } | |
84 | else | |
85 | return IRQ_NONE; /* not handled */ | |
86 | } | |
87 | ||
88 | static struct irqaction at91rm9200_timer_irq = { | |
89 | .name = "at91_tick", | |
52e405ea | 90 | .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER, |
73a59c1c SP |
91 | .handler = at91rm9200_timer_interrupt |
92 | }; | |
93 | ||
2a6f9902 AV |
94 | void at91rm9200_timer_reset(void) |
95 | { | |
96 | last_crtr = 0; | |
97 | ||
98 | /* Real time counter incremented every 30.51758 microseconds */ | |
99 | at91_sys_write(AT91_ST_RTMR, 1); | |
100 | ||
101 | /* Set Period Interval timer */ | |
102 | at91_sys_write(AT91_ST_PIMR, LATCH); | |
103 | ||
104 | /* Enable Period Interval Timer interrupt */ | |
105 | at91_sys_write(AT91_ST_IER, AT91_ST_PITS); | |
106 | } | |
107 | ||
73a59c1c SP |
108 | /* |
109 | * Set up timer interrupt. | |
110 | */ | |
111 | void __init at91rm9200_timer_init(void) | |
112 | { | |
113 | /* Disable all timer interrupts */ | |
114 | at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); | |
115 | (void) at91_sys_read(AT91_ST_SR); /* Clear any pending interrupts */ | |
116 | ||
2a6f9902 | 117 | /* Make IRQs happen for the system timer */ |
73a59c1c SP |
118 | setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq); |
119 | ||
73a59c1c SP |
120 | /* Change the kernel's 'tick' value to 10009 usec. (the default is 10000) */ |
121 | tick_usec = (LATCH * 1000000) / CLOCK_TICK_RATE; | |
122 | ||
2a6f9902 AV |
123 | /* Initialize and enable the timer interrupt */ |
124 | at91rm9200_timer_reset(); | |
125 | } | |
126 | ||
127 | #ifdef CONFIG_PM | |
128 | static void at91rm9200_timer_suspend(void) | |
129 | { | |
130 | /* disable Period Interval Timer interrupt */ | |
131 | at91_sys_write(AT91_ST_IDR, AT91_ST_PITS); | |
73a59c1c | 132 | } |
2a6f9902 AV |
133 | #else |
134 | #define at91rm9200_timer_suspend NULL | |
135 | #endif | |
73a59c1c SP |
136 | |
137 | struct sys_timer at91rm9200_timer = { | |
138 | .init = at91rm9200_timer_init, | |
139 | .offset = at91rm9200_gettimeoffset, | |
2a6f9902 AV |
140 | .suspend = at91rm9200_timer_suspend, |
141 | .resume = at91rm9200_timer_reset, | |
73a59c1c | 142 | }; |
2a6f9902 | 143 |