[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-at91rm9200 / clock.c

/*
 * linux/arch/arm/mach-at91rm9200/clock.c
 *
 * Copyright (C) 2005 David Brownell
 * Copyright (C) 2005 Ivan Kokshaysky
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/clk.h>

#include <asm/semaphore.h>
#include <asm/io.h>
#include <asm/mach-types.h>

#include <asm/hardware.h>

#include "generic.h"


/*
 * There's a lot more which can be done with clocks, including cpufreq
 * integration, slow clock mode support (for system suspend), letting
 * PLLB be used at other rates (on boards that don't need USB), etc.
 */

struct clk {
	const char	*name;		/* unique clock name */
	const char	*function;	/* function of the clock */
	struct device	*dev;		/* device associated with function */
	unsigned long	rate_hz;
	struct clk	*parent;
	u32		pmc_mask;
	void		(*mode)(struct clk *, int);
	unsigned	id:2;		/* PCK0..3, or 32k/main/a/b */
	unsigned	primary:1;
	unsigned	pll:1;
	unsigned	programmable:1;
	u16		users;
};

static spinlock_t	clk_lock;
static u32		at91_pllb_usb_init;

/*
 * Four primary clock sources:  two crystal oscillators (32K, main), and
 * two PLLs.  PLLA usually runs the master clock; and PLLB must run at
 * 48 MHz (unless no USB function clocks are needed).  The main clock and
 * both PLLs are turned off to run in "slow clock mode" (system suspend).
 */
static struct clk clk32k = {
	.name		= "clk32k",
	.rate_hz	= AT91_SLOW_CLOCK,
	.users		= 1,		/* always on */
	.id		= 0,
	.primary	= 1,
};
static struct clk main_clk = {
	.name		= "main",
	.pmc_mask	= AT91_PMC_MOSCS,	/* in PMC_SR */
	.id		= 1,
	.primary	= 1,
};
static struct clk plla = {
	.name		= "plla",
	.parent		= &main_clk,
	.pmc_mask	= AT91_PMC_LOCKA,	/* in PMC_SR */
	.id		= 2,
	.primary	= 1,
	.pll		= 1,
};

static void pllb_mode(struct clk *clk, int is_on)
{
	u32	value;

	if (is_on) {
		is_on = AT91_PMC_LOCKB;
		value = at91_pllb_usb_init;
	} else
		value = 0;

	at91_sys_write(AT91_CKGR_PLLBR, value);

	do {
		cpu_relax();
	} while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
}

static struct clk pllb = {
	.name		= "pllb",
	.parent		= &main_clk,
	.pmc_mask	= AT91_PMC_LOCKB,	/* in PMC_SR */
	.mode		= pllb_mode,
	.id		= 3,
	.primary	= 1,
	.pll		= 1,
};

static void pmc_sys_mode(struct clk *clk, int is_on)
{
	if (is_on)
		at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
	else
		at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
}

/* USB function clocks (PLLB must be 48 MHz) */
static struct clk udpck = {
	.name		= "udpck",
	.parent		= &pllb,
	.pmc_mask	= AT91_PMC_UDP,
	.mode		= pmc_sys_mode,
};
static struct clk uhpck = {
	.name		= "uhpck",
	.parent		= &pllb,
	.pmc_mask	= AT91_PMC_UHP,
	.mode		= pmc_sys_mode,
};

#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
/*
 * The four programmable clocks can be parented by any primary clock.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.mode		= pmc_sys_mode,
	.programmable	= 1,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.mode		= pmc_sys_mode,
	.programmable	= 1,
	.id		= 1,
};
static struct clk pck2 = {
	.name		= "pck2",
	.pmc_mask	= AT91_PMC_PCK2,
	.mode		= pmc_sys_mode,
	.programmable	= 1,
	.id		= 2,
};
static struct clk pck3 = {
	.name		= "pck3",
	.pmc_mask	= AT91_PMC_PCK3,
	.mode		= pmc_sys_mode,
	.programmable	= 1,
	.id		= 3,
};
#endif	/* CONFIG_AT91_PROGRAMMABLE_CLOCKS */


/*
 * The master clock is divided from the CPU clock (by 1-4).  It's used for
 * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
 * (e.g baud rate generation).  It's sourced from one of the primary clocks.
 */
static struct clk mck = {
	.name		= "mck",
	.pmc_mask	= AT91_PMC_MCKRDY,	/* in PMC_SR */
};

static void pmc_periph_mode(struct clk *clk, int is_on)
{
	if (is_on)
		at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
	else
		at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
}

static struct clk udc_clk = {
	.name		= "udc_clk",
	.parent		= &mck,
	.pmc_mask	= 1 << AT91RM9200_ID_UDP,
	.mode		= pmc_periph_mode,
};
static struct clk ohci_clk = {
	.name		= "ohci_clk",
	.parent		= &mck,
	.pmc_mask	= 1 << AT91RM9200_ID_UHP,
	.mode		= pmc_periph_mode,
};
static struct clk ether_clk = {
	.name		= "ether_clk",
	.parent		= &mck,
	.pmc_mask	= 1 << AT91RM9200_ID_EMAC,
	.mode		= pmc_periph_mode,
};
static struct clk mmc_clk = {
	.name		= "mci_clk",
	.parent		= &mck,
	.pmc_mask	= 1 << AT91RM9200_ID_MCI,
	.mode		= pmc_periph_mode,
};
static struct clk twi_clk = {
	.name		= "twi_clk",
	.parent		= &mck,
	.pmc_mask	= 1 << AT91RM9200_ID_TWI,
	.mode		= pmc_periph_mode,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.parent		= &mck,
	.pmc_mask	= 1 << AT91RM9200_ID_US0,
	.mode		= pmc_periph_mode,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.parent		= &mck,
	.pmc_mask	= 1 << AT91RM9200_ID_US1,
	.mode		= pmc_periph_mode,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.parent		= &mck,
	.pmc_mask	= 1 << AT91RM9200_ID_US2,
	.mode		= pmc_periph_mode,
};
static struct clk usart3_clk = {
	.name		= "usart3_clk",
	.parent		= &mck,
	.pmc_mask	= 1 << AT91RM9200_ID_US3,
	.mode		= pmc_periph_mode,
};
static struct clk spi_clk = {
	.name		= "spi0_clk",
	.parent		= &mck,
	.pmc_mask	= 1 << AT91RM9200_ID_SPI,
	.mode		= pmc_periph_mode,
};
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.parent		= &mck,
	.pmc_mask	= 1 << AT91RM9200_ID_PIOA,
	.mode		= pmc_periph_mode,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.parent		= &mck,
	.pmc_mask	= 1 << AT91RM9200_ID_PIOB,
	.mode		= pmc_periph_mode,
};
static struct clk pioC_clk = {
	.name		= "pioC_clk",
	.parent		= &mck,
	.pmc_mask	= 1 << AT91RM9200_ID_PIOC,
	.mode		= pmc_periph_mode,
};
static struct clk pioD_clk = {
	.name		= "pioD_clk",
	.parent		= &mck,
	.pmc_mask	= 1 << AT91RM9200_ID_PIOD,
	.mode		= pmc_periph_mode,
};

static struct clk *const clock_list[] = {
	/* four primary clocks -- MUST BE FIRST! */
	&clk32k,
	&main_clk,
	&plla,
	&pllb,

	/* PLLB children (USB) */
	&udpck,
	&uhpck,

#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
	/* programmable clocks */
	&pck0,
	&pck1,
	&pck2,
	&pck3,
#endif	/* CONFIG_AT91_PROGRAMMABLE_CLOCKS */

	/* MCK and peripherals */
	&mck,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&usart3_clk,
	&mmc_clk,
	&udc_clk,
	&twi_clk,
	&spi_clk,
	&pioA_clk,
	&pioB_clk,
	&pioC_clk,
	&pioD_clk,
	// ssc0..ssc2
	// tc0..tc5
	// irq0..irq6
	&ohci_clk,
	&ether_clk,
};


/*
 * Associate a particular clock with a function (eg, "uart") and device.
 * The drivers can then request the same 'function' with several different
 * devices and not care about which clock name to use.
 */
void __init at91_clock_associate(const char *id, struct device *dev, const char *func)
{
	struct clk *clk = clk_get(NULL, id);

	if (!dev || !clk || !IS_ERR(clk_get(dev, func)))
		return;

	clk->function = func;
	clk->dev = dev;
}

/* clocks are all static for now; no refcounting necessary */
struct clk *clk_get(struct device *dev, const char *id)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
		struct clk *clk = clock_list[i];

		if (strcmp(id, clk->name) == 0)
			return clk;
		if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0)
			return clk;
	}

	return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);

void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);

static void __clk_enable(struct clk *clk)
{
	if (clk->parent)
		__clk_enable(clk->parent);
	if (clk->users++ == 0 && clk->mode)
		clk->mode(clk, 1);
}

int clk_enable(struct clk *clk)
{
	unsigned long	flags;

	spin_lock_irqsave(&clk_lock, flags);
	__clk_enable(clk);
	spin_unlock_irqrestore(&clk_lock, flags);
	return 0;
}
EXPORT_SYMBOL(clk_enable);

static void __clk_disable(struct clk *clk)
{
	BUG_ON(clk->users == 0);
	if (--clk->users == 0 && clk->mode)
		clk->mode(clk, 0);
	if (clk->parent)
		__clk_disable(clk->parent);
}

void clk_disable(struct clk *clk)
{
	unsigned long	flags;

	spin_lock_irqsave(&clk_lock, flags);
	__clk_disable(clk);
	spin_unlock_irqrestore(&clk_lock, flags);
}
EXPORT_SYMBOL(clk_disable);

unsigned long clk_get_rate(struct clk *clk)
{
	unsigned long	flags;
	unsigned long	rate;

	spin_lock_irqsave(&clk_lock, flags);
	for (;;) {
		rate = clk->rate_hz;
		if (rate || !clk->parent)
			break;
		clk = clk->parent;
	}
	spin_unlock_irqrestore(&clk_lock, flags);
	return rate;
}
EXPORT_SYMBOL(clk_get_rate);

/*------------------------------------------------------------------------*/

#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS

/*
 * For now, only the programmable clocks support reparenting (MCK could
 * do this too, with care) or rate changing (the PLLs could do this too,
 * ditto MCK but that's more for cpufreq).  Drivers may reparent to get
 * a better rate match; we don't.
 */

long clk_round_rate(struct clk *clk, unsigned long rate)
{
	unsigned long	flags;
	unsigned	prescale;
	unsigned long	actual;

	if (!clk->programmable)
		return -EINVAL;
	spin_lock_irqsave(&clk_lock, flags);

	actual = clk->parent->rate_hz;
	for (prescale = 0; prescale < 7; prescale++) {
		if (actual && actual <= rate)
			break;
		actual >>= 1;
	}

	spin_unlock_irqrestore(&clk_lock, flags);
	return (prescale < 7) ? actual : -ENOENT;
}
EXPORT_SYMBOL(clk_round_rate);

int clk_set_rate(struct clk *clk, unsigned long rate)
{
	unsigned long	flags;
	unsigned	prescale;
	unsigned long	actual;

	if (!clk->programmable)
		return -EINVAL;
	if (clk->users)
		return -EBUSY;
	spin_lock_irqsave(&clk_lock, flags);

	actual = clk->parent->rate_hz;
	for (prescale = 0; prescale < 7; prescale++) {
		if (actual && actual <= rate) {
			u32	pckr;

			pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
			pckr &= AT91_PMC_CSS_PLLB;	/* clock selection */
			pckr |= prescale << 2;
			at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
			clk->rate_hz = actual;
			break;
		}
		actual >>= 1;
	}

	spin_unlock_irqrestore(&clk_lock, flags);
	return (prescale < 7) ? actual : -ENOENT;
}
EXPORT_SYMBOL(clk_set_rate);

struct clk *clk_get_parent(struct clk *clk)
{
	return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);

int clk_set_parent(struct clk *clk, struct clk *parent)
{
	unsigned long	flags;

	if (clk->users)
		return -EBUSY;
	if (!parent->primary || !clk->programmable)
		return -EINVAL;
	spin_lock_irqsave(&clk_lock, flags);

	clk->rate_hz = parent->rate_hz;
	clk->parent = parent;
	at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);

	spin_unlock_irqrestore(&clk_lock, flags);
	return 0;
}
EXPORT_SYMBOL(clk_set_parent);

#endif	/* CONFIG_AT91_PROGRAMMABLE_CLOCKS */

/*------------------------------------------------------------------------*/

#ifdef CONFIG_DEBUG_FS

static int at91_clk_show(struct seq_file *s, void *unused)
{
	u32		scsr, pcsr, sr;
	unsigned	i;

	seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
	seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));

	seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
	seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
	seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
	seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));

	seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
	for (i = 0; i < 4; i++)
		seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i)));
	seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));

	seq_printf(s, "\n");

	for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
		char		*state;
		struct clk	*clk = clock_list[i];

		if (clk->mode == pmc_sys_mode)
			state = (scsr & clk->pmc_mask) ? "on" : "off";
		else if (clk->mode == pmc_periph_mode)
			state = (pcsr & clk->pmc_mask) ? "on" : "off";
		else if (clk->pmc_mask)
			state = (sr & clk->pmc_mask) ? "on" : "off";
		else if (clk == &clk32k || clk == &main_clk)
			state = "on";
		else
			state = "";

		seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
			clk->name, clk->users, state, clk_get_rate(clk),
			clk->parent ? clk->parent->name : "");
	}
	return 0;
}

static int at91_clk_open(struct inode *inode, struct file *file)
{
	return single_open(file, at91_clk_show, NULL);
}

static struct file_operations at91_clk_operations = {
	.open		= at91_clk_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init at91_clk_debugfs_init(void)
{
	/* /sys/kernel/debug/at91_clk */
	(void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);

	return 0;
}
postcore_initcall(at91_clk_debugfs_init);

#endif

/*------------------------------------------------------------------------*/

static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
{
	unsigned mul, div;

	div = reg & 0xff;
	mul = (reg >> 16) & 0x7ff;
	if (div && mul) {
		freq /= div;
		freq *= mul + 1;
	} else
		freq = 0;

	return freq;
}

static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
{
	if (pll == &pllb && (reg & AT91_PMC_USB96M))
		return freq / 2;
	else
		return freq;
}

static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
{
	unsigned i, div = 0, mul = 0, diff = 1 << 30;
	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;

	/* PLL output max 240 MHz (or 180 MHz per errata) */
	if (out_freq > 240000000)
		goto fail;

	for (i = 1; i < 256; i++) {
		int diff1;
		unsigned input, mul1;

		/*
		 * PLL input between 1MHz and 32MHz per spec, but lower
		 * frequences seem necessary in some cases so allow 100K.
		 */
		input = main_freq / i;
		if (input < 100000)
			continue;
		if (input > 32000000)
			continue;

		mul1 = out_freq / input;
		if (mul1 > 2048)
			continue;
		if (mul1 < 2)
			goto fail;

		diff1 = out_freq - input * mul1;
		if (diff1 < 0)
			diff1 = -diff1;
		if (diff > diff1) {
			diff = diff1;
			div = i;
			mul = mul1;
			if (diff == 0)
				break;
		}
	}
	if (i == 256 && diff > (out_freq >> 5))
		goto fail;
	return ret | ((mul - 1) << 16) | div;
fail:
	return 0;
}


/*
 * Several unused clocks may be active.  Turn them off.
 */
static void at91_periphclk_reset(void)
{
	unsigned long reg;
	int i;

	reg = at91_sys_read(AT91_PMC_PCSR);

	for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
		struct clk	*clk = clock_list[i];

		if (clk->mode != pmc_periph_mode)
			continue;

		if (clk->users > 0)
			reg &= ~clk->pmc_mask;
	}

	at91_sys_write(AT91_PMC_PCDR, reg);
}

int __init at91_clock_init(unsigned long main_clock)
{
	unsigned tmp, freq, mckr;

	spin_lock_init(&clk_lock);

	/*
	 * When the bootloader initialized the main oscillator correctly,
	 * there's no problem using the cycle counter.  But if it didn't,
	 * or when using oscillator bypass mode, we must be told the speed
	 * of the main clock.
	 */
	if (!main_clock) {
		do {
			tmp = at91_sys_read(AT91_CKGR_MCFR);
		} while (!(tmp & AT91_PMC_MAINRDY));
		main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
	}
	main_clk.rate_hz = main_clock;

	/* report if PLLA is more than mildly overclocked */
	plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
	if (plla.rate_hz > 209000000)
		pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);

	/*
	 * USB clock init:  choose 48 MHz PLLB value, turn all clocks off,
	 * disable 48MHz clock during usb peripheral suspend.
	 *
	 * REVISIT:  assumes MCK doesn't derive from PLLB!
	 */
	at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
	pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP | AT91_PMC_UDP);
	at91_sys_write(AT91_CKGR_PLLBR, 0);
	at91_sys_write(AT91_PMC_SCER, AT91_PMC_MCKUDP);

	udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
	uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);

	/*
	 * MCK and CPU derive from one of those primary clocks.
	 * For now, assume this parentage won't change.
	 */
	mckr = at91_sys_read(AT91_PMC_MCKR);
	mck.parent = clock_list[mckr & AT91_PMC_CSS];
	freq = mck.parent->rate_hz;
	freq /= (1 << ((mckr >> 2) & 3));		/* prescale */
	mck.rate_hz = freq / (1 + ((mckr >> 8) & 3));	/* mdiv */

	/* MCK and CPU clock are "always on" */
	clk_enable(&mck);

	printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
		freq / 1000000, (unsigned) mck.rate_hz / 1000000,
		(unsigned) main_clock / 1000000,
		((unsigned) main_clock % 1000000) / 1000);

#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
	/* establish PCK0..PCK3 parentage */
	for (tmp = 0; tmp < ARRAY_SIZE(clock_list); tmp++) {
		struct clk	*clk = clock_list[tmp], *parent;
		u32		pckr;

		if (!clk->programmable)
			continue;

		pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
		parent = clock_list[pckr & AT91_PMC_CSS];
		clk->parent = parent;
		clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3));

		if (clk->users == 0) {
			/* not being used, so switch it off */
			at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
		}
	}
#else
	/* disable all programmable clocks */
	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 | AT91_PMC_PCK1 | AT91_PMC_PCK2 | AT91_PMC_PCK3);
#endif

	/* enable the PIO clocks */
	clk_enable(&pioA_clk);
	clk_enable(&pioB_clk);
	clk_enable(&pioC_clk);
	clk_enable(&pioD_clk);

	/* disable all other unused peripheral clocks */
	at91_periphclk_reset();

	return 0;
}
Commit	Line	Data
73a59c1c SP	1	/*
	2	* linux/arch/arm/mach-at91rm9200/clock.c
	3	*
	4	* Copyright (C) 2005 David Brownell
	5	* Copyright (C) 2005 Ivan Kokshaysky
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
	12
	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/fs.h>
	17	#include <linux/debugfs.h>
	18	#include <linux/seq_file.h>
	19	#include <linux/list.h>
	20	#include <linux/errno.h>
	21	#include <linux/err.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/delay.h>
	24	#include <linux/clk.h>
	25
	26	#include <asm/semaphore.h>
	27	#include <asm/io.h>
	28	#include <asm/mach-types.h>
	29
ea75ee9a	30	#include <asm/hardware.h>
73a59c1c SP	31
	32	#include "generic.h"
	33
55c20c0a	34
73a59c1c SP	35	/*
	36	* There's a lot more which can be done with clocks, including cpufreq
	37	* integration, slow clock mode support (for system suspend), letting
	38	* PLLB be used at other rates (on boards that don't need USB), etc.
	39	*/
	40
	41	struct clk {
91f8ed83 AV	42	const char name; / unique clock name */
	43	const char function; / function of the clock */
	44	struct device dev; / device associated with function */
73a59c1c SP	45	unsigned long rate_hz;
	46	struct clk *parent;
	47	u32 pmc_mask;
	48	void (mode)(struct clk , int);
	49	unsigned id:2; /* PCK0..3, or 32k/main/a/b */
	50	unsigned primary:1;
	51	unsigned pll:1;
	52	unsigned programmable:1;
	53	u16 users;
	54	};
	55
	56	static spinlock_t clk_lock;
	57	static u32 at91_pllb_usb_init;
	58
	59	/*
	60	* Four primary clock sources: two crystal oscillators (32K, main), and
	61	* two PLLs. PLLA usually runs the master clock; and PLLB must run at
	62	* 48 MHz (unless no USB function clocks are needed). The main clock and
	63	* both PLLs are turned off to run in "slow clock mode" (system suspend).
	64	*/
	65	static struct clk clk32k = {
	66	.name = "clk32k",
	67	.rate_hz = AT91_SLOW_CLOCK,
	68	.users = 1, /* always on */
	69	.id = 0,
	70	.primary = 1,
	71	};
	72	static struct clk main_clk = {
	73	.name = "main",
91f8ed83	74	.pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
73a59c1c SP	75	.id = 1,
	76	.primary = 1,
	77	};
	78	static struct clk plla = {
	79	.name = "plla",
	80	.parent = &main_clk,
91f8ed83	81	.pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
73a59c1c SP	82	.id = 2,
	83	.primary = 1,
	84	.pll = 1,
	85	};
	86
	87	static void pllb_mode(struct clk *clk, int is_on)
	88	{
	89	u32 value;
	90
	91	if (is_on) {
	92	is_on = AT91_PMC_LOCKB;
	93	value = at91_pllb_usb_init;
	94	} else
	95	value = 0;
	96
	97	at91_sys_write(AT91_CKGR_PLLBR, value);
	98
	99	do {
	100	cpu_relax();
	101	} while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
	102	}
	103
	104	static struct clk pllb = {
	105	.name = "pllb",
	106	.parent = &main_clk,
91f8ed83	107	.pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
73a59c1c SP	108	.mode = pllb_mode,
	109	.id = 3,
	110	.primary = 1,
	111	.pll = 1,
	112	};
	113
	114	static void pmc_sys_mode(struct clk *clk, int is_on)
	115	{
	116	if (is_on)
	117	at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
	118	else
	119	at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
	120	}
	121
	122	/* USB function clocks (PLLB must be 48 MHz) */
	123	static struct clk udpck = {
	124	.name = "udpck",
	125	.parent = &pllb,
	126	.pmc_mask = AT91_PMC_UDP,
	127	.mode = pmc_sys_mode,
	128	};
	129	static struct clk uhpck = {
	130	.name = "uhpck",
	131	.parent = &pllb,
	132	.pmc_mask = AT91_PMC_UHP,
	133	.mode = pmc_sys_mode,
	134	};
	135
	136	#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
	137	/*
	138	* The four programmable clocks can be parented by any primary clock.
	139	* You must configure pin multiplexing to bring these signals out.
	140	*/
	141	static struct clk pck0 = {
	142	.name = "pck0",
	143	.pmc_mask = AT91_PMC_PCK0,
	144	.mode = pmc_sys_mode,
	145	.programmable = 1,
	146	.id = 0,
	147	};
	148	static struct clk pck1 = {
	149	.name = "pck1",
	150	.pmc_mask = AT91_PMC_PCK1,
	151	.mode = pmc_sys_mode,
	152	.programmable = 1,
	153	.id = 1,
	154	};
	155	static struct clk pck2 = {
	156	.name = "pck2",
	157	.pmc_mask = AT91_PMC_PCK2,
	158	.mode = pmc_sys_mode,
	159	.programmable = 1,
	160	.id = 2,
	161	};
	162	static struct clk pck3 = {
	163	.name = "pck3",
	164	.pmc_mask = AT91_PMC_PCK3,
	165	.mode = pmc_sys_mode,
	166	.programmable = 1,
	167	.id = 3,
	168	};
	169	#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
	170
	171
172	/*
173	* The master clock is divided from the CPU clock (by 1-4). It's used for
174	* memory, interfaces to on-chip peripherals, the AIC, and sometimes more
175	* (e.g baud rate generation). It's sourced from one of the primary clocks.
176	*/
177	static struct clk mck = {
178	.name = "mck",
91f8ed83	179	.pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */
73a59c1c SP	180	};
	181
	182	static void pmc_periph_mode(struct clk *clk, int is_on)
	183	{
	184	if (is_on)
	185	at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
	186	else
	187	at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
	188	}
	189
	190	static struct clk udc_clk = {
	191	.name = "udc_clk",
	192	.parent = &mck,
72729910	193	.pmc_mask = 1 << AT91RM9200_ID_UDP,
73a59c1c SP	194	.mode = pmc_periph_mode,
	195	};
	196	static struct clk ohci_clk = {
	197	.name = "ohci_clk",
	198	.parent = &mck,
72729910	199	.pmc_mask = 1 << AT91RM9200_ID_UHP,
73a59c1c SP	200	.mode = pmc_periph_mode,
73a59c1c SP	201	};
69b648a2 AV	202	static struct clk ether_clk = {
	203	.name = "ether_clk",
	204	.parent = &mck,
72729910	205	.pmc_mask = 1 << AT91RM9200_ID_EMAC,
69b648a2 AV	206	.mode = pmc_periph_mode,
	207	};
	208	static struct clk mmc_clk = {
	209	.name = "mci_clk",
	210	.parent = &mck,
72729910	211	.pmc_mask = 1 << AT91RM9200_ID_MCI,
69b648a2 AV	212	.mode = pmc_periph_mode,
	213	};
	214	static struct clk twi_clk = {
	215	.name = "twi_clk",
	216	.parent = &mck,
72729910	217	.pmc_mask = 1 << AT91RM9200_ID_TWI,
69b648a2 AV	218	.mode = pmc_periph_mode,
	219	};
	220	static struct clk usart0_clk = {
	221	.name = "usart0_clk",
	222	.parent = &mck,
72729910	223	.pmc_mask = 1 << AT91RM9200_ID_US0,
69b648a2 AV	224	.mode = pmc_periph_mode,
	225	};
	226	static struct clk usart1_clk = {
	227	.name = "usart1_clk",
	228	.parent = &mck,
72729910	229	.pmc_mask = 1 << AT91RM9200_ID_US1,
69b648a2 AV	230	.mode = pmc_periph_mode,
	231	};
	232	static struct clk usart2_clk = {
	233	.name = "usart2_clk",
	234	.parent = &mck,
72729910	235	.pmc_mask = 1 << AT91RM9200_ID_US2,
69b648a2 AV	236	.mode = pmc_periph_mode,
	237	};
	238	static struct clk usart3_clk = {
	239	.name = "usart3_clk",
	240	.parent = &mck,
72729910	241	.pmc_mask = 1 << AT91RM9200_ID_US3,
69b648a2 AV	242	.mode = pmc_periph_mode,
	243	};
	244	static struct clk spi_clk = {
	245	.name = "spi0_clk",
	246	.parent = &mck,
72729910	247	.pmc_mask = 1 << AT91RM9200_ID_SPI,
69b648a2 AV	248	.mode = pmc_periph_mode,
69b648a2 AV	249	};
91f8ed83 AV	250	static struct clk pioA_clk = {
	251	.name = "pioA_clk",
	252	.parent = &mck,
72729910	253	.pmc_mask = 1 << AT91RM9200_ID_PIOA,
91f8ed83 AV	254	.mode = pmc_periph_mode,
	255	};
	256	static struct clk pioB_clk = {
	257	.name = "pioB_clk",
	258	.parent = &mck,
72729910	259	.pmc_mask = 1 << AT91RM9200_ID_PIOB,
91f8ed83 AV	260	.mode = pmc_periph_mode,
	261	};
	262	static struct clk pioC_clk = {
	263	.name = "pioC_clk",
	264	.parent = &mck,
72729910	265	.pmc_mask = 1 << AT91RM9200_ID_PIOC,
91f8ed83 AV	266	.mode = pmc_periph_mode,
	267	};
	268	static struct clk pioD_clk = {
	269	.name = "pioD_clk",
	270	.parent = &mck,
72729910	271	.pmc_mask = 1 << AT91RM9200_ID_PIOD,
91f8ed83 AV	272	.mode = pmc_periph_mode,
91f8ed83 AV	273	};
73a59c1c SP	274
	275	static struct clk *const clock_list[] = {
	276	/* four primary clocks -- MUST BE FIRST! */
	277	&clk32k,
	278	&main_clk,
	279	&plla,
	280	&pllb,
	281
	282	/* PLLB children (USB) */
	283	&udpck,
	284	&uhpck,
	285
	286	#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
	287	/* programmable clocks */
	288	&pck0,
	289	&pck1,
	290	&pck2,
	291	&pck3,
	292	#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
	293
	294	/* MCK and peripherals */
	295	&mck,
69b648a2 AV	296	&usart0_clk,
	297	&usart1_clk,
	298	&usart2_clk,
	299	&usart3_clk,
	300	&mmc_clk,
73a59c1c	301	&udc_clk,
69b648a2 AV	302	&twi_clk,
69b648a2 AV	303	&spi_clk,
91f8ed83 AV	304	&pioA_clk,
	305	&pioB_clk,
	306	&pioC_clk,
	307	&pioD_clk,
73a59c1c SP	308	// ssc0..ssc2
73a59c1c SP	309	// tc0..tc5
91f8ed83	310	// irq0..irq6
73a59c1c	311	&ohci_clk,
69b648a2	312	&ether_clk,
73a59c1c SP	313	};
	314
	315
91f8ed83 AV	316	/*
	317	* Associate a particular clock with a function (eg, "uart") and device.
	318	* The drivers can then request the same 'function' with several different
	319	* devices and not care about which clock name to use.
	320	*/
	321	void __init at91_clock_associate(const char id, struct device dev, const char *func)
	322	{
	323	struct clk *clk = clk_get(NULL, id);
	324
	325	if (!dev \|\| !clk \|\| !IS_ERR(clk_get(dev, func)))
	326	return;
	327
	328	clk->function = func;
	329	clk->dev = dev;
	330	}
	331
73a59c1c SP	332	/* clocks are all static for now; no refcounting necessary */
	333	struct clk clk_get(struct device dev, const char *id)
	334	{
	335	int i;
	336
	337	for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
91f8ed83 AV	338	struct clk *clk = clock_list[i];
	339
	340	if (strcmp(id, clk->name) == 0)
	341	return clk;
	342	if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0)
	343	return clk;
73a59c1c SP	344	}
	345
	346	return ERR_PTR(-ENOENT);
	347	}
	348	EXPORT_SYMBOL(clk_get);
	349
	350	void clk_put(struct clk *clk)
	351	{
	352	}
	353	EXPORT_SYMBOL(clk_put);
	354
	355	static void __clk_enable(struct clk *clk)
	356	{
	357	if (clk->parent)
	358	__clk_enable(clk->parent);
	359	if (clk->users++ == 0 && clk->mode)
	360	clk->mode(clk, 1);
	361	}
	362
	363	int clk_enable(struct clk *clk)
	364	{
	365	unsigned long flags;
	366
	367	spin_lock_irqsave(&clk_lock, flags);
	368	__clk_enable(clk);
	369	spin_unlock_irqrestore(&clk_lock, flags);
	370	return 0;
	371	}
	372	EXPORT_SYMBOL(clk_enable);
	373
	374	static void __clk_disable(struct clk *clk)
	375	{
	376	BUG_ON(clk->users == 0);
	377	if (--clk->users == 0 && clk->mode)
	378	clk->mode(clk, 0);
	379	if (clk->parent)
	380	__clk_disable(clk->parent);
	381	}
	382
	383	void clk_disable(struct clk *clk)
	384	{
	385	unsigned long flags;
	386
	387	spin_lock_irqsave(&clk_lock, flags);
	388	__clk_disable(clk);
	389	spin_unlock_irqrestore(&clk_lock, flags);
	390	}
	391	EXPORT_SYMBOL(clk_disable);
	392
	393	unsigned long clk_get_rate(struct clk *clk)
	394	{
	395	unsigned long flags;
	396	unsigned long rate;
	397
	398	spin_lock_irqsave(&clk_lock, flags);
	399	for (;;) {
	400	rate = clk->rate_hz;
	401	if (rate \|\| !clk->parent)
	402	break;
	403	clk = clk->parent;
	404	}
	405	spin_unlock_irqrestore(&clk_lock, flags);
	406	return rate;
	407	}
408	EXPORT_SYMBOL(clk_get_rate);
409
410	/------------------------------------------------------------------------/
411
412	#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
413
414	/*
415	* For now, only the programmable clocks support reparenting (MCK could
416	* do this too, with care) or rate changing (the PLLs could do this too,
417	* ditto MCK but that's more for cpufreq). Drivers may reparent to get
418	* a better rate match; we don't.
419	*/
420
421	long clk_round_rate(struct clk *clk, unsigned long rate)
422	{
423	unsigned long flags;
424	unsigned prescale;
425	unsigned long actual;
426
427	if (!clk->programmable)
428	return -EINVAL;
429	spin_lock_irqsave(&clk_lock, flags);
430
431	actual = clk->parent->rate_hz;
432	for (prescale = 0; prescale < 7; prescale++) {
433	if (actual && actual <= rate)
434	break;
435	actual >>= 1;
436	}
437
438	spin_unlock_irqrestore(&clk_lock, flags);
439	return (prescale < 7) ? actual : -ENOENT;
440	}
441	EXPORT_SYMBOL(clk_round_rate);
442
443	int clk_set_rate(struct clk *clk, unsigned long rate)
444	{
445	unsigned long flags;
446	unsigned prescale;
447	unsigned long actual;
448
449	if (!clk->programmable)
450	return -EINVAL;
451	if (clk->users)
452	return -EBUSY;
453	spin_lock_irqsave(&clk_lock, flags);
454
455	actual = clk->parent->rate_hz;
456	for (prescale = 0; prescale < 7; prescale++) {
457	if (actual && actual <= rate) {
458	u32 pckr;
459
460	pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
69b648a2	461	pckr &= AT91_PMC_CSS_PLLB; /* clock selection */
73a59c1c SP	462	pckr \|= prescale << 2;
	463	at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
	464	clk->rate_hz = actual;
	465	break;
	466	}
	467	actual >>= 1;
	468	}
	469
	470	spin_unlock_irqrestore(&clk_lock, flags);
	471	return (prescale < 7) ? actual : -ENOENT;
	472	}
	473	EXPORT_SYMBOL(clk_set_rate);
	474
	475	struct clk clk_get_parent(struct clk clk)
	476	{
	477	return clk->parent;
	478	}
	479	EXPORT_SYMBOL(clk_get_parent);
	480
	481	int clk_set_parent(struct clk clk, struct clk parent)
	482	{
	483	unsigned long flags;
	484
	485	if (clk->users)
	486	return -EBUSY;
	487	if (!parent->primary \|\| !clk->programmable)
	488	return -EINVAL;
	489	spin_lock_irqsave(&clk_lock, flags);
	490
	491	clk->rate_hz = parent->rate_hz;
	492	clk->parent = parent;
	493	at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
	494
	495	spin_unlock_irqrestore(&clk_lock, flags);
	496	return 0;
	497	}
	498	EXPORT_SYMBOL(clk_set_parent);
	499
	500	#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
	501
	502	/------------------------------------------------------------------------/
	503
	504	#ifdef CONFIG_DEBUG_FS
	505
	506	static int at91_clk_show(struct seq_file s, void unused)
	507	{
	508	u32 scsr, pcsr, sr;
	509	unsigned i;
	510
	511	seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
	512	seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
	513
	514	seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR));
	515	seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
	516	seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
	517	seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
	518
	519	seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
	520	for (i = 0; i < 4; i++)
	521	seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i)));
	522	seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
	523
	524	seq_printf(s, "\n");
	525
526	for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
527	char *state;
528	struct clk *clk = clock_list[i];
529
530	if (clk->mode == pmc_sys_mode)
531	state = (scsr & clk->pmc_mask) ? "on" : "off";
532	else if (clk->mode == pmc_periph_mode)
533	state = (pcsr & clk->pmc_mask) ? "on" : "off";
534	else if (clk->pmc_mask)
535	state = (sr & clk->pmc_mask) ? "on" : "off";
536	else if (clk == &clk32k \|\| clk == &main_clk)
537	state = "on";
538	else
539	state = "";
540
69b648a2	541	seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
73a59c1c SP	542	clk->name, clk->users, state, clk_get_rate(clk),
	543	clk->parent ? clk->parent->name : "");
	544	}
	545	return 0;
	546	}
	547
	548	static int at91_clk_open(struct inode inode, struct file file)
	549	{
	550	return single_open(file, at91_clk_show, NULL);
	551	}
	552
	553	static struct file_operations at91_clk_operations = {
	554	.open = at91_clk_open,
	555	.read = seq_read,
	556	.llseek = seq_lseek,
	557	.release = single_release,
	558	};
	559
	560	static int __init at91_clk_debugfs_init(void)
	561	{
	562	/* /sys/kernel/debug/at91_clk */
	563	(void) debugfs_create_file("at91_clk", S_IFREG \| S_IRUGO, NULL, NULL, &at91_clk_operations);
	564
	565	return 0;
	566	}
	567	postcore_initcall(at91_clk_debugfs_init);
	568
	569	#endif
	570
	571	/------------------------------------------------------------------------/
	572
	573	static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
	574	{
	575	unsigned mul, div;
	576
	577	div = reg & 0xff;
	578	mul = (reg >> 16) & 0x7ff;
	579	if (div && mul) {
	580	freq /= div;
	581	freq *= mul + 1;
	582	} else
	583	freq = 0;
69b648a2	584
73a59c1c SP	585	return freq;
	586	}
	587
69b648a2 AV	588	static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
	589	{
	590	if (pll == &pllb && (reg & AT91_PMC_USB96M))
	591	return freq / 2;
	592	else
	593	return freq;
	594	}
	595
73a59c1c SP	596	static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
	597	{
	598	unsigned i, div = 0, mul = 0, diff = 1 << 30;
	599	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
	600
	601	/* PLL output max 240 MHz (or 180 MHz per errata) */
	602	if (out_freq > 240000000)
	603	goto fail;
	604
	605	for (i = 1; i < 256; i++) {
	606	int diff1;
	607	unsigned input, mul1;
	608
	609	/*
	610	* PLL input between 1MHz and 32MHz per spec, but lower
	611	* frequences seem necessary in some cases so allow 100K.
	612	*/
	613	input = main_freq / i;
	614	if (input < 100000)
	615	continue;
	616	if (input > 32000000)
	617	continue;
	618
	619	mul1 = out_freq / input;
	620	if (mul1 > 2048)
	621	continue;
	622	if (mul1 < 2)
	623	goto fail;
	624
	625	diff1 = out_freq - input * mul1;
	626	if (diff1 < 0)
	627	diff1 = -diff1;
	628	if (diff > diff1) {
	629	diff = diff1;
	630	div = i;
	631	mul = mul1;
	632	if (diff == 0)
	633	break;
	634	}
	635	}
	636	if (i == 256 && diff > (out_freq >> 5))
	637	goto fail;
	638	return ret \| ((mul - 1) << 16) \| div;
	639	fail:
	640	return 0;
	641	}
	642
91f8ed83 AV	643
	644	/*
	645	* Several unused clocks may be active. Turn them off.
	646	*/
	647	static void at91_periphclk_reset(void)
	648	{
	649	unsigned long reg;
	650	int i;
	651
	652	reg = at91_sys_read(AT91_PMC_PCSR);
	653
	654	for (i = 0; i < ARRAY_SIZE(clock_list); i++) {
	655	struct clk *clk = clock_list[i];
	656
	657	if (clk->mode != pmc_periph_mode)
	658	continue;
	659
	660	if (clk->users > 0)
	661	reg &= ~clk->pmc_mask;
	662	}
	663
	664	at91_sys_write(AT91_PMC_PCDR, reg);
	665	}
	666
73a59c1c SP	667	int __init at91_clock_init(unsigned long main_clock)
	668	{
	669	unsigned tmp, freq, mckr;
	670
	671	spin_lock_init(&clk_lock);
	672
	673	/*
	674	* When the bootloader initialized the main oscillator correctly,
	675	* there's no problem using the cycle counter. But if it didn't,
	676	* or when using oscillator bypass mode, we must be told the speed
	677	* of the main clock.
	678	*/
	679	if (!main_clock) {
	680	do {
	681	tmp = at91_sys_read(AT91_CKGR_MCFR);
69b648a2 AV	682	} while (!(tmp & AT91_PMC_MAINRDY));
69b648a2 AV	683	main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
73a59c1c SP	684	}
	685	main_clk.rate_hz = main_clock;
	686
	687	/* report if PLLA is more than mildly overclocked */
	688	plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
	689	if (plla.rate_hz > 209000000)
	690	pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
	691
	692	/*
	693	* USB clock init: choose 48 MHz PLLB value, turn all clocks off,
	694	* disable 48MHz clock during usb peripheral suspend.
	695	*
	696	* REVISIT: assumes MCK doesn't derive from PLLB!
	697	*/
69b648a2	698	at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) \| AT91_PMC_USB96M;
73a59c1c	699	pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
73a59c1c SP	700	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP \| AT91_PMC_UDP);
	701	at91_sys_write(AT91_CKGR_PLLBR, 0);
	702	at91_sys_write(AT91_PMC_SCER, AT91_PMC_MCKUDP);
	703
69b648a2 AV	704	udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
	705	uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
	706
73a59c1c SP	707	/*
	708	* MCK and CPU derive from one of those primary clocks.
	709	* For now, assume this parentage won't change.
	710	*/
	711	mckr = at91_sys_read(AT91_PMC_MCKR);
	712	mck.parent = clock_list[mckr & AT91_PMC_CSS];
73a59c1c SP	713	freq = mck.parent->rate_hz;
	714	freq /= (1 << ((mckr >> 2) & 3)); /* prescale */
	715	mck.rate_hz = freq / (1 + ((mckr >> 8) & 3)); /* mdiv */
	716
91f8ed83 AV	717	/* MCK and CPU clock are "always on" */
	718	clk_enable(&mck);
	719
73a59c1c SP	720	printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
	721	freq / 1000000, (unsigned) mck.rate_hz / 1000000,
	722	(unsigned) main_clock / 1000000,
	723	((unsigned) main_clock % 1000000) / 1000);
	724
73a59c1c SP	725	#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
	726	/* establish PCK0..PCK3 parentage */
	727	for (tmp = 0; tmp < ARRAY_SIZE(clock_list); tmp++) {
	728	struct clk clk = clock_list[tmp], parent;
	729	u32 pckr;
	730
	731	if (!clk->programmable)
	732	continue;
	733
	734	pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
91f8ed83	735	parent = clock_list[pckr & AT91_PMC_CSS];
73a59c1c SP	736	clk->parent = parent;
73a59c1c SP	737	clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3));
91f8ed83 AV	738
	739	if (clk->users == 0) {
	740	/* not being used, so switch it off */
	741	at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
	742	}
73a59c1c SP	743	}
73a59c1c SP	744	#else
91f8ed83	745	/* disable all programmable clocks */
73a59c1c	746	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 \| AT91_PMC_PCK1 \| AT91_PMC_PCK2 \| AT91_PMC_PCK3);
91f8ed83	747	#endif
73a59c1c	748
91f8ed83 AV	749	/* enable the PIO clocks */
	750	clk_enable(&pioA_clk);
	751	clk_enable(&pioB_clk);
	752	clk_enable(&pioC_clk);
	753	clk_enable(&pioD_clk);
	754
	755	/* disable all other unused peripheral clocks */
	756	at91_periphclk_reset();
73a59c1c SP	757
	758	return 0;
	759	}