[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-at91rm9200 / gpio.c

/*
 * linux/arch/arm/mach-at91rm9200/gpio.c
 *
 * Copyright (C) 2005 HP Labs
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/clk.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>

#include <asm/io.h>
#include <asm/hardware.h>
#include <asm/arch/gpio.h>

#include "generic.h"


static struct at91_gpio_bank *gpio;
static int gpio_banks;


static inline void __iomem *pin_to_controller(unsigned pin)
{
	void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS;

	pin -= PIN_BASE;
	pin /= 32;
	if (likely(pin < gpio_banks))
		return sys_base + gpio[pin].offset;

	return NULL;
}

static inline unsigned pin_to_mask(unsigned pin)
{
	pin -= PIN_BASE;
	return 1 << (pin % 32);
}


/*--------------------------------------------------------------------------*/

/* Not all hardware capabilities are exposed through these calls; they
 * only encapsulate the most common features and modes.  (So if you
 * want to change signals in groups, do it directly.)
 *
 * Bootloaders will usually handle some of the pin multiplexing setup.
 * The intent is certainly that by the time Linux is fully booted, all
 * pins should have been fully initialized.  These setup calls should
 * only be used by board setup routines, or possibly in driver probe().
 *
 * For bootloaders doing all that setup, these calls could be inlined
 * as NOPs so Linux won't duplicate any setup code
 */


/*
 * mux the pin to the "A" internal peripheral role.
 */
int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + PIO_IDR);
	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	__raw_writel(mask, pio + PIO_ASR);
	__raw_writel(mask, pio + PIO_PDR);
	return 0;
}
EXPORT_SYMBOL(at91_set_A_periph);


/*
 * mux the pin to the "B" internal peripheral role.
 */
int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + PIO_IDR);
	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	__raw_writel(mask, pio + PIO_BSR);
	__raw_writel(mask, pio + PIO_PDR);
	return 0;
}
EXPORT_SYMBOL(at91_set_B_periph);


/*
 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
 * configure it for an input.
 */
int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + PIO_IDR);
	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	__raw_writel(mask, pio + PIO_ODR);
	__raw_writel(mask, pio + PIO_PER);
	return 0;
}
EXPORT_SYMBOL(at91_set_gpio_input);


/*
 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
 * and configure it for an output.
 */
int __init_or_module at91_set_gpio_output(unsigned pin, int value)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + PIO_IDR);
	__raw_writel(mask, pio + PIO_PUDR);
	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
	__raw_writel(mask, pio + PIO_OER);
	__raw_writel(mask, pio + PIO_PER);
	return 0;
}
EXPORT_SYMBOL(at91_set_gpio_output);


/*
 * enable/disable the glitch filter; mostly used with IRQ handling.
 */
int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;
	__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
	return 0;
}
EXPORT_SYMBOL(at91_set_deglitch);

/*
 * enable/disable the multi-driver; This is only valid for output and
 * allows the output pin to run as an open collector output.
 */
int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
	return 0;
}
EXPORT_SYMBOL(at91_set_multi_drive);

/*--------------------------------------------------------------------------*/

/*
 * assuming the pin is muxed as a gpio output, set its value.
 */
int at91_set_gpio_value(unsigned pin, int value)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;
	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
	return 0;
}
EXPORT_SYMBOL(at91_set_gpio_value);


/*
 * read the pin's value (works even if it's not muxed as a gpio).
 */
int at91_get_gpio_value(unsigned pin)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);
	u32		pdsr;

	if (!pio)
		return -EINVAL;
	pdsr = __raw_readl(pio + PIO_PDSR);
	return (pdsr & mask) != 0;
}
EXPORT_SYMBOL(at91_get_gpio_value);

/*--------------------------------------------------------------------------*/

#ifdef CONFIG_PM

static u32 wakeups[MAX_GPIO_BANKS];
static u32 backups[MAX_GPIO_BANKS];

static int gpio_irq_set_wake(unsigned pin, unsigned state)
{
	unsigned	mask = pin_to_mask(pin);

	pin -= PIN_BASE;
	pin /= 32;

	if (unlikely(pin >= MAX_GPIO_BANKS))
		return -EINVAL;

	if (state)
		wakeups[pin] |= mask;
	else
		wakeups[pin] &= ~mask;

	return 0;
}

void at91_gpio_suspend(void)
{
	int i;

	for (i = 0; i < gpio_banks; i++) {
		u32 pio = gpio[i].offset;

		/*
		 * Note: drivers should have disabled GPIO interrupts that
		 * aren't supposed to be wakeup sources.
		 * But that is not much good on ARM.....  disable_irq() does
		 * not update the hardware immediately, so the hardware mask
		 * (IMR) has the wrong value (not current, too much is
		 * permitted).
		 *
		 * Our workaround is to disable all non-wakeup IRQs ...
		 * which is exactly what correct drivers asked for in the
		 * first place!
		 */
		backups[i] = at91_sys_read(pio + PIO_IMR);
		at91_sys_write(pio + PIO_IDR, backups[i]);
		at91_sys_write(pio + PIO_IER, wakeups[i]);

		if (!wakeups[i]) {
			disable_irq_wake(gpio[i].id);
			at91_sys_write(AT91_PMC_PCDR, 1 << gpio[i].id);
		} else {
			enable_irq_wake(gpio[i].id);
#ifdef CONFIG_PM_DEBUG
			printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", "ABCD"[i], wakeups[i]);
#endif
		}
	}
}

void at91_gpio_resume(void)
{
	int i;

	for (i = 0; i < gpio_banks; i++) {
		u32 pio = gpio[i].offset;

		at91_sys_write(pio + PIO_IDR, wakeups[i]);
		at91_sys_write(pio + PIO_IER, backups[i]);
		at91_sys_write(AT91_PMC_PCER, 1 << gpio[i].id);
	}
}

#else
#define gpio_irq_set_wake	NULL
#endif


/* Several AIC controller irqs are dispatched through this GPIO handler.
 * To use any AT91_PIN_* as an externally triggered IRQ, first call
 * at91_set_gpio_input() then maybe enable its glitch filter.
 * Then just request_irq() with the pin ID; it works like any ARM IRQ
 * handler, though it always triggers on rising and falling edges.
 *
 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
 * configuring them with at91_set_a_periph() or at91_set_b_periph().
 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
 */

static void gpio_irq_mask(unsigned pin)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (pio)
		__raw_writel(mask, pio + PIO_IDR);
}

static void gpio_irq_unmask(unsigned pin)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (pio)
		__raw_writel(mask, pio + PIO_IER);
}

static int gpio_irq_type(unsigned pin, unsigned type)
{
	return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL;
}

static struct irq_chip gpio_irqchip = {
	.name		= "GPIO",
	.mask		= gpio_irq_mask,
	.unmask		= gpio_irq_unmask,
	.set_type	= gpio_irq_type,
	.set_wake	= gpio_irq_set_wake,
};

static void gpio_irq_handler(unsigned irq, struct irqdesc *desc)
{
	unsigned	pin;
	struct irqdesc	*gpio;
	void __iomem	*pio;
	u32		isr;

	pio = get_irq_chip_data(irq);

	/* temporarily mask (level sensitive) parent IRQ */
	desc->chip->ack(irq);
	for (;;) {
		/* reading ISR acks the pending (edge triggered) GPIO interrupt */
		isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
		if (!isr)
			break;

		pin = (unsigned) get_irq_data(irq);
		gpio = &irq_desc[pin];

		while (isr) {
			if (isr & 1) {
				if (unlikely(gpio->depth)) {
					/*
					 * The core ARM interrupt handler lazily disables IRQs so
					 * another IRQ must be generated before it actually gets
					 * here to be disabled on the GPIO controller.
					 */
					gpio_irq_mask(pin);
				}
				else
					desc_handle_irq(pin, gpio);
			}
			pin++;
			gpio++;
			isr >>= 1;
		}
	}
	desc->chip->unmask(irq);
	/* now it may re-trigger */
}

/*--------------------------------------------------------------------------*/

/*
 * Called from the processor-specific init to enable GPIO interrupt support.
 */
void __init at91_gpio_irq_setup(void)
{
	unsigned	pioc, pin;

	for (pioc = 0, pin = PIN_BASE;
			pioc < gpio_banks;
			pioc++) {
		void __iomem	*controller;
		unsigned	id = gpio[pioc].id;
		unsigned	i;

		clk_enable(gpio[pioc].clock);	/* enable PIO controller's clock */

		controller = (void __iomem *) AT91_VA_BASE_SYS + gpio[pioc].offset;
		__raw_writel(~0, controller + PIO_IDR);

		set_irq_data(id, (void *) pin);
		set_irq_chipdata(id, controller);

		for (i = 0; i < 32; i++, pin++) {
			/*
			 * Can use the "simple" and not "edge" handler since it's
			 * shorter, and the AIC handles interupts sanely.
			 */
			set_irq_chip(pin, &gpio_irqchip);
			set_irq_handler(pin, do_simple_IRQ);
			set_irq_flags(pin, IRQF_VALID);
		}

		set_irq_chained_handler(id, gpio_irq_handler);
	}
	pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
}

/*
 * Called from the processor-specific init to enable GPIO pin support.
 */
void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
{
	BUG_ON(nr_banks > MAX_GPIO_BANKS);

	gpio = data;
	gpio_banks = nr_banks;
}
Commit	Line	Data
73a59c1c SP	1	/*
	2	* linux/arch/arm/mach-at91rm9200/gpio.c
	3	*
	4	* Copyright (C) 2005 HP Labs
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
f2173834	12	#include <linux/clk.h>
73a59c1c	13	#include <linux/errno.h>
07d265dd TG	14	#include <linux/interrupt.h>
07d265dd TG	15	#include <linux/irq.h>
73a59c1c SP	16	#include <linux/kernel.h>
	17	#include <linux/list.h>
	18	#include <linux/module.h>
	19
	20	#include <asm/io.h>
ea75ee9a	21	#include <asm/hardware.h>
73a59c1c SP	22	#include <asm/arch/gpio.h>
73a59c1c SP	23
f2173834 AV	24	#include "generic.h"
	25
	26
	27	static struct at91_gpio_bank *gpio;
	28	static int gpio_banks;
	29
73a59c1c SP	30
	31	static inline void __iomem *pin_to_controller(unsigned pin)
	32	{
	33	void __iomem sys_base = (void __iomem ) AT91_VA_BASE_SYS;
	34
	35	pin -= PIN_BASE;
	36	pin /= 32;
f2173834 AV	37	if (likely(pin < gpio_banks))
f2173834 AV	38	return sys_base + gpio[pin].offset;
73a59c1c SP	39
	40	return NULL;
	41	}
	42
	43	static inline unsigned pin_to_mask(unsigned pin)
	44	{
	45	pin -= PIN_BASE;
	46	return 1 << (pin % 32);
	47	}
	48
	49
	50	/--------------------------------------------------------------------------/
	51
	52	/* Not all hardware capabilities are exposed through these calls; they
	53	* only encapsulate the most common features and modes. (So if you
	54	* want to change signals in groups, do it directly.)
	55	*
	56	* Bootloaders will usually handle some of the pin multiplexing setup.
	57	* The intent is certainly that by the time Linux is fully booted, all
	58	* pins should have been fully initialized. These setup calls should
	59	* only be used by board setup routines, or possibly in driver probe().
	60	*
	61	* For bootloaders doing all that setup, these calls could be inlined
	62	* as NOPs so Linux won't duplicate any setup code
	63	*/
	64
	65
	66	/*
	67	* mux the pin to the "A" internal peripheral role.
	68	*/
	69	int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
	70	{
	71	void __iomem *pio = pin_to_controller(pin);
	72	unsigned mask = pin_to_mask(pin);
	73
	74	if (!pio)
	75	return -EINVAL;
	76
	77	__raw_writel(mask, pio + PIO_IDR);
	78	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	79	__raw_writel(mask, pio + PIO_ASR);
	80	__raw_writel(mask, pio + PIO_PDR);
	81	return 0;
	82	}
	83	EXPORT_SYMBOL(at91_set_A_periph);
	84
	85
	86	/*
	87	* mux the pin to the "B" internal peripheral role.
	88	*/
	89	int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
	90	{
	91	void __iomem *pio = pin_to_controller(pin);
	92	unsigned mask = pin_to_mask(pin);
	93
	94	if (!pio)
	95	return -EINVAL;
	96
	97	__raw_writel(mask, pio + PIO_IDR);
	98	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	99	__raw_writel(mask, pio + PIO_BSR);
	100	__raw_writel(mask, pio + PIO_PDR);
	101	return 0;
	102	}
103	EXPORT_SYMBOL(at91_set_B_periph);
104
105
106	/*
107	* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
108	* configure it for an input.
109	*/
110	int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
111	{
112	void __iomem *pio = pin_to_controller(pin);
113	unsigned mask = pin_to_mask(pin);
114
115	if (!pio)
116	return -EINVAL;
117
118	__raw_writel(mask, pio + PIO_IDR);
119	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
120	__raw_writel(mask, pio + PIO_ODR);
121	__raw_writel(mask, pio + PIO_PER);
122	return 0;
123	}
124	EXPORT_SYMBOL(at91_set_gpio_input);
125
126
127	/*
128	* mux the pin to the gpio controller (instead of "A" or "B" peripheral),
129	* and configure it for an output.
130	*/
131	int __init_or_module at91_set_gpio_output(unsigned pin, int value)
132	{
133	void __iomem *pio = pin_to_controller(pin);
134	unsigned mask = pin_to_mask(pin);
135
136	if (!pio)
137	return -EINVAL;
138
139	__raw_writel(mask, pio + PIO_IDR);
140	__raw_writel(mask, pio + PIO_PUDR);
141	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
142	__raw_writel(mask, pio + PIO_OER);
143	__raw_writel(mask, pio + PIO_PER);
144	return 0;
145	}
146	EXPORT_SYMBOL(at91_set_gpio_output);
147
148
149	/*
150	* enable/disable the glitch filter; mostly used with IRQ handling.
151	*/
152	int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
153	{
154	void __iomem *pio = pin_to_controller(pin);
155	unsigned mask = pin_to_mask(pin);
156
157	if (!pio)
158	return -EINVAL;
159	__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
160	return 0;
161	}
162	EXPORT_SYMBOL(at91_set_deglitch);
163
df666b9c AV	164	/*
	165	* enable/disable the multi-driver; This is only valid for output and
	166	* allows the output pin to run as an open collector output.
	167	*/
	168	int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
	169	{
	170	void __iomem *pio = pin_to_controller(pin);
	171	unsigned mask = pin_to_mask(pin);
	172
	173	if (!pio)
	174	return -EINVAL;
	175
	176	__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
	177	return 0;
	178	}
	179	EXPORT_SYMBOL(at91_set_multi_drive);
	180
73a59c1c SP	181	/--------------------------------------------------------------------------/
73a59c1c SP	182
73a59c1c SP	183	/*
	184	* assuming the pin is muxed as a gpio output, set its value.
	185	*/
	186	int at91_set_gpio_value(unsigned pin, int value)
	187	{
	188	void __iomem *pio = pin_to_controller(pin);
	189	unsigned mask = pin_to_mask(pin);
	190
	191	if (!pio)
	192	return -EINVAL;
	193	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
	194	return 0;
	195	}
	196	EXPORT_SYMBOL(at91_set_gpio_value);
	197
	198
	199	/*
	200	* read the pin's value (works even if it's not muxed as a gpio).
	201	*/
	202	int at91_get_gpio_value(unsigned pin)
	203	{
	204	void __iomem *pio = pin_to_controller(pin);
	205	unsigned mask = pin_to_mask(pin);
	206	u32 pdsr;
	207
	208	if (!pio)
	209	return -EINVAL;
	210	pdsr = __raw_readl(pio + PIO_PDSR);
	211	return (pdsr & mask) != 0;
	212	}
	213	EXPORT_SYMBOL(at91_get_gpio_value);
	214
	215	/--------------------------------------------------------------------------/
	216
814138ff AV	217	#ifdef CONFIG_PM
814138ff AV	218
f2173834 AV	219	static u32 wakeups[MAX_GPIO_BANKS];
f2173834 AV	220	static u32 backups[MAX_GPIO_BANKS];
814138ff AV	221
	222	static int gpio_irq_set_wake(unsigned pin, unsigned state)
	223	{
	224	unsigned mask = pin_to_mask(pin);
	225
	226	pin -= PIN_BASE;
	227	pin /= 32;
	228
f2173834	229	if (unlikely(pin >= MAX_GPIO_BANKS))
814138ff AV	230	return -EINVAL;
	231
	232	if (state)
	233	wakeups[pin] \|= mask;
	234	else
	235	wakeups[pin] &= ~mask;
	236
	237	return 0;
	238	}
	239
	240	void at91_gpio_suspend(void)
	241	{
	242	int i;
	243
f2173834 AV	244	for (i = 0; i < gpio_banks; i++) {
f2173834 AV	245	u32 pio = gpio[i].offset;
814138ff AV	246
	247	/*
	248	* Note: drivers should have disabled GPIO interrupts that
	249	* aren't supposed to be wakeup sources.
	250	* But that is not much good on ARM..... disable_irq() does
	251	* not update the hardware immediately, so the hardware mask
	252	* (IMR) has the wrong value (not current, too much is
	253	* permitted).
	254	*
	255	* Our workaround is to disable all non-wakeup IRQs ...
	256	* which is exactly what correct drivers asked for in the
	257	* first place!
	258	*/
	259	backups[i] = at91_sys_read(pio + PIO_IMR);
f2173834 AV	260	at91_sys_write(pio + PIO_IDR, backups[i]);
f2173834 AV	261	at91_sys_write(pio + PIO_IER, wakeups[i]);
814138ff AV	262
814138ff AV	263	if (!wakeups[i]) {
f2173834 AV	264	disable_irq_wake(gpio[i].id);
f2173834 AV	265	at91_sys_write(AT91_PMC_PCDR, 1 << gpio[i].id);
814138ff	266	} else {
f2173834	267	enable_irq_wake(gpio[i].id);
814138ff AV	268	#ifdef CONFIG_PM_DEBUG
	269	printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", "ABCD"[i], wakeups[i]);
	270	#endif
	271	}
	272	}
	273	}
	274
	275	void at91_gpio_resume(void)
	276	{
	277	int i;
	278
f2173834 AV	279	for (i = 0; i < gpio_banks; i++) {
f2173834 AV	280	u32 pio = gpio[i].offset;
814138ff	281
f2173834 AV	282	at91_sys_write(pio + PIO_IDR, wakeups[i]);
	283	at91_sys_write(pio + PIO_IER, backups[i]);
	284	at91_sys_write(AT91_PMC_PCER, 1 << gpio[i].id);
	285	}
814138ff AV	286	}
	287
	288	#else
	289	#define gpio_irq_set_wake NULL
	290	#endif
	291
73a59c1c SP	292
	293	/* Several AIC controller irqs are dispatched through this GPIO handler.
	294	* To use any AT91_PIN_* as an externally triggered IRQ, first call
	295	* at91_set_gpio_input() then maybe enable its glitch filter.
	296	* Then just request_irq() with the pin ID; it works like any ARM IRQ
	297	* handler, though it always triggers on rising and falling edges.
	298	*
	299	* Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
	300	* configuring them with at91_set_a_periph() or at91_set_b_periph().
	301	* IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
	302	*/
	303
	304	static void gpio_irq_mask(unsigned pin)
	305	{
	306	void __iomem *pio = pin_to_controller(pin);
	307	unsigned mask = pin_to_mask(pin);
	308
	309	if (pio)
	310	__raw_writel(mask, pio + PIO_IDR);
	311	}
	312
	313	static void gpio_irq_unmask(unsigned pin)
	314	{
	315	void __iomem *pio = pin_to_controller(pin);
	316	unsigned mask = pin_to_mask(pin);
	317
	318	if (pio)
	319	__raw_writel(mask, pio + PIO_IER);
	320	}
	321
	322	static int gpio_irq_type(unsigned pin, unsigned type)
	323	{
	324	return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL;
	325	}
	326
38c677cb DB	327	static struct irq_chip gpio_irqchip = {
38c677cb DB	328	.name = "GPIO",
73a59c1c SP	329	.mask = gpio_irq_mask,
	330	.unmask = gpio_irq_unmask,
	331	.set_type = gpio_irq_type,
814138ff	332	.set_wake = gpio_irq_set_wake,
73a59c1c SP	333	};
73a59c1c SP	334
0cd61b68	335	static void gpio_irq_handler(unsigned irq, struct irqdesc *desc)
73a59c1c SP	336	{
	337	unsigned pin;
	338	struct irqdesc *gpio;
	339	void __iomem *pio;
	340	u32 isr;
	341
07d265dd	342	pio = get_irq_chip_data(irq);
73a59c1c SP	343
	344	/* temporarily mask (level sensitive) parent IRQ */
	345	desc->chip->ack(irq);
	346	for (;;) {
814138ff	347	/* reading ISR acks the pending (edge triggered) GPIO interrupt */
73a59c1c SP	348	isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
	349	if (!isr)
	350	break;
	351
07d265dd	352	pin = (unsigned) get_irq_data(irq);
73a59c1c SP	353	gpio = &irq_desc[pin];
	354
	355	while (isr) {
abbea718	356	if (isr & 1) {
07d265dd	357	if (unlikely(gpio->depth)) {
abbea718 AV	358	/*
	359	* The core ARM interrupt handler lazily disables IRQs so
	360	* another IRQ must be generated before it actually gets
	361	* here to be disabled on the GPIO controller.
	362	*/
	363	gpio_irq_mask(pin);
	364	}
	365	else
0cd61b68	366	desc_handle_irq(pin, gpio);
abbea718	367	}
73a59c1c SP	368	pin++;
	369	gpio++;
	370	isr >>= 1;
	371	}
	372	}
	373	desc->chip->unmask(irq);
	374	/* now it may re-trigger */
	375	}
	376
f2173834 AV	377	/--------------------------------------------------------------------------/
	378
	379	/*
	380	* Called from the processor-specific init to enable GPIO interrupt support.
	381	*/
	382	void __init at91_gpio_irq_setup(void)
73a59c1c	383	{
f2173834	384	unsigned pioc, pin;
73a59c1c	385
f2173834 AV	386	for (pioc = 0, pin = PIN_BASE;
	387	pioc < gpio_banks;
	388	pioc++) {
73a59c1c	389	void __iomem *controller;
f2173834	390	unsigned id = gpio[pioc].id;
73a59c1c SP	391	unsigned i;
73a59c1c SP	392
f2173834 AV	393	clk_enable(gpio[pioc].clock); /* enable PIO controller's clock */
	394
	395	controller = (void __iomem *) AT91_VA_BASE_SYS + gpio[pioc].offset;
73a59c1c SP	396	__raw_writel(~0, controller + PIO_IDR);
	397
	398	set_irq_data(id, (void *) pin);
54815366	399	set_irq_chipdata(id, controller);
73a59c1c SP	400
73a59c1c SP	401	for (i = 0; i < 32; i++, pin++) {
814138ff AV	402	/*
	403	* Can use the "simple" and not "edge" handler since it's
	404	* shorter, and the AIC handles interupts sanely.
	405	*/
73a59c1c SP	406	set_irq_chip(pin, &gpio_irqchip);
	407	set_irq_handler(pin, do_simple_IRQ);
	408	set_irq_flags(pin, IRQF_VALID);
	409	}
	410
	411	set_irq_chained_handler(id, gpio_irq_handler);
73a59c1c	412	}
f2173834 AV	413	pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
	414	}
	415
	416	/*
	417	* Called from the processor-specific init to enable GPIO pin support.
	418	*/
	419	void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
	420	{
	421	BUG_ON(nr_banks > MAX_GPIO_BANKS);
	422
	423	gpio = data;
	424	gpio_banks = nr_banks;
73a59c1c	425	}