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73a59c1c SP |
1 | /* |
2 | * linux/arch/arm/mach-at91rm9200/irq.c | |
3 | * | |
4 | * Copyright (C) 2004 SAN People | |
5 | * Copyright (C) 2004 ATMEL | |
6 | * Copyright (C) Rick Bronson | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
73a59c1c SP |
23 | #include <linux/init.h> |
24 | #include <linux/module.h> | |
25 | #include <linux/mm.h> | |
26 | #include <linux/types.h> | |
27 | ||
28 | #include <asm/hardware.h> | |
29 | #include <asm/irq.h> | |
30 | #include <asm/mach-types.h> | |
31 | #include <asm/setup.h> | |
32 | ||
33 | #include <asm/mach/arch.h> | |
34 | #include <asm/mach/irq.h> | |
35 | #include <asm/mach/map.h> | |
36 | ||
37 | #include "generic.h" | |
38 | ||
73a59c1c | 39 | |
ba854e18 | 40 | static void at91_aic_mask_irq(unsigned int irq) |
73a59c1c SP |
41 | { |
42 | /* Disable interrupt on AIC */ | |
43 | at91_sys_write(AT91_AIC_IDCR, 1 << irq); | |
44 | } | |
45 | ||
ba854e18 | 46 | static void at91_aic_unmask_irq(unsigned int irq) |
73a59c1c SP |
47 | { |
48 | /* Enable interrupt on AIC */ | |
49 | at91_sys_write(AT91_AIC_IECR, 1 << irq); | |
50 | } | |
51 | ||
ba854e18 | 52 | static int at91_aic_set_type(unsigned irq, unsigned type) |
73a59c1c SP |
53 | { |
54 | unsigned int smr, srctype; | |
55 | ||
73a59c1c SP |
56 | switch (type) { |
57 | case IRQT_HIGH: | |
58 | srctype = AT91_AIC_SRCTYPE_HIGH; | |
59 | break; | |
60 | case IRQT_RISING: | |
61 | srctype = AT91_AIC_SRCTYPE_RISING; | |
62 | break; | |
63 | case IRQT_LOW: | |
37f2e4bc AV |
64 | if ((irq > AT91_ID_FIQ) && (irq < AT91_ID_IRQ0)) /* only supported on external interrupts */ |
65 | return -EINVAL; | |
73a59c1c SP |
66 | srctype = AT91_AIC_SRCTYPE_LOW; |
67 | break; | |
68 | case IRQT_FALLING: | |
37f2e4bc AV |
69 | if ((irq > AT91_ID_FIQ) && (irq < AT91_ID_IRQ0)) /* only supported on external interrupts */ |
70 | return -EINVAL; | |
73a59c1c SP |
71 | srctype = AT91_AIC_SRCTYPE_FALLING; |
72 | break; | |
73 | default: | |
74 | return -EINVAL; | |
75 | } | |
76 | ||
77 | smr = at91_sys_read(AT91_AIC_SMR(irq)) & ~AT91_AIC_SRCTYPE; | |
78 | at91_sys_write(AT91_AIC_SMR(irq), smr | srctype); | |
79 | return 0; | |
80 | } | |
81 | ||
683c66bf AV |
82 | #ifdef CONFIG_PM |
83 | ||
84 | static u32 wakeups; | |
85 | static u32 backups; | |
86 | ||
ba854e18 | 87 | static int at91_aic_set_wake(unsigned irq, unsigned value) |
683c66bf AV |
88 | { |
89 | if (unlikely(irq >= 32)) | |
90 | return -EINVAL; | |
91 | ||
92 | if (value) | |
93 | wakeups |= (1 << irq); | |
94 | else | |
95 | wakeups &= ~(1 << irq); | |
96 | ||
97 | return 0; | |
98 | } | |
99 | ||
100 | void at91_irq_suspend(void) | |
101 | { | |
102 | backups = at91_sys_read(AT91_AIC_IMR); | |
103 | at91_sys_write(AT91_AIC_IDCR, backups); | |
104 | at91_sys_write(AT91_AIC_IECR, wakeups); | |
105 | } | |
106 | ||
107 | void at91_irq_resume(void) | |
108 | { | |
109 | at91_sys_write(AT91_AIC_IDCR, wakeups); | |
110 | at91_sys_write(AT91_AIC_IECR, backups); | |
111 | } | |
112 | ||
113 | #else | |
ba854e18 | 114 | #define at91_aic_set_wake NULL |
683c66bf AV |
115 | #endif |
116 | ||
ba854e18 AV |
117 | static struct irqchip at91_aic_chip = { |
118 | .ack = at91_aic_mask_irq, | |
119 | .mask = at91_aic_mask_irq, | |
120 | .unmask = at91_aic_unmask_irq, | |
121 | .set_type = at91_aic_set_type, | |
122 | .set_wake = at91_aic_set_wake, | |
73a59c1c SP |
123 | }; |
124 | ||
125 | /* | |
126 | * Initialize the AIC interrupt controller. | |
127 | */ | |
ba854e18 | 128 | void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) |
73a59c1c SP |
129 | { |
130 | unsigned int i; | |
131 | ||
73a59c1c SP |
132 | /* |
133 | * The IVR is used by macro get_irqnr_and_base to read and verify. | |
134 | * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred. | |
135 | */ | |
136 | for (i = 0; i < NR_AIC_IRQS; i++) { | |
137 | /* Put irq number in Source Vector Register: */ | |
138 | at91_sys_write(AT91_AIC_SVR(i), i); | |
ba854e18 | 139 | /* Active Low interrupt, with the specified priority */ |
73a59c1c SP |
140 | at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); |
141 | ||
ba854e18 | 142 | set_irq_chip(i, &at91_aic_chip); |
73a59c1c SP |
143 | set_irq_handler(i, do_level_IRQ); |
144 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | |
145 | ||
146 | /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ | |
147 | if (i < 8) | |
148 | at91_sys_write(AT91_AIC_EOICR, 0); | |
149 | } | |
150 | ||
151 | /* | |
152 | * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS | |
153 | * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU | |
154 | */ | |
155 | at91_sys_write(AT91_AIC_SPU, NR_AIC_IRQS); | |
156 | ||
157 | /* No debugging in AIC: Debug (Protect) Control Register */ | |
158 | at91_sys_write(AT91_AIC_DCR, 0); | |
159 | ||
160 | /* Disable and clear all interrupts initially */ | |
161 | at91_sys_write(AT91_AIC_IDCR, 0xFFFFFFFF); | |
162 | at91_sys_write(AT91_AIC_ICCR, 0xFFFFFFFF); | |
163 | } |