]>
Commit | Line | Data |
---|---|---|
e94cdef0 AV |
1 | /* |
2 | * Cavium Networks CNS3420 Validation Board | |
3 | * | |
4 | * Copyright 2000 Deep Blue Solutions Ltd | |
5 | * Copyright 2008 ARM Limited | |
6 | * Copyright 2008 Cavium Networks | |
7 | * Scott Shu | |
8 | * Copyright 2010 MontaVista Software, LLC. | |
9 | * Anton Vorontsov <avorontsov@mvista.com> | |
10 | * | |
11 | * This file is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License, Version 2, as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/compiler.h> | |
19 | #include <linux/io.h> | |
cf36797f | 20 | #include <linux/dma-mapping.h> |
e94cdef0 AV |
21 | #include <linux/serial_core.h> |
22 | #include <linux/serial_8250.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/mtd/mtd.h> | |
25 | #include <linux/mtd/physmap.h> | |
26 | #include <linux/mtd/partitions.h> | |
b898f5fa | 27 | #include <linux/usb/ehci_pdriver.h> |
6da00dd7 | 28 | #include <linux/usb/ohci_pdriver.h> |
e94cdef0 AV |
29 | #include <asm/setup.h> |
30 | #include <asm/mach-types.h> | |
ead31ee5 | 31 | #include <asm/hardware/gic.h> |
e94cdef0 AV |
32 | #include <asm/mach/arch.h> |
33 | #include <asm/mach/map.h> | |
34 | #include <asm/mach/time.h> | |
e94cdef0 AV |
35 | #include <mach/cns3xxx.h> |
36 | #include <mach/irqs.h> | |
b898f5fa | 37 | #include <mach/pm.h> |
e94cdef0 | 38 | #include "core.h" |
6279d0ea | 39 | #include "devices.h" |
e94cdef0 AV |
40 | |
41 | /* | |
42 | * NOR Flash | |
43 | */ | |
44 | static struct mtd_partition cns3420_nor_partitions[] = { | |
45 | { | |
46 | .name = "uboot", | |
47 | .size = 0x00040000, | |
48 | .offset = 0, | |
49 | .mask_flags = MTD_WRITEABLE, | |
50 | }, { | |
51 | .name = "kernel", | |
52 | .size = 0x004C0000, | |
53 | .offset = MTDPART_OFS_APPEND, | |
54 | }, { | |
55 | .name = "filesystem", | |
56 | .size = 0x7000000, | |
57 | .offset = MTDPART_OFS_APPEND, | |
58 | }, { | |
59 | .name = "filesystem2", | |
60 | .size = 0x0AE0000, | |
61 | .offset = MTDPART_OFS_APPEND, | |
62 | }, { | |
63 | .name = "ubootenv", | |
64 | .size = MTDPART_SIZ_FULL, | |
65 | .offset = MTDPART_OFS_APPEND, | |
66 | }, | |
67 | }; | |
68 | ||
69 | static struct physmap_flash_data cns3420_nor_pdata = { | |
70 | .width = 2, | |
71 | .parts = cns3420_nor_partitions, | |
72 | .nr_parts = ARRAY_SIZE(cns3420_nor_partitions), | |
73 | }; | |
74 | ||
75 | static struct resource cns3420_nor_res = { | |
76 | .start = CNS3XXX_FLASH_BASE, | |
77 | .end = CNS3XXX_FLASH_BASE + SZ_128M - 1, | |
78 | .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, | |
79 | }; | |
80 | ||
81 | static struct platform_device cns3420_nor_pdev = { | |
82 | .name = "physmap-flash", | |
83 | .id = 0, | |
84 | .resource = &cns3420_nor_res, | |
85 | .num_resources = 1, | |
86 | .dev = { | |
87 | .platform_data = &cns3420_nor_pdata, | |
88 | }, | |
89 | }; | |
90 | ||
91 | /* | |
92 | * UART | |
93 | */ | |
94 | static void __init cns3420_early_serial_setup(void) | |
95 | { | |
96 | #ifdef CONFIG_SERIAL_8250_CONSOLE | |
97 | static struct uart_port cns3420_serial_port = { | |
98 | .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT, | |
99 | .mapbase = CNS3XXX_UART0_BASE, | |
100 | .irq = IRQ_CNS3XXX_UART0, | |
101 | .iotype = UPIO_MEM, | |
102 | .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, | |
103 | .regshift = 2, | |
104 | .uartclk = 24000000, | |
105 | .line = 0, | |
106 | .type = PORT_16550A, | |
107 | .fifosize = 16, | |
108 | }; | |
109 | ||
110 | early_serial_setup(&cns3420_serial_port); | |
111 | #endif | |
112 | } | |
113 | ||
cf36797f ML |
114 | /* |
115 | * USB | |
116 | */ | |
117 | static struct resource cns3xxx_usb_ehci_resources[] = { | |
118 | [0] = { | |
119 | .start = CNS3XXX_USB_BASE, | |
120 | .end = CNS3XXX_USB_BASE + SZ_16M - 1, | |
121 | .flags = IORESOURCE_MEM, | |
122 | }, | |
123 | [1] = { | |
124 | .start = IRQ_CNS3XXX_USB_EHCI, | |
125 | .flags = IORESOURCE_IRQ, | |
126 | }, | |
127 | }; | |
128 | ||
129 | static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32); | |
130 | ||
6da00dd7 | 131 | static int csn3xxx_usb_power_on(struct platform_device *pdev) |
b898f5fa FF |
132 | { |
133 | /* | |
134 | * EHCI and OHCI share the same clock and power, | |
135 | * resetting twice would cause the 1st controller been reset. | |
136 | * Therefore only do power up at the first up device, and | |
137 | * power down at the last down device. | |
138 | * | |
139 | * Set USB AHB INCR length to 16 | |
140 | */ | |
141 | if (atomic_inc_return(&usb_pwr_ref) == 1) { | |
142 | cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); | |
143 | cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); | |
144 | cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); | |
145 | __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), | |
146 | MISC_CHIP_CONFIG_REG); | |
147 | } | |
148 | ||
149 | return 0; | |
150 | } | |
151 | ||
6da00dd7 | 152 | static void csn3xxx_usb_power_off(struct platform_device *pdev) |
b898f5fa FF |
153 | { |
154 | /* | |
155 | * EHCI and OHCI share the same clock and power, | |
156 | * resetting twice would cause the 1st controller been reset. | |
157 | * Therefore only do power up at the first up device, and | |
158 | * power down at the last down device. | |
159 | */ | |
160 | if (atomic_dec_return(&usb_pwr_ref) == 0) | |
161 | cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); | |
162 | } | |
163 | ||
164 | static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = { | |
6da00dd7 FF |
165 | .power_on = csn3xxx_usb_power_on, |
166 | .power_off = csn3xxx_usb_power_off, | |
b898f5fa FF |
167 | }; |
168 | ||
cf36797f | 169 | static struct platform_device cns3xxx_usb_ehci_device = { |
b898f5fa | 170 | .name = "ehci-platform", |
cf36797f ML |
171 | .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources), |
172 | .resource = cns3xxx_usb_ehci_resources, | |
173 | .dev = { | |
174 | .dma_mask = &cns3xxx_usb_ehci_dma_mask, | |
175 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
b898f5fa | 176 | .platform_data = &cns3xxx_usb_ehci_pdata, |
cf36797f ML |
177 | }, |
178 | }; | |
179 | ||
180 | static struct resource cns3xxx_usb_ohci_resources[] = { | |
181 | [0] = { | |
182 | .start = CNS3XXX_USB_OHCI_BASE, | |
183 | .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1, | |
184 | .flags = IORESOURCE_MEM, | |
185 | }, | |
186 | [1] = { | |
187 | .start = IRQ_CNS3XXX_USB_OHCI, | |
188 | .flags = IORESOURCE_IRQ, | |
189 | }, | |
190 | }; | |
191 | ||
192 | static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32); | |
193 | ||
6da00dd7 FF |
194 | static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = { |
195 | .num_ports = 1, | |
196 | .power_on = csn3xxx_usb_power_on, | |
197 | .power_off = csn3xxx_usb_power_off, | |
198 | }; | |
199 | ||
cf36797f | 200 | static struct platform_device cns3xxx_usb_ohci_device = { |
6da00dd7 | 201 | .name = "ohci-platform", |
cf36797f ML |
202 | .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources), |
203 | .resource = cns3xxx_usb_ohci_resources, | |
204 | .dev = { | |
205 | .dma_mask = &cns3xxx_usb_ohci_dma_mask, | |
206 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
6da00dd7 | 207 | .platform_data = &cns3xxx_usb_ohci_pdata, |
cf36797f ML |
208 | }, |
209 | }; | |
210 | ||
e94cdef0 AV |
211 | /* |
212 | * Initialization | |
213 | */ | |
214 | static struct platform_device *cns3420_pdevs[] __initdata = { | |
215 | &cns3420_nor_pdev, | |
cf36797f ML |
216 | &cns3xxx_usb_ehci_device, |
217 | &cns3xxx_usb_ohci_device, | |
e94cdef0 AV |
218 | }; |
219 | ||
220 | static void __init cns3420_init(void) | |
221 | { | |
93e85d8e AV |
222 | cns3xxx_l2x0_init(); |
223 | ||
e94cdef0 AV |
224 | platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); |
225 | ||
23f5cace | 226 | cns3xxx_ahci_init(); |
6279d0ea AV |
227 | cns3xxx_sdhci_init(); |
228 | ||
e94cdef0 AV |
229 | pm_power_off = cns3xxx_power_off; |
230 | } | |
231 | ||
232 | static struct map_desc cns3420_io_desc[] __initdata = { | |
233 | { | |
234 | .virtual = CNS3XXX_UART0_BASE_VIRT, | |
235 | .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE), | |
236 | .length = SZ_4K, | |
237 | .type = MT_DEVICE, | |
238 | }, | |
239 | }; | |
240 | ||
241 | static void __init cns3420_map_io(void) | |
242 | { | |
243 | cns3xxx_map_io(); | |
244 | iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc)); | |
245 | ||
246 | cns3420_early_serial_setup(); | |
247 | } | |
248 | ||
249 | MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") | |
03e67202 | 250 | .atag_offset = 0x100, |
e94cdef0 AV |
251 | .map_io = cns3420_map_io, |
252 | .init_irq = cns3xxx_init_irq, | |
6bb27d73 | 253 | .init_time = cns3xxx_timer_init, |
ead31ee5 | 254 | .handle_irq = gic_handle_irq, |
e94cdef0 | 255 | .init_machine = cns3420_init, |
39214705 | 256 | .restart = cns3xxx_restart, |
e94cdef0 | 257 | MACHINE_END |