[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-davinci / board-mityomapl138.c

/*
 * Critical Link MityOMAP-L138 SoM
 *
 * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of
 * any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/platform_device.h>
#include <linux/mtd/partitions.h>
#include <linux/regulator/machine.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/etherdevice.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/cp_intc.h>
#include <mach/da8xx.h>
#include <mach/nand.h>
#include <mach/mux.h>

#define MITYOMAPL138_PHY_ID		"0:03"

#define FACTORY_CONFIG_MAGIC	0x012C0138
#define FACTORY_CONFIG_VERSION	0x00010001

/* Data Held in On-Board I2C device */
struct factory_config {
	u32	magic;
	u32	version;
	u8	mac[6];
	u32	fpga_type;
	u32	spare;
	u32	serialnumber;
	char	partnum[32];
};

static struct factory_config factory_config;

struct part_no_info {
	const char	*part_no;	/* part number string of interest */
	int		max_freq;	/* khz */
};

static struct part_no_info mityomapl138_pn_info[] = {
	{
		.part_no	= "L138-C",
		.max_freq	= 300000,
	},
	{
		.part_no	= "L138-D",
		.max_freq	= 375000,
	},
	{
		.part_no	= "L138-F",
		.max_freq	= 456000,
	},
	{
		.part_no	= "1808-C",
		.max_freq	= 300000,
	},
	{
		.part_no	= "1808-D",
		.max_freq	= 375000,
	},
	{
		.part_no	= "1808-F",
		.max_freq	= 456000,
	},
	{
		.part_no	= "1810-D",
		.max_freq	= 375000,
	},
};

#ifdef CONFIG_CPU_FREQ
static void mityomapl138_cpufreq_init(const char *partnum)
{
	int i, ret;

	for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
		/*
		 * the part number has additional characters beyond what is
		 * stored in the table.  This information is not needed for
		 * determining the speed grade, and would require several
		 * more table entries.  Only check the first N characters
		 * for a match.
		 */
		if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
			     strlen(mityomapl138_pn_info[i].part_no))) {
			da850_max_speed = mityomapl138_pn_info[i].max_freq;
			break;
		}
	}

	ret = da850_register_cpufreq("pll0_sysclk3");
	if (ret)
		pr_warning("cpufreq registration failed: %d\n", ret);
}
#else
static void mityomapl138_cpufreq_init(const char *partnum) { }
#endif

static void read_factory_config(struct memory_accessor *a, void *context)
{
	int ret;
	const char *partnum = NULL;
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
	if (ret != sizeof(struct factory_config)) {
		pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
				ret);
		goto bad_config;
	}

	if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
		pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
				factory_config.magic);
		goto bad_config;
	}

	if (factory_config.version != FACTORY_CONFIG_VERSION) {
		pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
				factory_config.version);
		goto bad_config;
	}

	pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
	if (is_valid_ether_addr(factory_config.mac))
		memcpy(soc_info->emac_pdata->mac_addr,
			factory_config.mac, ETH_ALEN);
	else
		pr_warning("MityOMAPL138: Invalid MAC found "
				"in factory config block\n");

	partnum = factory_config.partnum;
	pr_info("MityOMAPL138: Part Number = %s\n", partnum);

bad_config:
	/* default maximum speed is valid for all platforms */
	mityomapl138_cpufreq_init(partnum);
}

static struct at24_platform_data mityomapl138_fd_chip = {
	.byte_len	= 256,
	.page_size	= 8,
	.flags		= AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
	.setup		= read_factory_config,
	.context	= NULL,
};

static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
	.bus_freq	= 100,	/* kHz */
	.bus_delay	= 0,	/* usec */
};

/* TPS65023 voltage regulator support */
/* 1.2V Core */
static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
	{
		.supply = "cvdd",
	},
};

/* 1.8V */
static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
	{
		.supply = "usb0_vdda18",
	},
	{
		.supply = "usb1_vdda18",
	},
	{
		.supply = "ddr_dvdd18",
	},
	{
		.supply = "sata_vddr",
	},
};

/* 1.2V */
static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
	{
		.supply = "sata_vdd",
	},
	{
		.supply = "usb_cvdd",
	},
	{
		.supply = "pll0_vdda",
	},
	{
		.supply = "pll1_vdda",
	},
};

/* 1.8V Aux LDO, not used */
static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
	{
		.supply = "1.8v_aux",
	},
};

/* FPGA VCC Aux (2.5 or 3.3) LDO */
static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
	{
		.supply = "vccaux",
	},
};

static struct regulator_init_data tps65023_regulator_data[] = {
	/* dcdc1 */
	{
		.constraints = {
			.min_uV = 1150000,
			.max_uV = 1350000,
			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
					  REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
		.consumer_supplies = tps65023_dcdc1_consumers,
	},
	/* dcdc2 */
	{
		.constraints = {
			.min_uV = 1800000,
			.max_uV = 1800000,
			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
		.consumer_supplies = tps65023_dcdc2_consumers,
	},
	/* dcdc3 */
	{
		.constraints = {
			.min_uV = 1200000,
			.max_uV = 1200000,
			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
		.consumer_supplies = tps65023_dcdc3_consumers,
	},
	/* ldo1 */
	{
		.constraints = {
			.min_uV = 1800000,
			.max_uV = 1800000,
			.valid_ops_mask = REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
		.consumer_supplies = tps65023_ldo1_consumers,
	},
	/* ldo2 */
	{
		.constraints = {
			.min_uV = 2500000,
			.max_uV = 3300000,
			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
					  REGULATOR_CHANGE_STATUS,
			.boot_on = 1,
		},
		.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
		.consumer_supplies = tps65023_ldo2_consumers,
	},
};

static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
	{
		I2C_BOARD_INFO("tps65023", 0x48),
		.platform_data = &tps65023_regulator_data[0],
	},
	{
		I2C_BOARD_INFO("24c02", 0x50),
		.platform_data = &mityomapl138_fd_chip,
	},
};

static int __init pmic_tps65023_init(void)
{
	return i2c_register_board_info(1, mityomap_tps65023_info,
					ARRAY_SIZE(mityomap_tps65023_info));
}

/*
 * MityDSP-L138 includes a 256 MByte large-page NAND flash
 * (128K blocks).
 */
static struct mtd_partition mityomapl138_nandflash_partition[] = {
	{
		.name		= "rootfs",
		.offset		= 0,
		.size		= SZ_128M,
		.mask_flags	= 0, /* MTD_WRITEABLE, */
	},
	{
		.name		= "homefs",
		.offset		= MTDPART_OFS_APPEND,
		.size		= MTDPART_SIZ_FULL,
		.mask_flags	= 0,
	},
};

static struct davinci_nand_pdata mityomapl138_nandflash_data = {
	.parts		= mityomapl138_nandflash_partition,
	.nr_parts	= ARRAY_SIZE(mityomapl138_nandflash_partition),
	.ecc_mode	= NAND_ECC_HW,
	.options	= NAND_USE_FLASH_BBT | NAND_BUSWIDTH_16,
	.ecc_bits	= 1, /* 4 bit mode is not supported with 16 bit NAND */
};

static struct resource mityomapl138_nandflash_resource[] = {
	{
		.start	= DA8XX_AEMIF_CS3_BASE,
		.end	= DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= DA8XX_AEMIF_CTL_BASE,
		.end	= DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device mityomapl138_nandflash_device = {
	.name		= "davinci_nand",
	.id		= 0,
	.dev		= {
		.platform_data	= &mityomapl138_nandflash_data,
	},
	.num_resources	= ARRAY_SIZE(mityomapl138_nandflash_resource),
	.resource	= mityomapl138_nandflash_resource,
};

static struct platform_device *mityomapl138_devices[] __initdata = {
	&mityomapl138_nandflash_device,
};

static void __init mityomapl138_setup_nand(void)
{
	platform_add_devices(mityomapl138_devices,
				 ARRAY_SIZE(mityomapl138_devices));
}

static struct davinci_uart_config mityomapl138_uart_config __initdata = {
	.enabled_uarts = 0x7,
};

static const short mityomap_mii_pins[] = {
	DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
	DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
	DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
	DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
	DA850_MDIO_D,
	-1
};

static const short mityomap_rmii_pins[] = {
	DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
	DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
	DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
	DA850_MDIO_D,
	-1
};

static void __init mityomapl138_config_emac(void)
{
	void __iomem *cfg_chip3_base;
	int ret;
	u32 val;
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */

	cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
	val = __raw_readl(cfg_chip3_base);

	if (soc_info->emac_pdata->rmii_en) {
		val |= BIT(8);
		ret = davinci_cfg_reg_list(mityomap_rmii_pins);
		pr_info("RMII PHY configured\n");
	} else {
		val &= ~BIT(8);
		ret = davinci_cfg_reg_list(mityomap_mii_pins);
		pr_info("MII PHY configured\n");
	}

	if (ret) {
		pr_warning("mii/rmii mux setup failed: %d\n", ret);
		return;
	}

	/* configure the CFGCHIP3 register for RMII or MII */
	__raw_writel(val, cfg_chip3_base);

	soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;

	ret = da8xx_register_emac();
	if (ret)
		pr_warning("emac registration failed: %d\n", ret);
}

static struct davinci_pm_config da850_pm_pdata = {
	.sleepcount = 128,
};

static struct platform_device da850_pm_device = {
	.name	= "pm-davinci",
	.dev = {
		.platform_data  = &da850_pm_pdata,
	},
	.id	= -1,
};

static void __init mityomapl138_init(void)
{
	int ret;

	/* for now, no special EDMA channels are reserved */
	ret = da850_register_edma(NULL);
	if (ret)
		pr_warning("edma registration failed: %d\n", ret);

	ret = da8xx_register_watchdog();
	if (ret)
		pr_warning("watchdog registration failed: %d\n", ret);

	davinci_serial_init(&mityomapl138_uart_config);

	ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
	if (ret)
		pr_warning("i2c0 registration failed: %d\n", ret);

	ret = pmic_tps65023_init();
	if (ret)
		pr_warning("TPS65023 PMIC init failed: %d\n", ret);

	mityomapl138_setup_nand();

	mityomapl138_config_emac();

	ret = da8xx_register_rtc();
	if (ret)
		pr_warning("rtc setup failed: %d\n", ret);

	ret = da8xx_register_cpuidle();
	if (ret)
		pr_warning("cpuidle registration failed: %d\n", ret);

	ret = da850_register_pm(&da850_pm_device);
	if (ret)
		pr_warning("da850_evm_init: suspend registration failed: %d\n",
				ret);
}

#ifdef CONFIG_SERIAL_8250_CONSOLE
static int __init mityomapl138_console_init(void)
{
	if (!machine_is_mityomapl138())
		return 0;

	return add_preferred_console("ttyS", 1, "115200");
}
console_initcall(mityomapl138_console_init);
#endif

static void __init mityomapl138_map_io(void)
{
	da850_init();
}

MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
	.boot_params	= (DA8XX_DDR_BASE + 0x100),
	.map_io		= mityomapl138_map_io,
	.init_irq	= cp_intc_init,
	.timer		= &davinci_timer,
	.init_machine	= mityomapl138_init,
MACHINE_END
Commit	Line	Data
f2dbb6d9 MW	1	/*
	2	* Critical Link MityOMAP-L138 SoM
	3	*
	4	* Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of
	8	* any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/console.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/mtd/partitions.h>
87748823 MW	16	#include <linux/regulator/machine.h>
87748823 MW	17	#include <linux/i2c.h>
2a7dae04 MW	18	#include <linux/i2c/at24.h>
2a7dae04 MW	19	#include <linux/etherdevice.h>
f2dbb6d9 MW	20
	21	#include <asm/mach-types.h>
	22	#include <asm/mach/arch.h>
	23	#include <mach/common.h>
	24	#include <mach/cp_intc.h>
	25	#include <mach/da8xx.h>
	26	#include <mach/nand.h>
	27	#include <mach/mux.h>
	28
782f2d78	29	#define MITYOMAPL138_PHY_ID "0:03"
2a7dae04 MW	30
	31	#define FACTORY_CONFIG_MAGIC 0x012C0138
	32	#define FACTORY_CONFIG_VERSION 0x00010001
	33
	34	/* Data Held in On-Board I2C device */
	35	struct factory_config {
	36	u32 magic;
	37	u32 version;
	38	u8 mac[6];
	39	u32 fpga_type;
	40	u32 spare;
	41	u32 serialnumber;
	42	char partnum[32];
	43	};
	44
	45	static struct factory_config factory_config;
	46
6619490a MW	47	struct part_no_info {
	48	const char part_no; / part number string of interest */
	49	int max_freq; /* khz */
	50	};
	51
	52	static struct part_no_info mityomapl138_pn_info[] = {
	53	{
	54	.part_no = "L138-C",
	55	.max_freq = 300000,
	56	},
	57	{
	58	.part_no = "L138-D",
	59	.max_freq = 375000,
	60	},
	61	{
	62	.part_no = "L138-F",
	63	.max_freq = 456000,
	64	},
	65	{
	66	.part_no = "1808-C",
	67	.max_freq = 300000,
	68	},
	69	{
	70	.part_no = "1808-D",
	71	.max_freq = 375000,
	72	},
	73	{
	74	.part_no = "1808-F",
	75	.max_freq = 456000,
	76	},
	77	{
	78	.part_no = "1810-D",
	79	.max_freq = 375000,
	80	},
	81	};
	82
	83	#ifdef CONFIG_CPU_FREQ
	84	static void mityomapl138_cpufreq_init(const char *partnum)
	85	{
	86	int i, ret;
	87
	88	for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
	89	/*
	90	* the part number has additional characters beyond what is
	91	* stored in the table. This information is not needed for
	92	* determining the speed grade, and would require several
	93	* more table entries. Only check the first N characters
	94	* for a match.
	95	*/
	96	if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
	97	strlen(mityomapl138_pn_info[i].part_no))) {
	98	da850_max_speed = mityomapl138_pn_info[i].max_freq;
	99	break;
	100	}
	101	}
	102
	103	ret = da850_register_cpufreq("pll0_sysclk3");
	104	if (ret)
	105	pr_warning("cpufreq registration failed: %d\n", ret);
	106	}
	107	#else
	108	static void mityomapl138_cpufreq_init(const char *partnum) { }
	109	#endif
	110
2a7dae04 MW	111	static void read_factory_config(struct memory_accessor a, void context)
	112	{
	113	int ret;
6619490a	114	const char *partnum = NULL;
2a7dae04 MW	115	struct davinci_soc_info *soc_info = &davinci_soc_info;
	116
	117	ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
	118	if (ret != sizeof(struct factory_config)) {
	119	pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
	120	ret);
6619490a	121	goto bad_config;
2a7dae04 MW	122	}
	123
	124	if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
	125	pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
	126	factory_config.magic);
6619490a	127	goto bad_config;
2a7dae04 MW	128	}
	129
	130	if (factory_config.version != FACTORY_CONFIG_VERSION) {
	131	pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
	132	factory_config.version);
6619490a	133	goto bad_config;
2a7dae04 MW	134	}
	135
	136	pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
2a7dae04 MW	137	if (is_valid_ether_addr(factory_config.mac))
	138	memcpy(soc_info->emac_pdata->mac_addr,
	139	factory_config.mac, ETH_ALEN);
	140	else
	141	pr_warning("MityOMAPL138: Invalid MAC found "
	142	"in factory config block\n");
6619490a MW	143
	144	partnum = factory_config.partnum;
	145	pr_info("MityOMAPL138: Part Number = %s\n", partnum);
	146
	147	bad_config:
	148	/* default maximum speed is valid for all platforms */
	149	mityomapl138_cpufreq_init(partnum);
2a7dae04 MW	150	}
	151
	152	static struct at24_platform_data mityomapl138_fd_chip = {
	153	.byte_len = 256,
	154	.page_size = 8,
	155	.flags = AT24_FLAG_READONLY \| AT24_FLAG_IRUGO,
	156	.setup = read_factory_config,
	157	.context = NULL,
	158	};
	159
87748823 MW	160	static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
	161	.bus_freq = 100, /* kHz */
	162	.bus_delay = 0, /* usec */
	163	};
	164
	165	/* TPS65023 voltage regulator support */
	166	/* 1.2V Core */
8939b350	167	static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
87748823 MW	168	{
	169	.supply = "cvdd",
	170	},
	171	};
	172
	173	/* 1.8V */
8939b350	174	static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
87748823 MW	175	{
	176	.supply = "usb0_vdda18",
	177	},
	178	{
	179	.supply = "usb1_vdda18",
	180	},
	181	{
	182	.supply = "ddr_dvdd18",
	183	},
	184	{
	185	.supply = "sata_vddr",
	186	},
	187	};
	188
	189	/* 1.2V */
8939b350	190	static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
87748823 MW	191	{
	192	.supply = "sata_vdd",
	193	},
	194	{
	195	.supply = "usb_cvdd",
	196	},
	197	{
	198	.supply = "pll0_vdda",
	199	},
	200	{
	201	.supply = "pll1_vdda",
	202	},
	203	};
	204
	205	/* 1.8V Aux LDO, not used */
8939b350	206	static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
87748823 MW	207	{
	208	.supply = "1.8v_aux",
	209	},
	210	};
	211
	212	/* FPGA VCC Aux (2.5 or 3.3) LDO */
8939b350	213	static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
87748823 MW	214	{
	215	.supply = "vccaux",
	216	},
	217	};
	218
8939b350	219	static struct regulator_init_data tps65023_regulator_data[] = {
87748823 MW	220	/* dcdc1 */
	221	{
	222	.constraints = {
	223	.min_uV = 1150000,
	224	.max_uV = 1350000,
	225	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE \|
	226	REGULATOR_CHANGE_STATUS,
	227	.boot_on = 1,
	228	},
	229	.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
	230	.consumer_supplies = tps65023_dcdc1_consumers,
	231	},
	232	/* dcdc2 */
	233	{
	234	.constraints = {
	235	.min_uV = 1800000,
	236	.max_uV = 1800000,
	237	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
	238	.boot_on = 1,
	239	},
	240	.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
	241	.consumer_supplies = tps65023_dcdc2_consumers,
	242	},
	243	/* dcdc3 */
	244	{
	245	.constraints = {
	246	.min_uV = 1200000,
	247	.max_uV = 1200000,
	248	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
	249	.boot_on = 1,
	250	},
	251	.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
	252	.consumer_supplies = tps65023_dcdc3_consumers,
	253	},
	254	/* ldo1 */
	255	{
	256	.constraints = {
	257	.min_uV = 1800000,
	258	.max_uV = 1800000,
	259	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
	260	.boot_on = 1,
	261	},
	262	.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
	263	.consumer_supplies = tps65023_ldo1_consumers,
	264	},
	265	/* ldo2 */
	266	{
	267	.constraints = {
	268	.min_uV = 2500000,
	269	.max_uV = 3300000,
	270	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE \|
	271	REGULATOR_CHANGE_STATUS,
	272	.boot_on = 1,
	273	},
	274	.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
	275	.consumer_supplies = tps65023_ldo2_consumers,
	276	},
	277	};
	278
	279	static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
	280	{
	281	I2C_BOARD_INFO("tps65023", 0x48),
	282	.platform_data = &tps65023_regulator_data[0],
	283	},
284	{
285	I2C_BOARD_INFO("24c02", 0x50),
2a7dae04	286	.platform_data = &mityomapl138_fd_chip,
87748823 MW	287	},
	288	};
	289
	290	static int __init pmic_tps65023_init(void)
	291	{
	292	return i2c_register_board_info(1, mityomap_tps65023_info,
	293	ARRAY_SIZE(mityomap_tps65023_info));
	294	}
	295
f2dbb6d9 MW	296	/*
	297	* MityDSP-L138 includes a 256 MByte large-page NAND flash
	298	* (128K blocks).
	299	*/
8939b350	300	static struct mtd_partition mityomapl138_nandflash_partition[] = {
f2dbb6d9 MW	301	{
	302	.name = "rootfs",
	303	.offset = 0,
	304	.size = SZ_128M,
	305	.mask_flags = 0, /* MTD_WRITEABLE, */
	306	},
	307	{
	308	.name = "homefs",
	309	.offset = MTDPART_OFS_APPEND,
	310	.size = MTDPART_SIZ_FULL,
	311	.mask_flags = 0,
	312	},
	313	};
	314
	315	static struct davinci_nand_pdata mityomapl138_nandflash_data = {
	316	.parts = mityomapl138_nandflash_partition,
	317	.nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
	318	.ecc_mode = NAND_ECC_HW,
	319	.options = NAND_USE_FLASH_BBT \| NAND_BUSWIDTH_16,
	320	.ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */
	321	};
	322
	323	static struct resource mityomapl138_nandflash_resource[] = {
	324	{
	325	.start = DA8XX_AEMIF_CS3_BASE,
	326	.end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
	327	.flags = IORESOURCE_MEM,
	328	},
	329	{
	330	.start = DA8XX_AEMIF_CTL_BASE,
	331	.end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
	332	.flags = IORESOURCE_MEM,
	333	},
	334	};
	335
	336	static struct platform_device mityomapl138_nandflash_device = {
	337	.name = "davinci_nand",
	338	.id = 0,
	339	.dev = {
	340	.platform_data = &mityomapl138_nandflash_data,
	341	},
	342	.num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
	343	.resource = mityomapl138_nandflash_resource,
	344	};
	345
	346	static struct platform_device *mityomapl138_devices[] __initdata = {
	347	&mityomapl138_nandflash_device,
	348	};
	349
	350	static void __init mityomapl138_setup_nand(void)
	351	{
	352	platform_add_devices(mityomapl138_devices,
	353	ARRAY_SIZE(mityomapl138_devices));
	354	}
	355
	356	static struct davinci_uart_config mityomapl138_uart_config __initdata = {
	357	.enabled_uarts = 0x7,
	358	};
	359
	360	static const short mityomap_mii_pins[] = {
	361	DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
	362	DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
	363	DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
	364	DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
365	DA850_MDIO_D,
366	-1
367	};
368
369	static const short mityomap_rmii_pins[] = {
370	DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
371	DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
372	DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
373	DA850_MDIO_D,
374	-1
375	};
376
377	static void __init mityomapl138_config_emac(void)
378	{
379	void __iomem *cfg_chip3_base;
380	int ret;
381	u32 val;
382	struct davinci_soc_info *soc_info = &davinci_soc_info;
383
384	soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
385
386	cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
387	val = __raw_readl(cfg_chip3_base);
388
389	if (soc_info->emac_pdata->rmii_en) {
390	val \|= BIT(8);
391	ret = davinci_cfg_reg_list(mityomap_rmii_pins);
392	pr_info("RMII PHY configured\n");
393	} else {
394	val &= ~BIT(8);
395	ret = davinci_cfg_reg_list(mityomap_mii_pins);
396	pr_info("MII PHY configured\n");
397	}
398
399	if (ret) {
400	pr_warning("mii/rmii mux setup failed: %d\n", ret);
401	return;
402	}
403
404	/* configure the CFGCHIP3 register for RMII or MII */
405	__raw_writel(val, cfg_chip3_base);
406
782f2d78	407	soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
f2dbb6d9 MW	408
	409	ret = da8xx_register_emac();
	410	if (ret)
	411	pr_warning("emac registration failed: %d\n", ret);
	412	}
	413
	414	static struct davinci_pm_config da850_pm_pdata = {
	415	.sleepcount = 128,
	416	};
	417
	418	static struct platform_device da850_pm_device = {
	419	.name = "pm-davinci",
	420	.dev = {
	421	.platform_data = &da850_pm_pdata,
	422	},
	423	.id = -1,
	424	};
	425
	426	static void __init mityomapl138_init(void)
	427	{
	428	int ret;
	429
	430	/* for now, no special EDMA channels are reserved */
	431	ret = da850_register_edma(NULL);
	432	if (ret)
	433	pr_warning("edma registration failed: %d\n", ret);
	434
	435	ret = da8xx_register_watchdog();
	436	if (ret)
	437	pr_warning("watchdog registration failed: %d\n", ret);
	438
	439	davinci_serial_init(&mityomapl138_uart_config);
	440
87748823 MW	441	ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
	442	if (ret)
	443	pr_warning("i2c0 registration failed: %d\n", ret);
	444
	445	ret = pmic_tps65023_init();
	446	if (ret)
	447	pr_warning("TPS65023 PMIC init failed: %d\n", ret);
	448
f2dbb6d9 MW	449	mityomapl138_setup_nand();
	450
	451	mityomapl138_config_emac();
	452
	453	ret = da8xx_register_rtc();
	454	if (ret)
	455	pr_warning("rtc setup failed: %d\n", ret);
	456
f2dbb6d9 MW	457	ret = da8xx_register_cpuidle();
	458	if (ret)
	459	pr_warning("cpuidle registration failed: %d\n", ret);
	460
	461	ret = da850_register_pm(&da850_pm_device);
	462	if (ret)
	463	pr_warning("da850_evm_init: suspend registration failed: %d\n",
	464	ret);
	465	}
	466
	467	#ifdef CONFIG_SERIAL_8250_CONSOLE
	468	static int __init mityomapl138_console_init(void)
	469	{
	470	if (!machine_is_mityomapl138())
	471	return 0;
	472
	473	return add_preferred_console("ttyS", 1, "115200");
	474	}
	475	console_initcall(mityomapl138_console_init);
	476	#endif
	477
	478	static void __init mityomapl138_map_io(void)
	479	{
	480	da850_init();
	481	}
	482
	483	MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
f2dbb6d9 MW	484	.boot_params = (DA8XX_DDR_BASE + 0x100),
	485	.map_io = mityomapl138_map_io,
	486	.init_irq = cp_intc_init,
	487	.timer = &davinci_timer,
	488	.init_machine = mityomapl138_init,
	489	MACHINE_END