[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-davinci / clock.c

/*
 * Clock and PLL control for DaVinci devices
 *
 * Copyright (C) 2006-2007 Texas Instruments.
 * Copyright (C) 2008-2009 Deep Root Systems, LLC
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/io.h>
#include <linux/delay.h>

#include <mach/hardware.h>

#include <mach/clock.h>
#include "psc.h"
#include <mach/cputype.h>
#include "clock.h"

static LIST_HEAD(clocks);
static DEFINE_MUTEX(clocks_mutex);
static DEFINE_SPINLOCK(clockfw_lock);

void davinci_clk_enable(struct clk *clk)
{
	if (clk->parent)
		davinci_clk_enable(clk->parent);
	if (clk->usecount++ == 0) {
		if (clk->flags & CLK_PSC)
			davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
					   true, clk->flags);
		else if (clk->clk_enable)
			clk->clk_enable(clk);
	}
}

void davinci_clk_disable(struct clk *clk)
{
	if (WARN_ON(clk->usecount == 0))
		return;
	if (--clk->usecount == 0) {
		if (!(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC))
			davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
					   false, clk->flags);
		else if (clk->clk_disable)
			clk->clk_disable(clk);
	}
	if (clk->parent)
		davinci_clk_disable(clk->parent);
}

int davinci_clk_reset(struct clk *clk, bool reset)
{
	unsigned long flags;

	if (clk == NULL || IS_ERR(clk))
		return -EINVAL;

	spin_lock_irqsave(&clockfw_lock, flags);
	if (clk->flags & CLK_PSC)
		davinci_psc_reset(clk->gpsc, clk->lpsc, reset);
	spin_unlock_irqrestore(&clockfw_lock, flags);

	return 0;
}
EXPORT_SYMBOL(davinci_clk_reset);

int davinci_clk_reset_assert(struct clk *clk)
{
	if (clk == NULL || IS_ERR(clk) || !clk->reset)
		return -EINVAL;

	return clk->reset(clk, true);
}
EXPORT_SYMBOL(davinci_clk_reset_assert);

int davinci_clk_reset_deassert(struct clk *clk)
{
	if (clk == NULL || IS_ERR(clk) || !clk->reset)
		return -EINVAL;

	return clk->reset(clk, false);
}
EXPORT_SYMBOL(davinci_clk_reset_deassert);

int clk_enable(struct clk *clk)
{
	unsigned long flags;

	if (!clk)
		return 0;
	else if (IS_ERR(clk))
		return -EINVAL;

	spin_lock_irqsave(&clockfw_lock, flags);
	davinci_clk_enable(clk);
	spin_unlock_irqrestore(&clockfw_lock, flags);

	return 0;
}
EXPORT_SYMBOL(clk_enable);

void clk_disable(struct clk *clk)
{
	unsigned long flags;

	if (clk == NULL || IS_ERR(clk))
		return;

	spin_lock_irqsave(&clockfw_lock, flags);
	davinci_clk_disable(clk);
	spin_unlock_irqrestore(&clockfw_lock, flags);
}
EXPORT_SYMBOL(clk_disable);

unsigned long clk_get_rate(struct clk *clk)
{
	if (clk == NULL || IS_ERR(clk))
		return 0;

	return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);

long clk_round_rate(struct clk *clk, unsigned long rate)
{
	if (clk == NULL || IS_ERR(clk))
		return 0;

	if (clk->round_rate)
		return clk->round_rate(clk, rate);

	return clk->rate;
}
EXPORT_SYMBOL(clk_round_rate);

/* Propagate rate to children */
static void propagate_rate(struct clk *root)
{
	struct clk *clk;

	list_for_each_entry(clk, &root->children, childnode) {
		if (clk->recalc)
			clk->rate = clk->recalc(clk);
		propagate_rate(clk);
	}
}

int clk_set_rate(struct clk *clk, unsigned long rate)
{
	unsigned long flags;
	int ret = -EINVAL;

	if (!clk)
		return 0;
	else if (IS_ERR(clk))
		return -EINVAL;

	if (clk->set_rate)
		ret = clk->set_rate(clk, rate);

	spin_lock_irqsave(&clockfw_lock, flags);
	if (ret == 0) {
		if (clk->recalc)
			clk->rate = clk->recalc(clk);
		propagate_rate(clk);
	}
	spin_unlock_irqrestore(&clockfw_lock, flags);

	return ret;
}
EXPORT_SYMBOL(clk_set_rate);

int clk_set_parent(struct clk *clk, struct clk *parent)
{
	unsigned long flags;

	if (!clk)
		return 0;
	else if (IS_ERR(clk))
		return -EINVAL;

	/* Cannot change parent on enabled clock */
	if (WARN_ON(clk->usecount))
		return -EINVAL;

	mutex_lock(&clocks_mutex);
	if (clk->set_parent) {
		int ret = clk->set_parent(clk, parent);

		if (ret) {
			mutex_unlock(&clocks_mutex);
			return ret;
		}
	}
	clk->parent = parent;
	list_del_init(&clk->childnode);
	list_add(&clk->childnode, &clk->parent->children);
	mutex_unlock(&clocks_mutex);

	spin_lock_irqsave(&clockfw_lock, flags);
	if (clk->recalc)
		clk->rate = clk->recalc(clk);
	propagate_rate(clk);
	spin_unlock_irqrestore(&clockfw_lock, flags);

	return 0;
}
EXPORT_SYMBOL(clk_set_parent);

struct clk *clk_get_parent(struct clk *clk)
{
	if (!clk)
		return NULL;

	return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);

int clk_register(struct clk *clk)
{
	if (clk == NULL || IS_ERR(clk))
		return -EINVAL;

	if (WARN(clk->parent && !clk->parent->rate,
			"CLK: %s parent %s has no rate!\n",
			clk->name, clk->parent->name))
		return -EINVAL;

	INIT_LIST_HEAD(&clk->children);

	mutex_lock(&clocks_mutex);
	list_add_tail(&clk->node, &clocks);
	if (clk->parent) {
		if (clk->set_parent) {
			int ret = clk->set_parent(clk, clk->parent);

			if (ret) {
				mutex_unlock(&clocks_mutex);
				return ret;
			}
		}
		list_add_tail(&clk->childnode, &clk->parent->children);
	}
	mutex_unlock(&clocks_mutex);

	/* If rate is already set, use it */
	if (clk->rate)
		return 0;

	/* Else, see if there is a way to calculate it */
	if (clk->recalc)
		clk->rate = clk->recalc(clk);

	/* Otherwise, default to parent rate */
	else if (clk->parent)
		clk->rate = clk->parent->rate;

	return 0;
}
EXPORT_SYMBOL(clk_register);

void clk_unregister(struct clk *clk)
{
	if (clk == NULL || IS_ERR(clk))
		return;

	mutex_lock(&clocks_mutex);
	list_del(&clk->node);
	list_del(&clk->childnode);
	mutex_unlock(&clocks_mutex);
}
EXPORT_SYMBOL(clk_unregister);

#ifdef CONFIG_DAVINCI_RESET_CLOCKS
/*
 * Disable any unused clocks left on by the bootloader
 */
int __init davinci_clk_disable_unused(void)
{
	struct clk *ck;

	spin_lock_irq(&clockfw_lock);
	list_for_each_entry(ck, &clocks, node) {
		if (ck->usecount > 0)
			continue;
		if (!(ck->flags & CLK_PSC))
			continue;

		/* ignore if in Disabled or SwRstDisable states */
		if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc))
			continue;

		pr_debug("Clocks: disable unused %s\n", ck->name);

		davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc,
				false, ck->flags);
	}
	spin_unlock_irq(&clockfw_lock);

	return 0;
}
#endif

static unsigned long clk_sysclk_recalc(struct clk *clk)
{
	u32 v, plldiv;
	struct pll_data *pll;
	unsigned long rate = clk->rate;

	/* If this is the PLL base clock, no more calculations needed */
	if (clk->pll_data)
		return rate;

	if (WARN_ON(!clk->parent))
		return rate;

	rate = clk->parent->rate;

	/* Otherwise, the parent must be a PLL */
	if (WARN_ON(!clk->parent->pll_data))
		return rate;

	pll = clk->parent->pll_data;

	/* If pre-PLL, source clock is before the multiplier and divider(s) */
	if (clk->flags & PRE_PLL)
		rate = pll->input_rate;

	if (!clk->div_reg)
		return rate;

	v = __raw_readl(pll->base + clk->div_reg);
	if (v & PLLDIV_EN) {
		plldiv = (v & pll->div_ratio_mask) + 1;
		if (plldiv)
			rate /= plldiv;
	}

	return rate;
}

int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
{
	unsigned v;
	struct pll_data *pll;
	unsigned long input;
	unsigned ratio = 0;

	/* If this is the PLL base clock, wrong function to call */
	if (clk->pll_data)
		return -EINVAL;

	/* There must be a parent... */
	if (WARN_ON(!clk->parent))
		return -EINVAL;

	/* ... the parent must be a PLL... */
	if (WARN_ON(!clk->parent->pll_data))
		return -EINVAL;

	/* ... and this clock must have a divider. */
	if (WARN_ON(!clk->div_reg))
		return -EINVAL;

	pll = clk->parent->pll_data;

	input = clk->parent->rate;

	/* If pre-PLL, source clock is before the multiplier and divider(s) */
	if (clk->flags & PRE_PLL)
		input = pll->input_rate;

	if (input > rate) {
		/*
		 * Can afford to provide an output little higher than requested
		 * only if maximum rate supported by hardware on this sysclk
		 * is known.
		 */
		if (clk->maxrate) {
			ratio = DIV_ROUND_CLOSEST(input, rate);
			if (input / ratio > clk->maxrate)
				ratio = 0;
		}

		if (ratio == 0)
			ratio = DIV_ROUND_UP(input, rate);

		ratio--;
	}

	if (ratio > pll->div_ratio_mask)
		return -EINVAL;

	do {
		v = __raw_readl(pll->base + PLLSTAT);
	} while (v & PLLSTAT_GOSTAT);

	v = __raw_readl(pll->base + clk->div_reg);
	v &= ~pll->div_ratio_mask;
	v |= ratio | PLLDIV_EN;
	__raw_writel(v, pll->base + clk->div_reg);

	v = __raw_readl(pll->base + PLLCMD);
	v |= PLLCMD_GOSET;
	__raw_writel(v, pll->base + PLLCMD);

	do {
		v = __raw_readl(pll->base + PLLSTAT);
	} while (v & PLLSTAT_GOSTAT);

	return 0;
}
EXPORT_SYMBOL(davinci_set_sysclk_rate);

static unsigned long clk_leafclk_recalc(struct clk *clk)
{
	if (WARN_ON(!clk->parent))
		return clk->rate;

	return clk->parent->rate;
}

int davinci_simple_set_rate(struct clk *clk, unsigned long rate)
{
	clk->rate = rate;
	return 0;
}

static unsigned long clk_pllclk_recalc(struct clk *clk)
{
	u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
	u8 bypass;
	struct pll_data *pll = clk->pll_data;
	unsigned long rate = clk->rate;

	ctrl = __raw_readl(pll->base + PLLCTL);
	rate = pll->input_rate = clk->parent->rate;

	if (ctrl & PLLCTL_PLLEN) {
		bypass = 0;
		mult = __raw_readl(pll->base + PLLM);
		if (cpu_is_davinci_dm365())
			mult = 2 * (mult & PLLM_PLLM_MASK);
		else
			mult = (mult & PLLM_PLLM_MASK) + 1;
	} else
		bypass = 1;

	if (pll->flags & PLL_HAS_PREDIV) {
		prediv = __raw_readl(pll->base + PREDIV);
		if (prediv & PLLDIV_EN)
			prediv = (prediv & pll->div_ratio_mask) + 1;
		else
			prediv = 1;
	}

	/* pre-divider is fixed, but (some?) chips won't report that */
	if (cpu_is_davinci_dm355() && pll->num == 1)
		prediv = 8;

	if (pll->flags & PLL_HAS_POSTDIV) {
		postdiv = __raw_readl(pll->base + POSTDIV);
		if (postdiv & PLLDIV_EN)
			postdiv = (postdiv & pll->div_ratio_mask) + 1;
		else
			postdiv = 1;
	}

	if (!bypass) {
		rate /= prediv;
		rate *= mult;
		rate /= postdiv;
	}

	pr_debug("PLL%d: input = %lu MHz [ ",
		 pll->num, clk->parent->rate / 1000000);
	if (bypass)
		pr_debug("bypass ");
	if (prediv > 1)
		pr_debug("/ %d ", prediv);
	if (mult > 1)
		pr_debug("* %d ", mult);
	if (postdiv > 1)
		pr_debug("/ %d ", postdiv);
	pr_debug("] --> %lu MHz output.\n", rate / 1000000);

	return rate;
}

/**
 * davinci_set_pllrate - set the output rate of a given PLL.
 *
 * Note: Currently tested to work with OMAP-L138 only.
 *
 * @pll: pll whose rate needs to be changed.
 * @prediv: The pre divider value. Passing 0 disables the pre-divider.
 * @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
 * @postdiv: The post divider value. Passing 0 disables the post-divider.
 */
int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
					unsigned int mult, unsigned int postdiv)
{
	u32 ctrl;
	unsigned int locktime;
	unsigned long flags;

	if (pll->base == NULL)
		return -EINVAL;

	/*
	 *  PLL lock time required per OMAP-L138 datasheet is
	 * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
	 * as 4 and OSCIN cycle as 25 MHz.
	 */
	if (prediv) {
		locktime = ((2000 * prediv) / 100);
		prediv = (prediv - 1) | PLLDIV_EN;
	} else {
		locktime = PLL_LOCK_TIME;
	}
	if (postdiv)
		postdiv = (postdiv - 1) | PLLDIV_EN;
	if (mult)
		mult = mult - 1;

	/* Protect against simultaneous calls to PLL setting seqeunce */
	spin_lock_irqsave(&clockfw_lock, flags);

	ctrl = __raw_readl(pll->base + PLLCTL);

	/* Switch the PLL to bypass mode */
	ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
	__raw_writel(ctrl, pll->base + PLLCTL);

	udelay(PLL_BYPASS_TIME);

	/* Reset and enable PLL */
	ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
	__raw_writel(ctrl, pll->base + PLLCTL);

	if (pll->flags & PLL_HAS_PREDIV)
		__raw_writel(prediv, pll->base + PREDIV);

	__raw_writel(mult, pll->base + PLLM);

	if (pll->flags & PLL_HAS_POSTDIV)
		__raw_writel(postdiv, pll->base + POSTDIV);

	udelay(PLL_RESET_TIME);

	/* Bring PLL out of reset */
	ctrl |= PLLCTL_PLLRST;
	__raw_writel(ctrl, pll->base + PLLCTL);

	udelay(locktime);

	/* Remove PLL from bypass mode */
	ctrl |= PLLCTL_PLLEN;
	__raw_writel(ctrl, pll->base + PLLCTL);

	spin_unlock_irqrestore(&clockfw_lock, flags);

	return 0;
}
EXPORT_SYMBOL(davinci_set_pllrate);

/**
 * davinci_set_refclk_rate() - Set the reference clock rate
 * @rate:	The new rate.
 *
 * Sets the reference clock rate to a given value. This will most likely
 * result in the entire clock tree getting updated.
 *
 * This is used to support boards which use a reference clock different
 * than that used by default in <soc>.c file. The reference clock rate
 * should be updated early in the boot process; ideally soon after the
 * clock tree has been initialized once with the default reference clock
 * rate (davinci_clk_init()).
 *
 * Returns 0 on success, error otherwise.
 */
int davinci_set_refclk_rate(unsigned long rate)
{
	struct clk *refclk;

	refclk = clk_get(NULL, "ref");
	if (IS_ERR(refclk)) {
		pr_err("%s: failed to get reference clock\n", __func__);
		return PTR_ERR(refclk);
	}

	clk_set_rate(refclk, rate);

	clk_put(refclk);

	return 0;
}

int __init davinci_clk_init(struct clk_lookup *clocks)
{
	struct clk_lookup *c;
	struct clk *clk;
	size_t num_clocks = 0;

	for (c = clocks; c->clk; c++) {
		clk = c->clk;

		if (!clk->recalc) {

			/* Check if clock is a PLL */
			if (clk->pll_data)
				clk->recalc = clk_pllclk_recalc;

			/* Else, if it is a PLL-derived clock */
			else if (clk->flags & CLK_PLL)
				clk->recalc = clk_sysclk_recalc;

			/* Otherwise, it is a leaf clock (PSC clock) */
			else if (clk->parent)
				clk->recalc = clk_leafclk_recalc;
		}

		if (clk->pll_data) {
			struct pll_data *pll = clk->pll_data;

			if (!pll->div_ratio_mask)
				pll->div_ratio_mask = PLLDIV_RATIO_MASK;

			if (pll->phys_base && !pll->base) {
				pll->base = ioremap(pll->phys_base, SZ_4K);
				WARN_ON(!pll->base);
			}
		}

		if (clk->recalc)
			clk->rate = clk->recalc(clk);

		if (clk->lpsc)
			clk->flags |= CLK_PSC;

		if (clk->flags & PSC_LRST)
			clk->reset = davinci_clk_reset;

		clk_register(clk);
		num_clocks++;

		/* Turn on clocks that Linux doesn't otherwise manage */
		if (clk->flags & ALWAYS_ENABLED)
			clk_enable(clk);
	}

	clkdev_add_table(clocks, num_clocks);

	return 0;
}

#ifdef CONFIG_DEBUG_FS

#include <linux/debugfs.h>
#include <linux/seq_file.h>

#define CLKNAME_MAX	10		/* longest clock name */
#define NEST_DELTA	2
#define NEST_MAX	4

static void
dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
{
	char		*state;
	char		buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
	struct clk	*clk;
	unsigned	i;

	if (parent->flags & CLK_PLL)
		state = "pll";
	else if (parent->flags & CLK_PSC)
		state = "psc";
	else
		state = "";

	/* <nest spaces> name <pad to end> */
	memset(buf, ' ', sizeof(buf) - 1);
	buf[sizeof(buf) - 1] = 0;
	i = strlen(parent->name);
	memcpy(buf + nest, parent->name,
			min(i, (unsigned)(sizeof(buf) - 1 - nest)));

	seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
		   buf, parent->usecount, state, clk_get_rate(parent));
	/* REVISIT show device associations too */

	/* cost is now small, but not linear... */
	list_for_each_entry(clk, &parent->children, childnode) {
		dump_clock(s, nest + NEST_DELTA, clk);
	}
}

static int davinci_ck_show(struct seq_file *m, void *v)
{
	struct clk *clk;

	/*
	 * Show clock tree; We trust nonzero usecounts equate to PSC enables...
	 */
	mutex_lock(&clocks_mutex);
	list_for_each_entry(clk, &clocks, node)
		if (!clk->parent)
			dump_clock(m, 0, clk);
	mutex_unlock(&clocks_mutex);

	return 0;
}

static int davinci_ck_open(struct inode *inode, struct file *file)
{
	return single_open(file, davinci_ck_show, NULL);
}

static const struct file_operations davinci_ck_operations = {
	.open		= davinci_ck_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init davinci_clk_debugfs_init(void)
{
	debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL,
						&davinci_ck_operations);
	return 0;

}
device_initcall(davinci_clk_debugfs_init);
#endif /* CONFIG_DEBUG_FS */
Commit	Line	Data
3e062b07	1	/*
c5b736d0	2	* Clock and PLL control for DaVinci devices
3e062b07	3	*
c5b736d0 KH	4	* Copyright (C) 2006-2007 Texas Instruments.
c5b736d0 KH	5	* Copyright (C) 2008-2009 Deep Root Systems, LLC
3e062b07 VB	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
	12
	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/errno.h>
c5b736d0	17	#include <linux/clk.h>
3e062b07 VB	18	#include <linux/err.h>
3e062b07 VB	19	#include <linux/mutex.h>
fced80c7	20	#include <linux/io.h>
d6a61563	21	#include <linux/delay.h>
3e062b07	22
a09e64fb	23	#include <mach/hardware.h>
3e062b07	24
28552c2e	25	#include <mach/clock.h>
3acf731c	26	#include "psc.h"
c5b736d0	27	#include <mach/cputype.h>
3e062b07 VB	28	#include "clock.h"
3e062b07 VB	29
3e062b07 VB	30	static LIST_HEAD(clocks);
	31	static DEFINE_MUTEX(clocks_mutex);
	32	static DEFINE_SPINLOCK(clockfw_lock);
	33
48cd30b4	34	void davinci_clk_enable(struct clk *clk)
3e062b07	35	{
c5b736d0	36	if (clk->parent)
48cd30b4	37	davinci_clk_enable(clk->parent);
c6007ffe PA	38	if (clk->usecount++ == 0) {
	39	if (clk->flags & CLK_PSC)
	40	davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
	41	true, clk->flags);
	42	else if (clk->clk_enable)
	43	clk->clk_enable(clk);
	44	}
3e062b07 VB	45	}
3e062b07 VB	46
48cd30b4	47	void davinci_clk_disable(struct clk *clk)
3e062b07	48	{
c5b736d0	49	if (WARN_ON(clk->usecount == 0))
3e062b07	50	return;
c6007ffe PA	51	if (--clk->usecount == 0) {
	52	if (!(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC))
	53	davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
	54	false, clk->flags);
	55	else if (clk->clk_disable)
	56	clk->clk_disable(clk);
	57	}
c5b736d0	58	if (clk->parent)
48cd30b4	59	davinci_clk_disable(clk->parent);
3e062b07 VB	60	}
3e062b07 VB	61
af47e6bb RT	62	int davinci_clk_reset(struct clk *clk, bool reset)
	63	{
	64	unsigned long flags;
	65
	66	if (clk == NULL \|\| IS_ERR(clk))
	67	return -EINVAL;
	68
	69	spin_lock_irqsave(&clockfw_lock, flags);
	70	if (clk->flags & CLK_PSC)
	71	davinci_psc_reset(clk->gpsc, clk->lpsc, reset);
	72	spin_unlock_irqrestore(&clockfw_lock, flags);
	73
	74	return 0;
	75	}
	76	EXPORT_SYMBOL(davinci_clk_reset);
	77
	78	int davinci_clk_reset_assert(struct clk *clk)
	79	{
	80	if (clk == NULL \|\| IS_ERR(clk) \|\| !clk->reset)
	81	return -EINVAL;
	82
	83	return clk->reset(clk, true);
	84	}
	85	EXPORT_SYMBOL(davinci_clk_reset_assert);
	86
	87	int davinci_clk_reset_deassert(struct clk *clk)
	88	{
	89	if (clk == NULL \|\| IS_ERR(clk) \|\| !clk->reset)
	90	return -EINVAL;
	91
	92	return clk->reset(clk, false);
	93	}
	94	EXPORT_SYMBOL(davinci_clk_reset_deassert);
	95
3e062b07 VB	96	int clk_enable(struct clk *clk)
	97	{
	98	unsigned long flags;
3e062b07	99
f6c1a8a6 PU	100	if (!clk)
	101	return 0;
	102	else if (IS_ERR(clk))
3e062b07 VB	103	return -EINVAL;
3e062b07 VB	104
c5b736d0	105	spin_lock_irqsave(&clockfw_lock, flags);
48cd30b4	106	davinci_clk_enable(clk);
c5b736d0	107	spin_unlock_irqrestore(&clockfw_lock, flags);
3e062b07	108
c5b736d0	109	return 0;
3e062b07 VB	110	}
	111	EXPORT_SYMBOL(clk_enable);
	112
	113	void clk_disable(struct clk *clk)
	114	{
	115	unsigned long flags;
	116
	117	if (clk == NULL \|\| IS_ERR(clk))
	118	return;
	119
c5b736d0	120	spin_lock_irqsave(&clockfw_lock, flags);
48cd30b4	121	davinci_clk_disable(clk);
c5b736d0	122	spin_unlock_irqrestore(&clockfw_lock, flags);
3e062b07 VB	123	}
	124	EXPORT_SYMBOL(clk_disable);
	125
	126	unsigned long clk_get_rate(struct clk *clk)
	127	{
	128	if (clk == NULL \|\| IS_ERR(clk))
f6c1a8a6	129	return 0;
3e062b07	130
c5b736d0	131	return clk->rate;
3e062b07 VB	132	}
	133	EXPORT_SYMBOL(clk_get_rate);
	134
	135	long clk_round_rate(struct clk *clk, unsigned long rate)
	136	{
	137	if (clk == NULL \|\| IS_ERR(clk))
4408c26b	138	return 0;
3e062b07	139
d6a61563 SN	140	if (clk->round_rate)
	141	return clk->round_rate(clk, rate);
	142
c5b736d0	143	return clk->rate;
3e062b07 VB	144	}
	145	EXPORT_SYMBOL(clk_round_rate);
	146
d6a61563 SN	147	/* Propagate rate to children */
	148	static void propagate_rate(struct clk *root)
	149	{
	150	struct clk *clk;
	151
	152	list_for_each_entry(clk, &root->children, childnode) {
	153	if (clk->recalc)
	154	clk->rate = clk->recalc(clk);
	155	propagate_rate(clk);
	156	}
	157	}
	158
3e062b07 VB	159	int clk_set_rate(struct clk *clk, unsigned long rate)
3e062b07 VB	160	{
d6a61563 SN	161	unsigned long flags;
	162	int ret = -EINVAL;
	163
f6c1a8a6 PU	164	if (!clk)
	165	return 0;
	166	else if (IS_ERR(clk))
	167	return -EINVAL;
d6a61563	168
d6a61563 SN	169	if (clk->set_rate)
d6a61563 SN	170	ret = clk->set_rate(clk, rate);
3b43cd6f SN	171
3b43cd6f SN	172	spin_lock_irqsave(&clockfw_lock, flags);
d6a61563 SN	173	if (ret == 0) {
	174	if (clk->recalc)
	175	clk->rate = clk->recalc(clk);
	176	propagate_rate(clk);
	177	}
	178	spin_unlock_irqrestore(&clockfw_lock, flags);
3e062b07	179
d6a61563	180	return ret;
3e062b07 VB	181	}
	182	EXPORT_SYMBOL(clk_set_rate);
	183
b82a51e8 SN	184	int clk_set_parent(struct clk clk, struct clk parent)
	185	{
	186	unsigned long flags;
	187
f6c1a8a6 PU	188	if (!clk)
	189	return 0;
	190	else if (IS_ERR(clk))
b82a51e8 SN	191	return -EINVAL;
	192
	193	/* Cannot change parent on enabled clock */
	194	if (WARN_ON(clk->usecount))
	195	return -EINVAL;
	196
	197	mutex_lock(&clocks_mutex);
8a9d088f DL	198	if (clk->set_parent) {
	199	int ret = clk->set_parent(clk, parent);
	200
	201	if (ret) {
	202	mutex_unlock(&clocks_mutex);
	203	return ret;
	204	}
	205	}
b82a51e8 SN	206	clk->parent = parent;
	207	list_del_init(&clk->childnode);
	208	list_add(&clk->childnode, &clk->parent->children);
	209	mutex_unlock(&clocks_mutex);
	210
	211	spin_lock_irqsave(&clockfw_lock, flags);
	212	if (clk->recalc)
	213	clk->rate = clk->recalc(clk);
	214	propagate_rate(clk);
	215	spin_unlock_irqrestore(&clockfw_lock, flags);
	216
	217	return 0;
	218	}
	219	EXPORT_SYMBOL(clk_set_parent);
	220
31d5cf14 AB	221	struct clk clk_get_parent(struct clk clk)
	222	{
	223	if (!clk)
	224	return NULL;
	225
	226	return clk->parent;
	227	}
	228	EXPORT_SYMBOL(clk_get_parent);
	229
3e062b07 VB	230	int clk_register(struct clk *clk)
	231	{
	232	if (clk == NULL \|\| IS_ERR(clk))
	233	return -EINVAL;
	234
c5b736d0 KH	235	if (WARN(clk->parent && !clk->parent->rate,
	236	"CLK: %s parent %s has no rate!\n",
	237	clk->name, clk->parent->name))
	238	return -EINVAL;
	239
f02bf3b3 SN	240	INIT_LIST_HEAD(&clk->children);
f02bf3b3 SN	241
3e062b07	242	mutex_lock(&clocks_mutex);
c5b736d0	243	list_add_tail(&clk->node, &clocks);
8a9d088f DL	244	if (clk->parent) {
	245	if (clk->set_parent) {
	246	int ret = clk->set_parent(clk, clk->parent);
	247
	248	if (ret) {
	249	mutex_unlock(&clocks_mutex);
	250	return ret;
	251	}
	252	}
f02bf3b3	253	list_add_tail(&clk->childnode, &clk->parent->children);
8a9d088f	254	}
3e062b07 VB	255	mutex_unlock(&clocks_mutex);
3e062b07 VB	256
c5b736d0 KH	257	/* If rate is already set, use it */
	258	if (clk->rate)
	259	return 0;
	260
de381a91 SN	261	/* Else, see if there is a way to calculate it */
	262	if (clk->recalc)
	263	clk->rate = clk->recalc(clk);
	264
c5b736d0	265	/* Otherwise, default to parent rate */
de381a91	266	else if (clk->parent)
c5b736d0 KH	267	clk->rate = clk->parent->rate;
c5b736d0 KH	268
3e062b07 VB	269	return 0;
	270	}
	271	EXPORT_SYMBOL(clk_register);
	272
	273	void clk_unregister(struct clk *clk)
	274	{
	275	if (clk == NULL \|\| IS_ERR(clk))
	276	return;
	277
	278	mutex_lock(&clocks_mutex);
	279	list_del(&clk->node);
f02bf3b3	280	list_del(&clk->childnode);
3e062b07 VB	281	mutex_unlock(&clocks_mutex);
	282	}
	283	EXPORT_SYMBOL(clk_unregister);
	284
c5b736d0 KH	285	#ifdef CONFIG_DAVINCI_RESET_CLOCKS
	286	/*
	287	* Disable any unused clocks left on by the bootloader
	288	*/
3aa3e840	289	int __init davinci_clk_disable_unused(void)
c5b736d0 KH	290	{
	291	struct clk *ck;
	292
	293	spin_lock_irq(&clockfw_lock);
	294	list_for_each_entry(ck, &clocks, node) {
	295	if (ck->usecount > 0)
	296	continue;
	297	if (!(ck->flags & CLK_PSC))
	298	continue;
	299
	300	/* ignore if in Disabled or SwRstDisable states */
789a785e	301	if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc))
c5b736d0 KH	302	continue;
c5b736d0 KH	303
c89f1681	304	pr_debug("Clocks: disable unused %s\n", ck->name);
52958be3	305
12221d43	306	davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc,
a51ca38b	307	false, ck->flags);
3e062b07	308	}
c5b736d0 KH	309	spin_unlock_irq(&clockfw_lock);
	310
	311	return 0;
	312	}
c5b736d0	313	#endif
3e062b07	314
de381a91	315	static unsigned long clk_sysclk_recalc(struct clk *clk)
3e062b07	316	{
c5b736d0 KH	317	u32 v, plldiv;
c5b736d0 KH	318	struct pll_data *pll;
de381a91	319	unsigned long rate = clk->rate;
c5b736d0 KH	320
	321	/* If this is the PLL base clock, no more calculations needed */
	322	if (clk->pll_data)
de381a91	323	return rate;
c5b736d0 KH	324
c5b736d0 KH	325	if (WARN_ON(!clk->parent))
de381a91	326	return rate;
c5b736d0	327
de381a91	328	rate = clk->parent->rate;
c5b736d0 KH	329
	330	/* Otherwise, the parent must be a PLL */
	331	if (WARN_ON(!clk->parent->pll_data))
de381a91	332	return rate;
c5b736d0 KH	333
	334	pll = clk->parent->pll_data;
	335
	336	/* If pre-PLL, source clock is before the multiplier and divider(s) */
	337	if (clk->flags & PRE_PLL)
de381a91	338	rate = pll->input_rate;
c5b736d0 KH	339
c5b736d0 KH	340	if (!clk->div_reg)
de381a91	341	return rate;
c5b736d0 KH	342
	343	v = __raw_readl(pll->base + clk->div_reg);
	344	if (v & PLLDIV_EN) {
d6961e68	345	plldiv = (v & pll->div_ratio_mask) + 1;
c5b736d0	346	if (plldiv)
de381a91	347	rate /= plldiv;
c5b736d0	348	}
de381a91 SN	349
	350	return rate;
	351	}
	352
b39639b8 SN	353	int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
	354	{
	355	unsigned v;
	356	struct pll_data *pll;
	357	unsigned long input;
	358	unsigned ratio = 0;
	359
	360	/* If this is the PLL base clock, wrong function to call */
	361	if (clk->pll_data)
	362	return -EINVAL;
	363
	364	/* There must be a parent... */
	365	if (WARN_ON(!clk->parent))
	366	return -EINVAL;
	367
	368	/* ... the parent must be a PLL... */
	369	if (WARN_ON(!clk->parent->pll_data))
	370	return -EINVAL;
	371
	372	/* ... and this clock must have a divider. */
	373	if (WARN_ON(!clk->div_reg))
	374	return -EINVAL;
	375
	376	pll = clk->parent->pll_data;
	377
	378	input = clk->parent->rate;
	379
	380	/* If pre-PLL, source clock is before the multiplier and divider(s) */
	381	if (clk->flags & PRE_PLL)
	382	input = pll->input_rate;
	383
	384	if (input > rate) {
	385	/*
	386	* Can afford to provide an output little higher than requested
	387	* only if maximum rate supported by hardware on this sysclk
	388	* is known.
	389	*/
	390	if (clk->maxrate) {
	391	ratio = DIV_ROUND_CLOSEST(input, rate);
	392	if (input / ratio > clk->maxrate)
	393	ratio = 0;
	394	}
	395
	396	if (ratio == 0)
	397	ratio = DIV_ROUND_UP(input, rate);
	398
	399	ratio--;
	400	}
	401
b1d05be6	402	if (ratio > pll->div_ratio_mask)
b39639b8 SN	403	return -EINVAL;
	404
	405	do {
	406	v = __raw_readl(pll->base + PLLSTAT);
	407	} while (v & PLLSTAT_GOSTAT);
	408
	409	v = __raw_readl(pll->base + clk->div_reg);
b1d05be6	410	v &= ~pll->div_ratio_mask;
b39639b8 SN	411	v \|= ratio \| PLLDIV_EN;
	412	__raw_writel(v, pll->base + clk->div_reg);
	413
	414	v = __raw_readl(pll->base + PLLCMD);
	415	v \|= PLLCMD_GOSET;
	416	__raw_writel(v, pll->base + PLLCMD);
	417
	418	do {
	419	v = __raw_readl(pll->base + PLLSTAT);
	420	} while (v & PLLSTAT_GOSTAT);
	421
	422	return 0;
	423	}
	424	EXPORT_SYMBOL(davinci_set_sysclk_rate);
	425
de381a91 SN	426	static unsigned long clk_leafclk_recalc(struct clk *clk)
	427	{
	428	if (WARN_ON(!clk->parent))
	429	return clk->rate;
	430
	431	return clk->parent->rate;
c5b736d0 KH	432	}
c5b736d0 KH	433
56e580d7 SN	434	int davinci_simple_set_rate(struct clk *clk, unsigned long rate)
	435	{
	436	clk->rate = rate;
	437	return 0;
	438	}
	439
de381a91	440	static unsigned long clk_pllclk_recalc(struct clk *clk)
c5b736d0 KH	441	{
	442	u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
	443	u8 bypass;
	444	struct pll_data *pll = clk->pll_data;
de381a91	445	unsigned long rate = clk->rate;
c5b736d0	446
c5b736d0	447	ctrl = __raw_readl(pll->base + PLLCTL);
de381a91	448	rate = pll->input_rate = clk->parent->rate;
c5b736d0 KH	449
	450	if (ctrl & PLLCTL_PLLEN) {
	451	bypass = 0;
	452	mult = __raw_readl(pll->base + PLLM);
fb8fcb89 SP	453	if (cpu_is_davinci_dm365())
	454	mult = 2 * (mult & PLLM_PLLM_MASK);
	455	else
	456	mult = (mult & PLLM_PLLM_MASK) + 1;
c5b736d0 KH	457	} else
	458	bypass = 1;
	459
	460	if (pll->flags & PLL_HAS_PREDIV) {
	461	prediv = __raw_readl(pll->base + PREDIV);
	462	if (prediv & PLLDIV_EN)
d6961e68	463	prediv = (prediv & pll->div_ratio_mask) + 1;
c5b736d0 KH	464	else
	465	prediv = 1;
	466	}
	467
	468	/* pre-divider is fixed, but (some?) chips won't report that */
	469	if (cpu_is_davinci_dm355() && pll->num == 1)
	470	prediv = 8;
	471
	472	if (pll->flags & PLL_HAS_POSTDIV) {
	473	postdiv = __raw_readl(pll->base + POSTDIV);
	474	if (postdiv & PLLDIV_EN)
d6961e68	475	postdiv = (postdiv & pll->div_ratio_mask) + 1;
c5b736d0 KH	476	else
	477	postdiv = 1;
	478	}
	479
	480	if (!bypass) {
de381a91 SN	481	rate /= prediv;
	482	rate *= mult;
	483	rate /= postdiv;
c5b736d0 KH	484	}
	485
	486	pr_debug("PLL%d: input = %lu MHz [ ",
	487	pll->num, clk->parent->rate / 1000000);
	488	if (bypass)
	489	pr_debug("bypass ");
	490	if (prediv > 1)
	491	pr_debug("/ %d ", prediv);
	492	if (mult > 1)
	493	pr_debug("* %d ", mult);
	494	if (postdiv > 1)
	495	pr_debug("/ %d ", postdiv);
de381a91 SN	496	pr_debug("] --> %lu MHz output.\n", rate / 1000000);
	497
	498	return rate;
c5b736d0 KH	499	}
c5b736d0 KH	500
d6a61563 SN	501	/**
	502	* davinci_set_pllrate - set the output rate of a given PLL.
	503	*
	504	* Note: Currently tested to work with OMAP-L138 only.
	505	*
	506	* @pll: pll whose rate needs to be changed.
	507	* @prediv: The pre divider value. Passing 0 disables the pre-divider.
	508	* @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
	509	* @postdiv: The post divider value. Passing 0 disables the post-divider.
	510	*/
	511	int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
	512	unsigned int mult, unsigned int postdiv)
	513	{
	514	u32 ctrl;
	515	unsigned int locktime;
3b43cd6f	516	unsigned long flags;
d6a61563 SN	517
	518	if (pll->base == NULL)
	519	return -EINVAL;
	520
	521	/*
	522	* PLL lock time required per OMAP-L138 datasheet is
	523	* (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
	524	* as 4 and OSCIN cycle as 25 MHz.
	525	*/
	526	if (prediv) {
	527	locktime = ((2000 * prediv) / 100);
	528	prediv = (prediv - 1) \| PLLDIV_EN;
	529	} else {
9a219a9e	530	locktime = PLL_LOCK_TIME;
d6a61563 SN	531	}
	532	if (postdiv)
	533	postdiv = (postdiv - 1) \| PLLDIV_EN;
	534	if (mult)
	535	mult = mult - 1;
	536
3b43cd6f SN	537	/* Protect against simultaneous calls to PLL setting seqeunce */
	538	spin_lock_irqsave(&clockfw_lock, flags);
	539
d6a61563 SN	540	ctrl = __raw_readl(pll->base + PLLCTL);
	541
	542	/* Switch the PLL to bypass mode */
	543	ctrl &= ~(PLLCTL_PLLENSRC \| PLLCTL_PLLEN);
	544	__raw_writel(ctrl, pll->base + PLLCTL);
	545
9a219a9e	546	udelay(PLL_BYPASS_TIME);
d6a61563 SN	547
	548	/* Reset and enable PLL */
	549	ctrl &= ~(PLLCTL_PLLRST \| PLLCTL_PLLDIS);
	550	__raw_writel(ctrl, pll->base + PLLCTL);
	551
	552	if (pll->flags & PLL_HAS_PREDIV)
	553	__raw_writel(prediv, pll->base + PREDIV);
	554
	555	__raw_writel(mult, pll->base + PLLM);
	556
	557	if (pll->flags & PLL_HAS_POSTDIV)
	558	__raw_writel(postdiv, pll->base + POSTDIV);
	559
9a219a9e	560	udelay(PLL_RESET_TIME);
d6a61563 SN	561
	562	/* Bring PLL out of reset */
	563	ctrl \|= PLLCTL_PLLRST;
	564	__raw_writel(ctrl, pll->base + PLLCTL);
	565
	566	udelay(locktime);
	567
	568	/* Remove PLL from bypass mode */
	569	ctrl \|= PLLCTL_PLLEN;
	570	__raw_writel(ctrl, pll->base + PLLCTL);
	571
3b43cd6f SN	572	spin_unlock_irqrestore(&clockfw_lock, flags);
3b43cd6f SN	573
d6a61563 SN	574	return 0;
	575	}
	576	EXPORT_SYMBOL(davinci_set_pllrate);
	577
56e580d7 SN	578	/**
	579	* davinci_set_refclk_rate() - Set the reference clock rate
	580	* @rate: The new rate.
	581	*
	582	* Sets the reference clock rate to a given value. This will most likely
	583	* result in the entire clock tree getting updated.
	584	*
	585	* This is used to support boards which use a reference clock different
	586	* than that used by default in <soc>.c file. The reference clock rate
	587	* should be updated early in the boot process; ideally soon after the
	588	* clock tree has been initialized once with the default reference clock
6fc9ebbd	589	* rate (davinci_clk_init()).
56e580d7 SN	590	*
	591	* Returns 0 on success, error otherwise.
	592	*/
	593	int davinci_set_refclk_rate(unsigned long rate)
	594	{
	595	struct clk *refclk;
	596
	597	refclk = clk_get(NULL, "ref");
	598	if (IS_ERR(refclk)) {
a7ca2bcf	599	pr_err("%s: failed to get reference clock\n", __func__);
56e580d7 SN	600	return PTR_ERR(refclk);
	601	}
	602
	603	clk_set_rate(refclk, rate);
	604
	605	clk_put(refclk);
	606
	607	return 0;
	608	}
	609
08aca087	610	int __init davinci_clk_init(struct clk_lookup *clocks)
af47e6bb	611	{
08aca087	612	struct clk_lookup *c;
c5b736d0	613	struct clk *clk;
08aca087	614	size_t num_clocks = 0;
c5b736d0	615
08aca087 KH	616	for (c = clocks; c->clk; c++) {
08aca087 KH	617	clk = c->clk;
c5b736d0	618
de381a91 SN	619	if (!clk->recalc) {
	620
	621	/* Check if clock is a PLL */
	622	if (clk->pll_data)
	623	clk->recalc = clk_pllclk_recalc;
	624
	625	/* Else, if it is a PLL-derived clock */
	626	else if (clk->flags & CLK_PLL)
	627	clk->recalc = clk_sysclk_recalc;
	628
	629	/* Otherwise, it is a leaf clock (PSC clock) */
	630	else if (clk->parent)
	631	clk->recalc = clk_leafclk_recalc;
	632	}
c5b736d0	633
e4c822c7 CC	634	if (clk->pll_data) {
	635	struct pll_data *pll = clk->pll_data;
	636
	637	if (!pll->div_ratio_mask)
	638	pll->div_ratio_mask = PLLDIV_RATIO_MASK;
	639
	640	if (pll->phys_base && !pll->base) {
	641	pll->base = ioremap(pll->phys_base, SZ_4K);
	642	WARN_ON(!pll->base);
	643	}
	644	}
d6961e68	645
de381a91 SN	646	if (clk->recalc)
de381a91 SN	647	clk->rate = clk->recalc(clk);
c5b736d0 KH	648
	649	if (clk->lpsc)
	650	clk->flags \|= CLK_PSC;
	651
af47e6bb RT	652	if (clk->flags & PSC_LRST)
	653	clk->reset = davinci_clk_reset;
	654
c5b736d0	655	clk_register(clk);
08aca087	656	num_clocks++;
c5b736d0 KH	657
	658	/* Turn on clocks that Linux doesn't otherwise manage */
	659	if (clk->flags & ALWAYS_ENABLED)
	660	clk_enable(clk);
3e062b07 VB	661	}
3e062b07 VB	662
08aca087 KH	663	clkdev_add_table(clocks, num_clocks);
08aca087 KH	664
3e062b07 VB	665	return 0;
	666	}
	667
2f72e8dc	668	#ifdef CONFIG_DEBUG_FS
3e062b07	669
2f72e8dc SN	670	#include <linux/debugfs.h>
2f72e8dc SN	671	#include <linux/seq_file.h>
3e062b07	672
c5b736d0 KH	673	#define CLKNAME_MAX 10 /* longest clock name */
	674	#define NEST_DELTA 2
	675	#define NEST_MAX 4
	676
	677	static void
	678	dump_clock(struct seq_file s, unsigned nest, struct clk parent)
3e062b07	679	{
c5b736d0 KH	680	char *state;
	681	char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
	682	struct clk *clk;
	683	unsigned i;
	684
	685	if (parent->flags & CLK_PLL)
	686	state = "pll";
	687	else if (parent->flags & CLK_PSC)
	688	state = "psc";
	689	else
	690	state = "";
	691
	692	/* <nest spaces> name <pad to end> */
	693	memset(buf, ' ', sizeof(buf) - 1);
	694	buf[sizeof(buf) - 1] = 0;
	695	i = strlen(parent->name);
	696	memcpy(buf + nest, parent->name,
	697	min(i, (unsigned)(sizeof(buf) - 1 - nest)));
	698
	699	seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
	700	buf, parent->usecount, state, clk_get_rate(parent));
	701	/* REVISIT show device associations too */
	702
	703	/* cost is now small, but not linear... */
f02bf3b3 SN	704	list_for_each_entry(clk, &parent->children, childnode) {
f02bf3b3 SN	705	dump_clock(s, nest + NEST_DELTA, clk);
c5b736d0 KH	706	}
c5b736d0 KH	707	}
3e062b07	708
c5b736d0 KH	709	static int davinci_ck_show(struct seq_file m, void v)
c5b736d0 KH	710	{
f979aa6e SN	711	struct clk *clk;
	712
	713	/*
	714	* Show clock tree; We trust nonzero usecounts equate to PSC enables...
c5b736d0 KH	715	*/
c5b736d0 KH	716	mutex_lock(&clocks_mutex);
f979aa6e SN	717	list_for_each_entry(clk, &clocks, node)
	718	if (!clk->parent)
	719	dump_clock(m, 0, clk);
c5b736d0	720	mutex_unlock(&clocks_mutex);
3e062b07 VB	721
	722	return 0;
	723	}
	724
3e062b07 VB	725	static int davinci_ck_open(struct inode inode, struct file file)
3e062b07 VB	726	{
2f72e8dc	727	return single_open(file, davinci_ck_show, NULL);
3e062b07 VB	728	}
3e062b07 VB	729
2f72e8dc	730	static const struct file_operations davinci_ck_operations = {
3e062b07 VB	731	.open = davinci_ck_open,
	732	.read = seq_read,
	733	.llseek = seq_lseek,
2f72e8dc	734	.release = single_release,
3e062b07 VB	735	};
3e062b07 VB	736
2f72e8dc	737	static int __init davinci_clk_debugfs_init(void)
3e062b07	738	{
2f72e8dc SN	739	debugfs_create_file("davinci_clocks", S_IFREG \| S_IRUGO, NULL, NULL,
2f72e8dc SN	740	&davinci_ck_operations);
3e062b07 VB	741	return 0;
	742
	743	}
2f72e8dc SN	744	device_initcall(davinci_clk_debugfs_init);
2f72e8dc SN	745	#endif /* CONFIG_DEBUG_FS */