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e1a8d7e2 SR |
1 | /* |
2 | * TI DA850/OMAP-L138 chip specific setup | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * Derived from: arch/arm/mach-davinci/da830.c | |
7 | * Original Copyrights follow: | |
8 | * | |
9 | * 2009 (c) MontaVista Software, Inc. This file is licensed under | |
10 | * the terms of the GNU General Public License version 2. This program | |
11 | * is licensed "as is" without any warranty of any kind, whether express | |
12 | * or implied. | |
13 | */ | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/clk.h> | |
17 | #include <linux/platform_device.h> | |
18 | ||
19 | #include <asm/mach/map.h> | |
20 | ||
21 | #include <mach/clock.h> | |
22 | #include <mach/psc.h> | |
23 | #include <mach/mux.h> | |
24 | #include <mach/irqs.h> | |
25 | #include <mach/cputype.h> | |
26 | #include <mach/common.h> | |
27 | #include <mach/time.h> | |
28 | #include <mach/da8xx.h> | |
29 | ||
30 | #include "clock.h" | |
31 | #include "mux.h" | |
32 | ||
33 | #define DA850_PLL1_BASE 0x01e1a000 | |
34 | #define DA850_TIMER64P2_BASE 0x01f0c000 | |
35 | #define DA850_TIMER64P3_BASE 0x01f0d000 | |
36 | ||
37 | #define DA850_REF_FREQ 24000000 | |
38 | ||
39 | static struct pll_data pll0_data = { | |
40 | .num = 1, | |
41 | .phys_base = DA8XX_PLL0_BASE, | |
42 | .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV, | |
43 | }; | |
44 | ||
45 | static struct clk ref_clk = { | |
46 | .name = "ref_clk", | |
47 | .rate = DA850_REF_FREQ, | |
48 | }; | |
49 | ||
50 | static struct clk pll0_clk = { | |
51 | .name = "pll0", | |
52 | .parent = &ref_clk, | |
53 | .pll_data = &pll0_data, | |
54 | .flags = CLK_PLL, | |
55 | }; | |
56 | ||
57 | static struct clk pll0_aux_clk = { | |
58 | .name = "pll0_aux_clk", | |
59 | .parent = &pll0_clk, | |
60 | .flags = CLK_PLL | PRE_PLL, | |
61 | }; | |
62 | ||
63 | static struct clk pll0_sysclk2 = { | |
64 | .name = "pll0_sysclk2", | |
65 | .parent = &pll0_clk, | |
66 | .flags = CLK_PLL, | |
67 | .div_reg = PLLDIV2, | |
68 | }; | |
69 | ||
70 | static struct clk pll0_sysclk3 = { | |
71 | .name = "pll0_sysclk3", | |
72 | .parent = &pll0_clk, | |
73 | .flags = CLK_PLL, | |
74 | .div_reg = PLLDIV3, | |
75 | }; | |
76 | ||
77 | static struct clk pll0_sysclk4 = { | |
78 | .name = "pll0_sysclk4", | |
79 | .parent = &pll0_clk, | |
80 | .flags = CLK_PLL, | |
81 | .div_reg = PLLDIV4, | |
82 | }; | |
83 | ||
84 | static struct clk pll0_sysclk5 = { | |
85 | .name = "pll0_sysclk5", | |
86 | .parent = &pll0_clk, | |
87 | .flags = CLK_PLL, | |
88 | .div_reg = PLLDIV5, | |
89 | }; | |
90 | ||
91 | static struct clk pll0_sysclk6 = { | |
92 | .name = "pll0_sysclk6", | |
93 | .parent = &pll0_clk, | |
94 | .flags = CLK_PLL, | |
95 | .div_reg = PLLDIV6, | |
96 | }; | |
97 | ||
98 | static struct clk pll0_sysclk7 = { | |
99 | .name = "pll0_sysclk7", | |
100 | .parent = &pll0_clk, | |
101 | .flags = CLK_PLL, | |
102 | .div_reg = PLLDIV7, | |
103 | }; | |
104 | ||
105 | static struct pll_data pll1_data = { | |
106 | .num = 2, | |
107 | .phys_base = DA850_PLL1_BASE, | |
108 | .flags = PLL_HAS_POSTDIV, | |
109 | }; | |
110 | ||
111 | static struct clk pll1_clk = { | |
112 | .name = "pll1", | |
113 | .parent = &ref_clk, | |
114 | .pll_data = &pll1_data, | |
115 | .flags = CLK_PLL, | |
116 | }; | |
117 | ||
118 | static struct clk pll1_aux_clk = { | |
119 | .name = "pll1_aux_clk", | |
120 | .parent = &pll1_clk, | |
121 | .flags = CLK_PLL | PRE_PLL, | |
122 | }; | |
123 | ||
124 | static struct clk pll1_sysclk2 = { | |
125 | .name = "pll1_sysclk2", | |
126 | .parent = &pll1_clk, | |
127 | .flags = CLK_PLL, | |
128 | .div_reg = PLLDIV2, | |
129 | }; | |
130 | ||
131 | static struct clk pll1_sysclk3 = { | |
132 | .name = "pll1_sysclk3", | |
133 | .parent = &pll1_clk, | |
134 | .flags = CLK_PLL, | |
135 | .div_reg = PLLDIV3, | |
136 | }; | |
137 | ||
138 | static struct clk pll1_sysclk4 = { | |
139 | .name = "pll1_sysclk4", | |
140 | .parent = &pll1_clk, | |
141 | .flags = CLK_PLL, | |
142 | .div_reg = PLLDIV4, | |
143 | }; | |
144 | ||
145 | static struct clk pll1_sysclk5 = { | |
146 | .name = "pll1_sysclk5", | |
147 | .parent = &pll1_clk, | |
148 | .flags = CLK_PLL, | |
149 | .div_reg = PLLDIV5, | |
150 | }; | |
151 | ||
152 | static struct clk pll1_sysclk6 = { | |
153 | .name = "pll0_sysclk6", | |
154 | .parent = &pll0_clk, | |
155 | .flags = CLK_PLL, | |
156 | .div_reg = PLLDIV6, | |
157 | }; | |
158 | ||
159 | static struct clk pll1_sysclk7 = { | |
160 | .name = "pll1_sysclk7", | |
161 | .parent = &pll1_clk, | |
162 | .flags = CLK_PLL, | |
163 | .div_reg = PLLDIV7, | |
164 | }; | |
165 | ||
166 | static struct clk i2c0_clk = { | |
167 | .name = "i2c0", | |
168 | .parent = &pll0_aux_clk, | |
169 | }; | |
170 | ||
171 | static struct clk timerp64_0_clk = { | |
172 | .name = "timer0", | |
173 | .parent = &pll0_aux_clk, | |
174 | }; | |
175 | ||
176 | static struct clk timerp64_1_clk = { | |
177 | .name = "timer1", | |
178 | .parent = &pll0_aux_clk, | |
179 | }; | |
180 | ||
181 | static struct clk arm_rom_clk = { | |
182 | .name = "arm_rom", | |
183 | .parent = &pll0_sysclk2, | |
184 | .lpsc = DA8XX_LPSC0_ARM_RAM_ROM, | |
185 | .flags = ALWAYS_ENABLED, | |
186 | }; | |
187 | ||
188 | static struct clk tpcc0_clk = { | |
189 | .name = "tpcc0", | |
190 | .parent = &pll0_sysclk2, | |
191 | .lpsc = DA8XX_LPSC0_TPCC, | |
192 | .flags = ALWAYS_ENABLED | CLK_PSC, | |
193 | }; | |
194 | ||
195 | static struct clk tptc0_clk = { | |
196 | .name = "tptc0", | |
197 | .parent = &pll0_sysclk2, | |
198 | .lpsc = DA8XX_LPSC0_TPTC0, | |
199 | .flags = ALWAYS_ENABLED, | |
200 | }; | |
201 | ||
202 | static struct clk tptc1_clk = { | |
203 | .name = "tptc1", | |
204 | .parent = &pll0_sysclk2, | |
205 | .lpsc = DA8XX_LPSC0_TPTC1, | |
206 | .flags = ALWAYS_ENABLED, | |
207 | }; | |
208 | ||
209 | static struct clk tpcc1_clk = { | |
210 | .name = "tpcc1", | |
211 | .parent = &pll0_sysclk2, | |
212 | .lpsc = DA850_LPSC1_TPCC1, | |
213 | .flags = CLK_PSC | ALWAYS_ENABLED, | |
214 | .psc_ctlr = 1, | |
215 | }; | |
216 | ||
217 | static struct clk tptc2_clk = { | |
218 | .name = "tptc2", | |
219 | .parent = &pll0_sysclk2, | |
220 | .lpsc = DA850_LPSC1_TPTC2, | |
221 | .flags = ALWAYS_ENABLED, | |
222 | .psc_ctlr = 1, | |
223 | }; | |
224 | ||
225 | static struct clk uart0_clk = { | |
226 | .name = "uart0", | |
227 | .parent = &pll0_sysclk2, | |
228 | .lpsc = DA8XX_LPSC0_UART0, | |
229 | }; | |
230 | ||
231 | static struct clk uart1_clk = { | |
232 | .name = "uart1", | |
233 | .parent = &pll0_sysclk2, | |
234 | .lpsc = DA8XX_LPSC1_UART1, | |
235 | .psc_ctlr = 1, | |
236 | }; | |
237 | ||
238 | static struct clk uart2_clk = { | |
239 | .name = "uart2", | |
240 | .parent = &pll0_sysclk2, | |
241 | .lpsc = DA8XX_LPSC1_UART2, | |
242 | .psc_ctlr = 1, | |
243 | }; | |
244 | ||
245 | static struct clk aintc_clk = { | |
246 | .name = "aintc", | |
247 | .parent = &pll0_sysclk4, | |
248 | .lpsc = DA8XX_LPSC0_AINTC, | |
249 | .flags = ALWAYS_ENABLED, | |
250 | }; | |
251 | ||
252 | static struct clk gpio_clk = { | |
253 | .name = "gpio", | |
254 | .parent = &pll0_sysclk4, | |
255 | .lpsc = DA8XX_LPSC1_GPIO, | |
256 | .psc_ctlr = 1, | |
257 | }; | |
258 | ||
259 | static struct clk i2c1_clk = { | |
260 | .name = "i2c1", | |
261 | .parent = &pll0_sysclk4, | |
262 | .lpsc = DA8XX_LPSC1_I2C, | |
263 | .psc_ctlr = 1, | |
264 | }; | |
265 | ||
266 | static struct clk emif3_clk = { | |
267 | .name = "emif3", | |
268 | .parent = &pll0_sysclk5, | |
269 | .lpsc = DA8XX_LPSC1_EMIF3C, | |
270 | .flags = ALWAYS_ENABLED, | |
271 | .psc_ctlr = 1, | |
272 | }; | |
273 | ||
274 | static struct clk arm_clk = { | |
275 | .name = "arm", | |
276 | .parent = &pll0_sysclk6, | |
277 | .lpsc = DA8XX_LPSC0_ARM, | |
278 | .flags = ALWAYS_ENABLED, | |
279 | }; | |
280 | ||
281 | static struct clk rmii_clk = { | |
282 | .name = "rmii", | |
283 | .parent = &pll0_sysclk7, | |
284 | }; | |
285 | ||
5a4b1315 SR |
286 | static struct clk emac_clk = { |
287 | .name = "emac", | |
288 | .parent = &pll0_sysclk4, | |
289 | .lpsc = DA8XX_LPSC1_CPGMAC, | |
53ca5c91 | 290 | .psc_ctlr = 1, |
5a4b1315 SR |
291 | }; |
292 | ||
e1a8d7e2 SR |
293 | static struct davinci_clk da850_clks[] = { |
294 | CLK(NULL, "ref", &ref_clk), | |
295 | CLK(NULL, "pll0", &pll0_clk), | |
296 | CLK(NULL, "pll0_aux", &pll0_aux_clk), | |
297 | CLK(NULL, "pll0_sysclk2", &pll0_sysclk2), | |
298 | CLK(NULL, "pll0_sysclk3", &pll0_sysclk3), | |
299 | CLK(NULL, "pll0_sysclk4", &pll0_sysclk4), | |
300 | CLK(NULL, "pll0_sysclk5", &pll0_sysclk5), | |
301 | CLK(NULL, "pll0_sysclk6", &pll0_sysclk6), | |
302 | CLK(NULL, "pll0_sysclk7", &pll0_sysclk7), | |
303 | CLK(NULL, "pll1", &pll1_clk), | |
304 | CLK(NULL, "pll1_aux", &pll1_aux_clk), | |
305 | CLK(NULL, "pll1_sysclk2", &pll1_sysclk2), | |
306 | CLK(NULL, "pll1_sysclk3", &pll1_sysclk3), | |
307 | CLK(NULL, "pll1_sysclk4", &pll1_sysclk4), | |
308 | CLK(NULL, "pll1_sysclk5", &pll1_sysclk5), | |
309 | CLK(NULL, "pll1_sysclk6", &pll1_sysclk6), | |
310 | CLK(NULL, "pll1_sysclk7", &pll1_sysclk7), | |
311 | CLK("i2c_davinci.1", NULL, &i2c0_clk), | |
312 | CLK(NULL, "timer0", &timerp64_0_clk), | |
313 | CLK("watchdog", NULL, &timerp64_1_clk), | |
314 | CLK(NULL, "arm_rom", &arm_rom_clk), | |
315 | CLK(NULL, "tpcc0", &tpcc0_clk), | |
316 | CLK(NULL, "tptc0", &tptc0_clk), | |
317 | CLK(NULL, "tptc1", &tptc1_clk), | |
318 | CLK(NULL, "tpcc1", &tpcc1_clk), | |
319 | CLK(NULL, "tptc2", &tptc2_clk), | |
320 | CLK(NULL, "uart0", &uart0_clk), | |
321 | CLK(NULL, "uart1", &uart1_clk), | |
322 | CLK(NULL, "uart2", &uart2_clk), | |
323 | CLK(NULL, "aintc", &aintc_clk), | |
324 | CLK(NULL, "gpio", &gpio_clk), | |
325 | CLK("i2c_davinci.2", NULL, &i2c1_clk), | |
326 | CLK(NULL, "emif3", &emif3_clk), | |
327 | CLK(NULL, "arm", &arm_clk), | |
328 | CLK(NULL, "rmii", &rmii_clk), | |
5a4b1315 | 329 | CLK("davinci_emac.1", NULL, &emac_clk), |
e1a8d7e2 SR |
330 | CLK(NULL, NULL, NULL), |
331 | }; | |
332 | ||
333 | /* | |
334 | * Device specific mux setup | |
335 | * | |
336 | * soc description mux mode mode mux dbg | |
337 | * reg offset mask mode | |
338 | */ | |
339 | static const struct mux_config da850_pins[] = { | |
340 | #ifdef CONFIG_DAVINCI_MUX | |
341 | /* UART0 function */ | |
342 | MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false) | |
343 | MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false) | |
344 | MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false) | |
345 | MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false) | |
346 | /* UART1 function */ | |
347 | MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false) | |
348 | MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false) | |
349 | /* UART2 function */ | |
350 | MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false) | |
351 | MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false) | |
352 | /* I2C1 function */ | |
353 | MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false) | |
354 | MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false) | |
355 | /* I2C0 function */ | |
356 | MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false) | |
357 | MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false) | |
5a4b1315 SR |
358 | /* EMAC function */ |
359 | MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false) | |
360 | MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false) | |
361 | MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false) | |
362 | MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false) | |
363 | MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false) | |
364 | MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false) | |
365 | MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false) | |
366 | MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false) | |
367 | MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false) | |
368 | MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false) | |
369 | MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false) | |
370 | MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false) | |
371 | MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false) | |
372 | MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false) | |
373 | MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false) | |
53ca5c91 SR |
374 | MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false) |
375 | MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false) | |
e1a8d7e2 SR |
376 | #endif |
377 | }; | |
378 | ||
379 | const short da850_uart0_pins[] __initdata = { | |
380 | DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD, | |
381 | -1 | |
382 | }; | |
383 | ||
384 | const short da850_uart1_pins[] __initdata = { | |
385 | DA850_UART1_RXD, DA850_UART1_TXD, | |
386 | -1 | |
387 | }; | |
388 | ||
389 | const short da850_uart2_pins[] __initdata = { | |
390 | DA850_UART2_RXD, DA850_UART2_TXD, | |
391 | -1 | |
392 | }; | |
393 | ||
394 | const short da850_i2c0_pins[] __initdata = { | |
395 | DA850_I2C0_SDA, DA850_I2C0_SCL, | |
396 | -1 | |
397 | }; | |
398 | ||
399 | const short da850_i2c1_pins[] __initdata = { | |
400 | DA850_I2C1_SCL, DA850_I2C1_SDA, | |
401 | -1 | |
402 | }; | |
403 | ||
5a4b1315 SR |
404 | const short da850_cpgmac_pins[] __initdata = { |
405 | DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, | |
406 | DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, | |
407 | DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, | |
53ca5c91 SR |
408 | DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, |
409 | DA850_MDIO_D, | |
5a4b1315 SR |
410 | -1 |
411 | }; | |
412 | ||
e1a8d7e2 SR |
413 | /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ |
414 | static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = { | |
415 | [IRQ_DA8XX_COMMTX] = 7, | |
416 | [IRQ_DA8XX_COMMRX] = 7, | |
417 | [IRQ_DA8XX_NINT] = 7, | |
418 | [IRQ_DA8XX_EVTOUT0] = 7, | |
419 | [IRQ_DA8XX_EVTOUT1] = 7, | |
420 | [IRQ_DA8XX_EVTOUT2] = 7, | |
421 | [IRQ_DA8XX_EVTOUT3] = 7, | |
422 | [IRQ_DA8XX_EVTOUT4] = 7, | |
423 | [IRQ_DA8XX_EVTOUT5] = 7, | |
424 | [IRQ_DA8XX_EVTOUT6] = 7, | |
425 | [IRQ_DA8XX_EVTOUT6] = 7, | |
426 | [IRQ_DA8XX_EVTOUT7] = 7, | |
427 | [IRQ_DA8XX_CCINT0] = 7, | |
428 | [IRQ_DA8XX_CCERRINT] = 7, | |
429 | [IRQ_DA8XX_TCERRINT0] = 7, | |
430 | [IRQ_DA8XX_AEMIFINT] = 7, | |
431 | [IRQ_DA8XX_I2CINT0] = 7, | |
432 | [IRQ_DA8XX_MMCSDINT0] = 7, | |
433 | [IRQ_DA8XX_MMCSDINT1] = 7, | |
434 | [IRQ_DA8XX_ALLINT0] = 7, | |
435 | [IRQ_DA8XX_RTC] = 7, | |
436 | [IRQ_DA8XX_SPINT0] = 7, | |
437 | [IRQ_DA8XX_TINT12_0] = 7, | |
438 | [IRQ_DA8XX_TINT34_0] = 7, | |
439 | [IRQ_DA8XX_TINT12_1] = 7, | |
440 | [IRQ_DA8XX_TINT34_1] = 7, | |
441 | [IRQ_DA8XX_UARTINT0] = 7, | |
442 | [IRQ_DA8XX_KEYMGRINT] = 7, | |
443 | [IRQ_DA8XX_SECINT] = 7, | |
444 | [IRQ_DA8XX_SECKEYERR] = 7, | |
445 | [IRQ_DA850_MPUADDRERR0] = 7, | |
446 | [IRQ_DA850_MPUPROTERR0] = 7, | |
447 | [IRQ_DA850_IOPUADDRERR0] = 7, | |
448 | [IRQ_DA850_IOPUPROTERR0] = 7, | |
449 | [IRQ_DA850_IOPUADDRERR1] = 7, | |
450 | [IRQ_DA850_IOPUPROTERR1] = 7, | |
451 | [IRQ_DA850_IOPUADDRERR2] = 7, | |
452 | [IRQ_DA850_IOPUPROTERR2] = 7, | |
453 | [IRQ_DA850_BOOTCFG_ADDR_ERR] = 7, | |
454 | [IRQ_DA850_BOOTCFG_PROT_ERR] = 7, | |
455 | [IRQ_DA850_MPUADDRERR1] = 7, | |
456 | [IRQ_DA850_MPUPROTERR1] = 7, | |
457 | [IRQ_DA850_IOPUADDRERR3] = 7, | |
458 | [IRQ_DA850_IOPUPROTERR3] = 7, | |
459 | [IRQ_DA850_IOPUADDRERR4] = 7, | |
460 | [IRQ_DA850_IOPUPROTERR4] = 7, | |
461 | [IRQ_DA850_IOPUADDRERR5] = 7, | |
462 | [IRQ_DA850_IOPUPROTERR5] = 7, | |
463 | [IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7, | |
464 | [IRQ_DA8XX_CHIPINT0] = 7, | |
465 | [IRQ_DA8XX_CHIPINT1] = 7, | |
466 | [IRQ_DA8XX_CHIPINT2] = 7, | |
467 | [IRQ_DA8XX_CHIPINT3] = 7, | |
468 | [IRQ_DA8XX_TCERRINT1] = 7, | |
469 | [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7, | |
470 | [IRQ_DA8XX_C0_RX_PULSE] = 7, | |
471 | [IRQ_DA8XX_C0_TX_PULSE] = 7, | |
472 | [IRQ_DA8XX_C0_MISC_PULSE] = 7, | |
473 | [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7, | |
474 | [IRQ_DA8XX_C1_RX_PULSE] = 7, | |
475 | [IRQ_DA8XX_C1_TX_PULSE] = 7, | |
476 | [IRQ_DA8XX_C1_MISC_PULSE] = 7, | |
477 | [IRQ_DA8XX_MEMERR] = 7, | |
478 | [IRQ_DA8XX_GPIO0] = 7, | |
479 | [IRQ_DA8XX_GPIO1] = 7, | |
480 | [IRQ_DA8XX_GPIO2] = 7, | |
481 | [IRQ_DA8XX_GPIO3] = 7, | |
482 | [IRQ_DA8XX_GPIO4] = 7, | |
483 | [IRQ_DA8XX_GPIO5] = 7, | |
484 | [IRQ_DA8XX_GPIO6] = 7, | |
485 | [IRQ_DA8XX_GPIO7] = 7, | |
486 | [IRQ_DA8XX_GPIO8] = 7, | |
487 | [IRQ_DA8XX_I2CINT1] = 7, | |
488 | [IRQ_DA8XX_LCDINT] = 7, | |
489 | [IRQ_DA8XX_UARTINT1] = 7, | |
490 | [IRQ_DA8XX_MCASPINT] = 7, | |
491 | [IRQ_DA8XX_ALLINT1] = 7, | |
492 | [IRQ_DA8XX_SPINT1] = 7, | |
493 | [IRQ_DA8XX_UHPI_INT1] = 7, | |
494 | [IRQ_DA8XX_USB_INT] = 7, | |
495 | [IRQ_DA8XX_IRQN] = 7, | |
496 | [IRQ_DA8XX_RWAKEUP] = 7, | |
497 | [IRQ_DA8XX_UARTINT2] = 7, | |
498 | [IRQ_DA8XX_DFTSSINT] = 7, | |
499 | [IRQ_DA8XX_EHRPWM0] = 7, | |
500 | [IRQ_DA8XX_EHRPWM0TZ] = 7, | |
501 | [IRQ_DA8XX_EHRPWM1] = 7, | |
502 | [IRQ_DA8XX_EHRPWM1TZ] = 7, | |
503 | [IRQ_DA850_SATAINT] = 7, | |
504 | [IRQ_DA850_TINT12_2] = 7, | |
505 | [IRQ_DA850_TINT34_2] = 7, | |
506 | [IRQ_DA850_TINTALL_2] = 7, | |
507 | [IRQ_DA8XX_ECAP0] = 7, | |
508 | [IRQ_DA8XX_ECAP1] = 7, | |
509 | [IRQ_DA8XX_ECAP2] = 7, | |
510 | [IRQ_DA850_MMCSDINT0_1] = 7, | |
511 | [IRQ_DA850_MMCSDINT1_1] = 7, | |
512 | [IRQ_DA850_T12CMPINT0_2] = 7, | |
513 | [IRQ_DA850_T12CMPINT1_2] = 7, | |
514 | [IRQ_DA850_T12CMPINT2_2] = 7, | |
515 | [IRQ_DA850_T12CMPINT3_2] = 7, | |
516 | [IRQ_DA850_T12CMPINT4_2] = 7, | |
517 | [IRQ_DA850_T12CMPINT5_2] = 7, | |
518 | [IRQ_DA850_T12CMPINT6_2] = 7, | |
519 | [IRQ_DA850_T12CMPINT7_2] = 7, | |
520 | [IRQ_DA850_T12CMPINT0_3] = 7, | |
521 | [IRQ_DA850_T12CMPINT1_3] = 7, | |
522 | [IRQ_DA850_T12CMPINT2_3] = 7, | |
523 | [IRQ_DA850_T12CMPINT3_3] = 7, | |
524 | [IRQ_DA850_T12CMPINT4_3] = 7, | |
525 | [IRQ_DA850_T12CMPINT5_3] = 7, | |
526 | [IRQ_DA850_T12CMPINT6_3] = 7, | |
527 | [IRQ_DA850_T12CMPINT7_3] = 7, | |
528 | [IRQ_DA850_RPIINT] = 7, | |
529 | [IRQ_DA850_VPIFINT] = 7, | |
530 | [IRQ_DA850_CCINT1] = 7, | |
531 | [IRQ_DA850_CCERRINT1] = 7, | |
532 | [IRQ_DA850_TCERRINT2] = 7, | |
533 | [IRQ_DA850_TINT12_3] = 7, | |
534 | [IRQ_DA850_TINT34_3] = 7, | |
535 | [IRQ_DA850_TINTALL_3] = 7, | |
536 | [IRQ_DA850_MCBSP0RINT] = 7, | |
537 | [IRQ_DA850_MCBSP0XINT] = 7, | |
538 | [IRQ_DA850_MCBSP1RINT] = 7, | |
539 | [IRQ_DA850_MCBSP1XINT] = 7, | |
540 | [IRQ_DA8XX_ARMCLKSTOPREQ] = 7, | |
541 | }; | |
542 | ||
543 | static struct map_desc da850_io_desc[] = { | |
544 | { | |
545 | .virtual = IO_VIRT, | |
546 | .pfn = __phys_to_pfn(IO_PHYS), | |
547 | .length = IO_SIZE, | |
548 | .type = MT_DEVICE | |
549 | }, | |
550 | { | |
551 | .virtual = DA8XX_CP_INTC_VIRT, | |
552 | .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE), | |
553 | .length = DA8XX_CP_INTC_SIZE, | |
554 | .type = MT_DEVICE | |
555 | }, | |
556 | }; | |
557 | ||
558 | static void __iomem *da850_psc_bases[] = { | |
559 | IO_ADDRESS(DA8XX_PSC0_BASE), | |
560 | IO_ADDRESS(DA8XX_PSC1_BASE), | |
561 | }; | |
562 | ||
563 | /* Contents of JTAG ID register used to identify exact cpu type */ | |
564 | static struct davinci_id da850_ids[] = { | |
565 | { | |
566 | .variant = 0x0, | |
567 | .part_no = 0xb7d1, | |
568 | .manufacturer = 0x017, /* 0x02f >> 1 */ | |
569 | .cpu_id = DAVINCI_CPU_ID_DA850, | |
570 | .name = "da850/omap-l138", | |
571 | }, | |
572 | }; | |
573 | ||
574 | static struct davinci_timer_instance da850_timer_instance[4] = { | |
575 | { | |
576 | .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE), | |
577 | .bottom_irq = IRQ_DA8XX_TINT12_0, | |
578 | .top_irq = IRQ_DA8XX_TINT34_0, | |
579 | }, | |
580 | { | |
581 | .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE), | |
582 | .bottom_irq = IRQ_DA8XX_TINT12_1, | |
583 | .top_irq = IRQ_DA8XX_TINT34_1, | |
584 | }, | |
585 | { | |
586 | .base = IO_ADDRESS(DA850_TIMER64P2_BASE), | |
587 | .bottom_irq = IRQ_DA850_TINT12_2, | |
588 | .top_irq = IRQ_DA850_TINT34_2, | |
589 | }, | |
590 | { | |
591 | .base = IO_ADDRESS(DA850_TIMER64P3_BASE), | |
592 | .bottom_irq = IRQ_DA850_TINT12_3, | |
593 | .top_irq = IRQ_DA850_TINT34_3, | |
594 | }, | |
595 | }; | |
596 | ||
597 | /* | |
598 | * T0_BOT: Timer 0, bottom : Used for clock_event | |
599 | * T0_TOP: Timer 0, top : Used for clocksource | |
600 | * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer | |
601 | */ | |
602 | static struct davinci_timer_info da850_timer_info = { | |
603 | .timers = da850_timer_instance, | |
604 | .clockevent_id = T0_BOT, | |
605 | .clocksource_id = T0_TOP, | |
606 | }; | |
607 | ||
608 | static struct davinci_soc_info davinci_soc_info_da850 = { | |
609 | .io_desc = da850_io_desc, | |
610 | .io_desc_num = ARRAY_SIZE(da850_io_desc), | |
611 | .jtag_id_base = IO_ADDRESS(DA8XX_JTAG_ID_REG), | |
612 | .ids = da850_ids, | |
613 | .ids_num = ARRAY_SIZE(da850_ids), | |
614 | .cpu_clks = da850_clks, | |
615 | .psc_bases = da850_psc_bases, | |
616 | .psc_bases_num = ARRAY_SIZE(da850_psc_bases), | |
617 | .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120), | |
618 | .pinmux_pins = da850_pins, | |
619 | .pinmux_pins_num = ARRAY_SIZE(da850_pins), | |
620 | .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, | |
621 | .intc_type = DAVINCI_INTC_TYPE_CP_INTC, | |
622 | .intc_irq_prios = da850_default_priorities, | |
623 | .intc_irq_num = DA850_N_CP_INTC_IRQ, | |
624 | .timer_info = &da850_timer_info, | |
625 | .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE), | |
626 | .gpio_num = 128, | |
627 | .gpio_irq = IRQ_DA8XX_GPIO0, | |
628 | .serial_dev = &da8xx_serial_device, | |
629 | .emac_pdata = &da8xx_emac_pdata, | |
630 | }; | |
631 | ||
632 | void __init da850_init(void) | |
633 | { | |
634 | davinci_common_init(&davinci_soc_info_da850); | |
635 | } |