projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 39c6d2d1 MH |
1 | /* |
| 2 | * This file contains the processor specific definitions | |
| 3 | * of the TI DM644x, DM355, DM365, and DM646x. | |
| 4 | * | |
| 5 | * Copyright (C) 2011 Texas Instruments Incorporated | |
| 6 | * Copyright (c) 2007 Deep Root Systems, LLC | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation version 2. | |
| 11 | * | |
| 12 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
| 13 | * kind, whether express or implied; without even the implied warranty | |
| 14 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | */ | |
| 17 | #ifndef __DAVINCI_H | |
| 18 | #define __DAVINCI_H | |
| 19 | ||
| 20 | #include <linux/clk.h> | |
| 21 | #include <linux/videodev2.h> | |
| 22 | #include <linux/davinci_emac.h> | |
| 23 | #include <linux/platform_device.h> | |
| 24 | #include <linux/spi/spi.h> | |
| 896f66b7 | 25 | #include <linux/platform_data/davinci_asp.h> |
| 3ad7a42d | 26 | #include <linux/platform_data/edma.h> |
| ec2a0833 | 27 | #include <linux/platform_data/keyscan-davinci.h> |
| 5cfb19ac | 28 | #include <mach/hardware.h> |
| 39c6d2d1 MH |
29 | |
| 30 | #include <media/davinci/vpfe_capture.h> | |
| 31 | #include <media/davinci/vpif_types.h> | |
| af946f26 MH |
32 | #include <media/davinci/vpss.h> |
| 33 | #include <media/davinci/vpbe_types.h> | |
| 34 | #include <media/davinci/vpbe_venc.h> | |
| 35 | #include <media/davinci/vpbe.h> | |
| 36 | #include <media/davinci/vpbe_osd.h> | |
| 39c6d2d1 | 37 | |
| 5cfb19ac | 38 | #define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000 |
| 120c6604 | 39 | #define SYSMOD_VDAC_CONFIG 0x2c |
| 5cfb19ac | 40 | #define SYSMOD_VIDCLKCTL 0x38 |
| af946f26 | 41 | #define SYSMOD_VPSS_CLKCTL 0x44 |
| 5cfb19ac MH |
42 | #define SYSMOD_VDD3P3VPWDN 0x48 |
| 43 | #define SYSMOD_VSCLKDIS 0x6c | |
| 44 | #define SYSMOD_PUPDCTL1 0x7c | |
| 45 | ||
| 120c6604 | 46 | /* VPSS CLKCTL bit definitions */ |
| 62a2d6cd | 47 | #define VPSS_MUXSEL_EXTCLK_ENABLE BIT(1) |
| 120c6604 LP |
48 | #define VPSS_VENCCLKEN_ENABLE BIT(3) |
| 49 | #define VPSS_DACCLKEN_ENABLE BIT(4) | |
| 50 | #define VPSS_PLLC2SYSCLK5_ENABLE BIT(5) | |
| 51 | ||
| 5cfb19ac MH |
52 | extern void __iomem *davinci_sysmod_base; |
| 53 | #define DAVINCI_SYSMOD_VIRT(x) (davinci_sysmod_base + (x)) | |
| 54 | void davinci_map_sysmod(void); | |
| 55 | ||
| 9cc1515c PA |
56 | #define DAVINCI_GPIO_BASE 0x01C67000 |
| 57 | int davinci_gpio_register(struct resource *res, int size, void *pdata); | |
| 58 | ||
| 39c6d2d1 MH |
59 | /* DM355 base addresses */ |
| 60 | #define DM355_ASYNC_EMIF_CONTROL_BASE 0x01e10000 | |
| 61 | #define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 | |
| 62 | ||
| 63 | #define ASP1_TX_EVT_EN 1 | |
| 64 | #define ASP1_RX_EVT_EN 2 | |
| 65 | ||
| 66 | /* DM365 base addresses */ | |
| 67 | #define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000 | |
| 68 | #define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 | |
| 69 | #define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 | |
| 70 | ||
| 71 | /* DM644x base addresses */ | |
| 72 | #define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01e00000 | |
| 73 | #define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 | |
| 74 | #define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 | |
| 75 | #define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000 | |
| 76 | #define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000 | |
| 77 | ||
| 78 | /* DM646x base addresses */ | |
| 79 | #define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000 | |
| 80 | #define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000 | |
| 81 | ||
| 1233090c SN |
82 | int davinci_init_wdt(void); |
| 83 | ||
| 39c6d2d1 | 84 | /* DM355 function declarations */ |
| b464e3cb | 85 | void dm355_init(void); |
| 39c6d2d1 | 86 | void dm355_init_spi0(unsigned chipselect_mask, |
| d65566e5 | 87 | const struct spi_board_info *info, unsigned len); |
| 6bce5efd | 88 | void dm355_init_asp1(u32 evt_enable); |
| 62a2d6cd | 89 | int dm355_init_video(struct vpfe_config *, struct vpbe_config *); |
| 9cc1515c | 90 | int dm355_gpio_register(void); |
| 39c6d2d1 MH |
91 | |
| 92 | /* DM365 function declarations */ | |
| b464e3cb | 93 | void dm365_init(void); |
| 6bce5efd | 94 | void dm365_init_asp(void); |
| 933b11ae | 95 | void dm365_init_vc(void); |
| b464e3cb LP |
96 | void dm365_init_ks(struct davinci_ks_platform_data *pdata); |
| 97 | void dm365_init_rtc(void); | |
| 39c6d2d1 | 98 | void dm365_init_spi0(unsigned chipselect_mask, |
| d65566e5 | 99 | const struct spi_board_info *info, unsigned len); |
| 120c6604 | 100 | int dm365_init_video(struct vpfe_config *, struct vpbe_config *); |
| 9cc1515c | 101 | int dm365_gpio_register(void); |
| 39c6d2d1 MH |
102 | |
| 103 | /* DM644x function declarations */ | |
| b464e3cb | 104 | void dm644x_init(void); |
| 6bce5efd | 105 | void dm644x_init_asp(void); |
| b464e3cb | 106 | int dm644x_init_video(struct vpfe_config *, struct vpbe_config *); |
| 9cc1515c | 107 | int dm644x_gpio_register(void); |
| 39c6d2d1 MH |
108 | |
| 109 | /* DM646x function declarations */ | |
| b464e3cb LP |
110 | void dm646x_init(void); |
| 111 | void dm646x_init_mcasp0(struct snd_platform_data *pdata); | |
| 112 | void dm646x_init_mcasp1(struct snd_platform_data *pdata); | |
| 113 | int dm646x_init_edma(struct edma_rsv_info *rsv); | |
| 39c6d2d1 MH |
114 | void dm646x_video_init(void); |
| 115 | void dm646x_setup_vpif(struct vpif_display_config *, | |
| 116 | struct vpif_capture_config *); | |
| 9cc1515c | 117 | int dm646x_gpio_register(void); |
| fcf7157b MP |
118 | |
| 119 | extern struct platform_device dm365_serial_device[]; | |
| 120 | extern struct platform_device dm355_serial_device[]; | |
| 121 | extern struct platform_device dm644x_serial_device[]; | |
| 122 | extern struct platform_device dm646x_serial_device[]; | |
| 39c6d2d1 | 123 | #endif /*__DAVINCI_H */ |