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d395e6ad KS |
1 | /* |
2 | * mach-davinci/devices.c | |
3 | * | |
4 | * DaVinci platform device setup/initialization | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
d395e6ad KS |
12 | #include <linux/init.h> |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/dma-mapping.h> | |
15 | #include <linux/io.h> | |
16 | ||
d395e6ad KS |
17 | #include <mach/hardware.h> |
18 | #include <mach/i2c.h> | |
80b02c17 | 19 | #include <mach/irqs.h> |
5526b3f7 KH |
20 | #include <mach/cputype.h> |
21 | #include <mach/mux.h> | |
2dbf56ae KH |
22 | #include <mach/edma.h> |
23 | #include <mach/mmc.h> | |
f64691b3 | 24 | #include <mach/time.h> |
d395e6ad | 25 | |
28552c2e KH |
26 | #include "clock.h" |
27 | ||
f5c122da | 28 | #define DAVINCI_I2C_BASE 0x01C21000 |
7a9978a1 | 29 | #define DAVINCI_ATA_BASE 0x01C66000 |
2dbf56ae KH |
30 | #define DAVINCI_MMCSD0_BASE 0x01E10000 |
31 | #define DM355_MMCSD0_BASE 0x01E11000 | |
32 | #define DM355_MMCSD1_BASE 0x01E00000 | |
19ff3bf2 SP |
33 | #define DM365_MMCSD0_BASE 0x01D11000 |
34 | #define DM365_MMCSD1_BASE 0x01D00000 | |
f5c122da | 35 | |
1a717c00 MH |
36 | /* System control register offsets */ |
37 | #define DM64XX_VDD3P3V_PWDN 0x48 | |
38 | ||
d395e6ad KS |
39 | static struct resource i2c_resources[] = { |
40 | { | |
41 | .start = DAVINCI_I2C_BASE, | |
42 | .end = DAVINCI_I2C_BASE + 0x40, | |
43 | .flags = IORESOURCE_MEM, | |
44 | }, | |
45 | { | |
46 | .start = IRQ_I2C, | |
47 | .flags = IORESOURCE_IRQ, | |
48 | }, | |
49 | }; | |
50 | ||
51 | static struct platform_device davinci_i2c_device = { | |
52 | .name = "i2c_davinci", | |
53 | .id = 1, | |
54 | .num_resources = ARRAY_SIZE(i2c_resources), | |
55 | .resource = i2c_resources, | |
56 | }; | |
57 | ||
58 | void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata) | |
59 | { | |
5526b3f7 KH |
60 | if (cpu_is_davinci_dm644x()) |
61 | davinci_cfg_reg(DM644X_I2C); | |
62 | ||
d395e6ad KS |
63 | davinci_i2c_device.dev.platform_data = pdata; |
64 | (void) platform_device_register(&davinci_i2c_device); | |
65 | } | |
66 | ||
7a9978a1 SS |
67 | static struct resource ide_resources[] = { |
68 | { | |
69 | .start = DAVINCI_ATA_BASE, | |
70 | .end = DAVINCI_ATA_BASE + 0x7ff, | |
71 | .flags = IORESOURCE_MEM, | |
72 | }, | |
73 | { | |
74 | .start = IRQ_IDE, | |
75 | .end = IRQ_IDE, | |
76 | .flags = IORESOURCE_IRQ, | |
77 | }, | |
78 | }; | |
79 | ||
80 | static u64 ide_dma_mask = DMA_BIT_MASK(32); | |
81 | ||
82 | static struct platform_device ide_device = { | |
83 | .name = "palm_bk3710", | |
84 | .id = -1, | |
85 | .resource = ide_resources, | |
86 | .num_resources = ARRAY_SIZE(ide_resources), | |
87 | .dev = { | |
88 | .dma_mask = &ide_dma_mask, | |
89 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
90 | }, | |
91 | }; | |
92 | ||
93 | void __init davinci_init_ide(void) | |
94 | { | |
95 | if (cpu_is_davinci_dm644x()) { | |
96 | davinci_cfg_reg(DM644X_HPIEN_DISABLE); | |
97 | davinci_cfg_reg(DM644X_ATAEN); | |
98 | davinci_cfg_reg(DM644X_HDIREN); | |
99 | } else if (cpu_is_davinci_dm646x()) { | |
100 | /* IRQ_DM646X_IDE is the same as IRQ_IDE */ | |
101 | davinci_cfg_reg(DM646X_ATAEN); | |
102 | } else { | |
103 | WARN_ON(1); | |
104 | return; | |
105 | } | |
106 | ||
107 | platform_device_register(&ide_device); | |
108 | } | |
109 | ||
2dbf56ae KH |
110 | #if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE) |
111 | ||
b0958aed | 112 | static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32); |
2dbf56ae KH |
113 | |
114 | static struct resource mmcsd0_resources[] = { | |
115 | { | |
116 | /* different on dm355 */ | |
117 | .start = DAVINCI_MMCSD0_BASE, | |
118 | .end = DAVINCI_MMCSD0_BASE + SZ_4K - 1, | |
119 | .flags = IORESOURCE_MEM, | |
120 | }, | |
121 | /* IRQs: MMC/SD, then SDIO */ | |
122 | { | |
123 | .start = IRQ_MMCINT, | |
124 | .flags = IORESOURCE_IRQ, | |
125 | }, { | |
126 | /* different on dm355 */ | |
127 | .start = IRQ_SDIOINT, | |
128 | .flags = IORESOURCE_IRQ, | |
129 | }, | |
130 | /* DMA channels: RX, then TX */ | |
131 | { | |
60902a2c | 132 | .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCRXEVT), |
2dbf56ae KH |
133 | .flags = IORESOURCE_DMA, |
134 | }, { | |
60902a2c | 135 | .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCTXEVT), |
2dbf56ae KH |
136 | .flags = IORESOURCE_DMA, |
137 | }, | |
138 | }; | |
139 | ||
140 | static struct platform_device davinci_mmcsd0_device = { | |
141 | .name = "davinci_mmc", | |
142 | .id = 0, | |
143 | .dev = { | |
144 | .dma_mask = &mmcsd0_dma_mask, | |
b0958aed | 145 | .coherent_dma_mask = DMA_BIT_MASK(32), |
2dbf56ae KH |
146 | }, |
147 | .num_resources = ARRAY_SIZE(mmcsd0_resources), | |
148 | .resource = mmcsd0_resources, | |
149 | }; | |
150 | ||
b0958aed | 151 | static u64 mmcsd1_dma_mask = DMA_BIT_MASK(32); |
2dbf56ae KH |
152 | |
153 | static struct resource mmcsd1_resources[] = { | |
154 | { | |
155 | .start = DM355_MMCSD1_BASE, | |
156 | .end = DM355_MMCSD1_BASE + SZ_4K - 1, | |
157 | .flags = IORESOURCE_MEM, | |
158 | }, | |
159 | /* IRQs: MMC/SD, then SDIO */ | |
160 | { | |
161 | .start = IRQ_DM355_MMCINT1, | |
162 | .flags = IORESOURCE_IRQ, | |
163 | }, { | |
164 | .start = IRQ_DM355_SDIOINT1, | |
165 | .flags = IORESOURCE_IRQ, | |
166 | }, | |
167 | /* DMA channels: RX, then TX */ | |
168 | { | |
60902a2c | 169 | .start = EDMA_CTLR_CHAN(0, 30), /* rx */ |
2dbf56ae KH |
170 | .flags = IORESOURCE_DMA, |
171 | }, { | |
60902a2c | 172 | .start = EDMA_CTLR_CHAN(0, 31), /* tx */ |
2dbf56ae KH |
173 | .flags = IORESOURCE_DMA, |
174 | }, | |
175 | }; | |
176 | ||
177 | static struct platform_device davinci_mmcsd1_device = { | |
178 | .name = "davinci_mmc", | |
179 | .id = 1, | |
180 | .dev = { | |
181 | .dma_mask = &mmcsd1_dma_mask, | |
b0958aed | 182 | .coherent_dma_mask = DMA_BIT_MASK(32), |
2dbf56ae KH |
183 | }, |
184 | .num_resources = ARRAY_SIZE(mmcsd1_resources), | |
185 | .resource = mmcsd1_resources, | |
186 | }; | |
187 | ||
188 | ||
189 | void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) | |
190 | { | |
191 | struct platform_device *pdev = NULL; | |
192 | ||
193 | if (WARN_ON(cpu_is_davinci_dm646x())) | |
194 | return; | |
195 | ||
196 | /* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too; | |
197 | * for example if MMCSD1 is used for SDIO, maybe DAT2 is unused. | |
198 | * | |
199 | * FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are | |
200 | * not handled right here ... | |
201 | */ | |
202 | switch (module) { | |
203 | case 1: | |
19ff3bf2 SP |
204 | if (cpu_is_davinci_dm355()) { |
205 | /* REVISIT we may not need all these pins if e.g. this | |
206 | * is a hard-wired SDIO device... | |
207 | */ | |
208 | davinci_cfg_reg(DM355_SD1_CMD); | |
209 | davinci_cfg_reg(DM355_SD1_CLK); | |
210 | davinci_cfg_reg(DM355_SD1_DATA0); | |
211 | davinci_cfg_reg(DM355_SD1_DATA1); | |
212 | davinci_cfg_reg(DM355_SD1_DATA2); | |
213 | davinci_cfg_reg(DM355_SD1_DATA3); | |
214 | } else if (cpu_is_davinci_dm365()) { | |
215 | void __iomem *pupdctl1 = | |
216 | IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c); | |
217 | ||
218 | /* Configure pull down control */ | |
0a477f6b | 219 | __raw_writel((__raw_readl(pupdctl1) & ~0xfc0), |
19ff3bf2 SP |
220 | pupdctl1); |
221 | ||
222 | mmcsd1_resources[0].start = DM365_MMCSD1_BASE; | |
223 | mmcsd1_resources[0].end = DM365_MMCSD1_BASE + | |
224 | SZ_4K - 1; | |
eb5ba378 | 225 | mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1; |
19ff3bf2 | 226 | } else |
2dbf56ae KH |
227 | break; |
228 | ||
2dbf56ae KH |
229 | pdev = &davinci_mmcsd1_device; |
230 | break; | |
231 | case 0: | |
232 | if (cpu_is_davinci_dm355()) { | |
233 | mmcsd0_resources[0].start = DM355_MMCSD0_BASE; | |
234 | mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1; | |
235 | mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0; | |
236 | ||
237 | /* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */ | |
238 | davinci_cfg_reg(DM355_MMCSD0); | |
239 | ||
240 | /* enable RX EDMA */ | |
241 | davinci_cfg_reg(DM355_EVT26_MMC0_RX); | |
19ff3bf2 SP |
242 | } else if (cpu_is_davinci_dm365()) { |
243 | mmcsd0_resources[0].start = DM365_MMCSD0_BASE; | |
244 | mmcsd0_resources[0].end = DM365_MMCSD0_BASE + | |
245 | SZ_4K - 1; | |
246 | mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0; | |
247 | } else if (cpu_is_davinci_dm644x()) { | |
2dbf56ae KH |
248 | /* REVISIT: should this be in board-init code? */ |
249 | void __iomem *base = | |
250 | IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); | |
251 | ||
252 | /* Power-on 3.3V IO cells */ | |
253 | __raw_writel(0, base + DM64XX_VDD3P3V_PWDN); | |
254 | /*Set up the pull regiter for MMC */ | |
255 | davinci_cfg_reg(DM644X_MSTK); | |
256 | } | |
257 | ||
258 | pdev = &davinci_mmcsd0_device; | |
259 | break; | |
260 | } | |
261 | ||
262 | if (WARN_ON(!pdev)) | |
263 | return; | |
264 | ||
265 | pdev->dev.platform_data = config; | |
266 | platform_device_register(pdev); | |
267 | } | |
268 | ||
269 | #else | |
270 | ||
271 | void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) | |
272 | { | |
273 | } | |
274 | ||
275 | #endif | |
276 | ||
fb631387 KH |
277 | /*-------------------------------------------------------------------------*/ |
278 | ||
279 | static struct resource wdt_resources[] = { | |
280 | { | |
5fcd294d KH |
281 | .start = DAVINCI_WDOG_BASE, |
282 | .end = DAVINCI_WDOG_BASE + SZ_1K - 1, | |
fb631387 KH |
283 | .flags = IORESOURCE_MEM, |
284 | }, | |
285 | }; | |
286 | ||
287 | struct platform_device davinci_wdt_device = { | |
288 | .name = "watchdog", | |
289 | .id = -1, | |
290 | .num_resources = ARRAY_SIZE(wdt_resources), | |
291 | .resource = wdt_resources, | |
292 | }; | |
293 | ||
c6121ddd SN |
294 | void davinci_restart(char mode, const char *cmd) |
295 | { | |
296 | davinci_watchdog_reset(&davinci_wdt_device); | |
297 | } | |
298 | ||
fb631387 KH |
299 | static void davinci_init_wdt(void) |
300 | { | |
301 | platform_device_register(&davinci_wdt_device); | |
302 | } | |
303 | ||
304 | /*-------------------------------------------------------------------------*/ | |
305 | ||
7e9f1945 | 306 | static struct platform_device davinci_pcm_device = { |
f0fba2ad LG |
307 | .name = "davinci-pcm-audio", |
308 | .id = -1, | |
309 | }; | |
310 | ||
311 | static void davinci_init_pcm(void) | |
312 | { | |
313 | platform_device_register(&davinci_pcm_device); | |
314 | } | |
315 | ||
316 | /*-------------------------------------------------------------------------*/ | |
317 | ||
f64691b3 MG |
318 | struct davinci_timer_instance davinci_timer_instance[2] = { |
319 | { | |
1bcd38ad | 320 | .base = DAVINCI_TIMER0_BASE, |
f64691b3 MG |
321 | .bottom_irq = IRQ_TINT0_TINT12, |
322 | .top_irq = IRQ_TINT0_TINT34, | |
323 | }, | |
324 | { | |
1bcd38ad | 325 | .base = DAVINCI_TIMER1_BASE, |
f64691b3 MG |
326 | .bottom_irq = IRQ_TINT1_TINT12, |
327 | .top_irq = IRQ_TINT1_TINT34, | |
328 | }, | |
329 | }; | |
330 | ||
331 | /*-------------------------------------------------------------------------*/ | |
332 | ||
fb631387 KH |
333 | static int __init davinci_init_devices(void) |
334 | { | |
335 | /* please keep these calls, and their implementations above, | |
336 | * in alphabetical order so they're easier to sort through. | |
337 | */ | |
f0fba2ad | 338 | davinci_init_pcm(); |
fb631387 KH |
339 | davinci_init_wdt(); |
340 | ||
341 | return 0; | |
342 | } | |
343 | arch_initcall(davinci_init_devices); | |
344 |