[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-davinci / dm355.c

/*
 * TI DaVinci DM355 chip specific setup
 *
 * Author: Kevin Hilman, Deep Root Systems, LLC
 *
 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/serial_8250.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>

#include <linux/spi/spi.h>

#include <asm/mach/map.h>

#include <mach/dm355.h>
#include <mach/clock.h>
#include <mach/cputype.h>
#include <mach/edma.h>
#include <mach/psc.h>
#include <mach/mux.h>
#include <mach/irqs.h>
#include <mach/time.h>
#include <mach/serial.h>
#include <mach/common.h>
#include <mach/asp.h>

#include "clock.h"
#include "mux.h"

#define DM355_UART2_BASE	(IO_PHYS + 0x206000)

/*
 * Device specific clocks
 */
#define DM355_REF_FREQ		24000000	/* 24 or 36 MHz */

static struct pll_data pll1_data = {
	.num       = 1,
	.phys_base = DAVINCI_PLL1_BASE,
	.flags     = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
};

static struct pll_data pll2_data = {
	.num       = 2,
	.phys_base = DAVINCI_PLL2_BASE,
	.flags     = PLL_HAS_PREDIV,
};

static struct clk ref_clk = {
	.name = "ref_clk",
	/* FIXME -- crystal rate is board-specific */
	.rate = DM355_REF_FREQ,
};

static struct clk pll1_clk = {
	.name = "pll1",
	.parent = &ref_clk,
	.flags = CLK_PLL,
	.pll_data = &pll1_data,
};

static struct clk pll1_aux_clk = {
	.name = "pll1_aux_clk",
	.parent = &pll1_clk,
	.flags = CLK_PLL | PRE_PLL,
};

static struct clk pll1_sysclk1 = {
	.name = "pll1_sysclk1",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV1,
};

static struct clk pll1_sysclk2 = {
	.name = "pll1_sysclk2",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV2,
};

static struct clk pll1_sysclk3 = {
	.name = "pll1_sysclk3",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV3,
};

static struct clk pll1_sysclk4 = {
	.name = "pll1_sysclk4",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV4,
};

static struct clk pll1_sysclkbp = {
	.name = "pll1_sysclkbp",
	.parent = &pll1_clk,
	.flags = CLK_PLL | PRE_PLL,
	.div_reg = BPDIV
};

static struct clk vpss_dac_clk = {
	.name = "vpss_dac",
	.parent = &pll1_sysclk3,
	.lpsc = DM355_LPSC_VPSS_DAC,
};

static struct clk vpss_master_clk = {
	.name = "vpss_master",
	.parent = &pll1_sysclk4,
	.lpsc = DAVINCI_LPSC_VPSSMSTR,
	.flags = CLK_PSC,
};

static struct clk vpss_slave_clk = {
	.name = "vpss_slave",
	.parent = &pll1_sysclk4,
	.lpsc = DAVINCI_LPSC_VPSSSLV,
};


static struct clk clkout1_clk = {
	.name = "clkout1",
	.parent = &pll1_aux_clk,
	/* NOTE:  clkout1 can be externally gated by muxing GPIO-18 */
};

static struct clk clkout2_clk = {
	.name = "clkout2",
	.parent = &pll1_sysclkbp,
};

static struct clk pll2_clk = {
	.name = "pll2",
	.parent = &ref_clk,
	.flags = CLK_PLL,
	.pll_data = &pll2_data,
};

static struct clk pll2_sysclk1 = {
	.name = "pll2_sysclk1",
	.parent = &pll2_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV1,
};

static struct clk pll2_sysclkbp = {
	.name = "pll2_sysclkbp",
	.parent = &pll2_clk,
	.flags = CLK_PLL | PRE_PLL,
	.div_reg = BPDIV
};

static struct clk clkout3_clk = {
	.name = "clkout3",
	.parent = &pll2_sysclkbp,
	/* NOTE:  clkout3 can be externally gated by muxing GPIO-16 */
};

static struct clk arm_clk = {
	.name = "arm_clk",
	.parent = &pll1_sysclk1,
	.lpsc = DAVINCI_LPSC_ARM,
	.flags = ALWAYS_ENABLED,
};

/*
 * NOT LISTED below, and not touched by Linux
 *   - in SyncReset state by default
 *	.lpsc = DAVINCI_LPSC_TPCC,
 *	.lpsc = DAVINCI_LPSC_TPTC0,
 *	.lpsc = DAVINCI_LPSC_TPTC1,
 *	.lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
 *	.lpsc = DAVINCI_LPSC_MEMSTICK,
 *   - in Enabled state by default
 *	.lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
 *	.lpsc = DAVINCI_LPSC_SCR2,	// "bus"
 *	.lpsc = DAVINCI_LPSC_SCR3,	// "bus"
 *	.lpsc = DAVINCI_LPSC_SCR4,	// "bus"
 *	.lpsc = DAVINCI_LPSC_CROSSBAR,	// "emulation"
 *	.lpsc = DAVINCI_LPSC_CFG27,	// "test"
 *	.lpsc = DAVINCI_LPSC_CFG3,	// "test"
 *	.lpsc = DAVINCI_LPSC_CFG5,	// "test"
 */

static struct clk mjcp_clk = {
	.name = "mjcp",
	.parent = &pll1_sysclk1,
	.lpsc = DAVINCI_LPSC_IMCOP,
};

static struct clk uart0_clk = {
	.name = "uart0",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_UART0,
};

static struct clk uart1_clk = {
	.name = "uart1",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_UART1,
};

static struct clk uart2_clk = {
	.name = "uart2",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_UART2,
};

static struct clk i2c_clk = {
	.name = "i2c",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_I2C,
};

static struct clk asp0_clk = {
	.name = "asp0",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_McBSP,
};

static struct clk asp1_clk = {
	.name = "asp1",
	.parent = &pll1_sysclk2,
	.lpsc = DM355_LPSC_McBSP1,
};

static struct clk mmcsd0_clk = {
	.name = "mmcsd0",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_MMC_SD,
};

static struct clk mmcsd1_clk = {
	.name = "mmcsd1",
	.parent = &pll1_sysclk2,
	.lpsc = DM355_LPSC_MMC_SD1,
};

static struct clk spi0_clk = {
	.name = "spi0",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_SPI,
};

static struct clk spi1_clk = {
	.name = "spi1",
	.parent = &pll1_sysclk2,
	.lpsc = DM355_LPSC_SPI1,
};

static struct clk spi2_clk = {
	.name = "spi2",
	.parent = &pll1_sysclk2,
	.lpsc = DM355_LPSC_SPI2,
};

static struct clk gpio_clk = {
	.name = "gpio",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_GPIO,
};

static struct clk aemif_clk = {
	.name = "aemif",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_AEMIF,
};

static struct clk pwm0_clk = {
	.name = "pwm0",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_PWM0,
};

static struct clk pwm1_clk = {
	.name = "pwm1",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_PWM1,
};

static struct clk pwm2_clk = {
	.name = "pwm2",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_PWM2,
};

static struct clk pwm3_clk = {
	.name = "pwm3",
	.parent = &pll1_aux_clk,
	.lpsc = DM355_LPSC_PWM3,
};

static struct clk timer0_clk = {
	.name = "timer0",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_TIMER0,
};

static struct clk timer1_clk = {
	.name = "timer1",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_TIMER1,
};

static struct clk timer2_clk = {
	.name = "timer2",
	.parent = &pll1_aux_clk,
	.lpsc = DAVINCI_LPSC_TIMER2,
	.usecount = 1,              /* REVISIT: why cant' this be disabled? */
};

static struct clk timer3_clk = {
	.name = "timer3",
	.parent = &pll1_aux_clk,
	.lpsc = DM355_LPSC_TIMER3,
};

static struct clk rto_clk = {
	.name = "rto",
	.parent = &pll1_aux_clk,
	.lpsc = DM355_LPSC_RTO,
};

static struct clk usb_clk = {
	.name = "usb",
	.parent = &pll1_sysclk2,
	.lpsc = DAVINCI_LPSC_USB,
};

static struct davinci_clk dm355_clks[] = {
	CLK(NULL, "ref", &ref_clk),
	CLK(NULL, "pll1", &pll1_clk),
	CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
	CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
	CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
	CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
	CLK(NULL, "pll1_aux", &pll1_aux_clk),
	CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
	CLK(NULL, "vpss_dac", &vpss_dac_clk),
	CLK(NULL, "vpss_master", &vpss_master_clk),
	CLK(NULL, "vpss_slave", &vpss_slave_clk),
	CLK(NULL, "clkout1", &clkout1_clk),
	CLK(NULL, "clkout2", &clkout2_clk),
	CLK(NULL, "pll2", &pll2_clk),
	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
	CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
	CLK(NULL, "clkout3", &clkout3_clk),
	CLK(NULL, "arm", &arm_clk),
	CLK(NULL, "mjcp", &mjcp_clk),
	CLK(NULL, "uart0", &uart0_clk),
	CLK(NULL, "uart1", &uart1_clk),
	CLK(NULL, "uart2", &uart2_clk),
	CLK("i2c_davinci.1", NULL, &i2c_clk),
	CLK(NULL, "asp0", &asp0_clk),
	CLK(NULL, "asp1", &asp1_clk),
	CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
	CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
	CLK(NULL, "spi0", &spi0_clk),
	CLK(NULL, "spi1", &spi1_clk),
	CLK(NULL, "spi2", &spi2_clk),
	CLK(NULL, "gpio", &gpio_clk),
	CLK(NULL, "aemif", &aemif_clk),
	CLK(NULL, "pwm0", &pwm0_clk),
	CLK(NULL, "pwm1", &pwm1_clk),
	CLK(NULL, "pwm2", &pwm2_clk),
	CLK(NULL, "pwm3", &pwm3_clk),
	CLK(NULL, "timer0", &timer0_clk),
	CLK(NULL, "timer1", &timer1_clk),
	CLK("watchdog", NULL, &timer2_clk),
	CLK(NULL, "timer3", &timer3_clk),
	CLK(NULL, "rto", &rto_clk),
	CLK(NULL, "usb", &usb_clk),
	CLK(NULL, NULL, NULL),
};

/*----------------------------------------------------------------------*/

static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);

static struct resource dm355_spi0_resources[] = {
	{
		.start = 0x01c66000,
		.end   = 0x01c667ff,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = IRQ_DM355_SPINT0_1,
		.flags = IORESOURCE_IRQ,
	},
	/* Not yet used, so not included:
	 * IORESOURCE_IRQ:
	 *  - IRQ_DM355_SPINT0_0
	 * IORESOURCE_DMA:
	 *  - DAVINCI_DMA_SPI_SPIX
	 *  - DAVINCI_DMA_SPI_SPIR
	 */
};

static struct platform_device dm355_spi0_device = {
	.name = "spi_davinci",
	.id = 0,
	.dev = {
		.dma_mask = &dm355_spi0_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.num_resources = ARRAY_SIZE(dm355_spi0_resources),
	.resource = dm355_spi0_resources,
};

void __init dm355_init_spi0(unsigned chipselect_mask,
		struct spi_board_info *info, unsigned len)
{
	/* for now, assume we need MISO */
	davinci_cfg_reg(DM355_SPI0_SDI);

	/* not all slaves will be wired up */
	if (chipselect_mask & BIT(0))
		davinci_cfg_reg(DM355_SPI0_SDENA0);
	if (chipselect_mask & BIT(1))
		davinci_cfg_reg(DM355_SPI0_SDENA1);

	spi_register_board_info(info, len);

	platform_device_register(&dm355_spi0_device);
}

/*----------------------------------------------------------------------*/

#define PINMUX0		0x00
#define PINMUX1		0x04
#define PINMUX2		0x08
#define PINMUX3		0x0c
#define PINMUX4		0x10
#define INTMUX		0x18
#define EVTMUX		0x1c

/*
 * Device specific mux setup
 *
 *	soc	description	mux  mode   mode  mux	 dbg
 *				reg  offset mask  mode
 */
static const struct mux_config dm355_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
MUX_CFG(DM355,	MMCSD0,		4,   2,     1,	  0,	 false)

MUX_CFG(DM355,	SD1_CLK,	3,   6,     1,	  1,	 false)
MUX_CFG(DM355,	SD1_CMD,	3,   7,     1,	  1,	 false)
MUX_CFG(DM355,	SD1_DATA3,	3,   8,     3,	  1,	 false)
MUX_CFG(DM355,	SD1_DATA2,	3,   10,    3,	  1,	 false)
MUX_CFG(DM355,	SD1_DATA1,	3,   12,    3,	  1,	 false)
MUX_CFG(DM355,	SD1_DATA0,	3,   14,    3,	  1,	 false)

MUX_CFG(DM355,	I2C_SDA,	3,   19,    1,	  1,	 false)
MUX_CFG(DM355,	I2C_SCL,	3,   20,    1,	  1,	 false)

MUX_CFG(DM355,	MCBSP0_BDX,	3,   0,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_X,	3,   1,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_BFSX,	3,   2,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_BDR,	3,   3,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_R,	3,   4,     1,	  1,	 false)
MUX_CFG(DM355,	MCBSP0_BFSR,	3,   5,     1,	  1,	 false)

MUX_CFG(DM355,	SPI0_SDI,	4,   1,     1,    0,	 false)
MUX_CFG(DM355,	SPI0_SDENA0,	4,   0,     1,    0,	 false)
MUX_CFG(DM355,	SPI0_SDENA1,	3,   28,    1,    1,	 false)

INT_CFG(DM355,  INT_EDMA_CC,	      2,    1,    1,     false)
INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)

EVT_CFG(DM355,  EVT8_ASP1_TX,	      0,    1,    0,     false)
EVT_CFG(DM355,  EVT9_ASP1_RX,	      1,    1,    0,     false)
EVT_CFG(DM355,  EVT26_MMC0_RX,	      2,    1,    0,     false)
#endif
};

static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
	[IRQ_DM355_CCDC_VDINT0]		= 2,
	[IRQ_DM355_CCDC_VDINT1]		= 6,
	[IRQ_DM355_CCDC_VDINT2]		= 6,
	[IRQ_DM355_IPIPE_HST]		= 6,
	[IRQ_DM355_H3AINT]		= 6,
	[IRQ_DM355_IPIPE_SDR]		= 6,
	[IRQ_DM355_IPIPEIFINT]		= 6,
	[IRQ_DM355_OSDINT]		= 7,
	[IRQ_DM355_VENCINT]		= 6,
	[IRQ_ASQINT]			= 6,
	[IRQ_IMXINT]			= 6,
	[IRQ_USBINT]			= 4,
	[IRQ_DM355_RTOINT]		= 4,
	[IRQ_DM355_UARTINT2]		= 7,
	[IRQ_DM355_TINT6]		= 7,
	[IRQ_CCINT0]			= 5,	/* dma */
	[IRQ_CCERRINT]			= 5,	/* dma */
	[IRQ_TCERRINT0]			= 5,	/* dma */
	[IRQ_TCERRINT]			= 5,	/* dma */
	[IRQ_DM355_SPINT2_1]		= 7,
	[IRQ_DM355_TINT7]		= 4,
	[IRQ_DM355_SDIOINT0]		= 7,
	[IRQ_MBXINT]			= 7,
	[IRQ_MBRINT]			= 7,
	[IRQ_MMCINT]			= 7,
	[IRQ_DM355_MMCINT1]		= 7,
	[IRQ_DM355_PWMINT3]		= 7,
	[IRQ_DDRINT]			= 7,
	[IRQ_AEMIFINT]			= 7,
	[IRQ_DM355_SDIOINT1]		= 4,
	[IRQ_TINT0_TINT12]		= 2,	/* clockevent */
	[IRQ_TINT0_TINT34]		= 2,	/* clocksource */
	[IRQ_TINT1_TINT12]		= 7,	/* DSP timer */
	[IRQ_TINT1_TINT34]		= 7,	/* system tick */
	[IRQ_PWMINT0]			= 7,
	[IRQ_PWMINT1]			= 7,
	[IRQ_PWMINT2]			= 7,
	[IRQ_I2C]			= 3,
	[IRQ_UARTINT0]			= 3,
	[IRQ_UARTINT1]			= 3,
	[IRQ_DM355_SPINT0_0]		= 3,
	[IRQ_DM355_SPINT0_1]		= 3,
	[IRQ_DM355_GPIO0]		= 3,
	[IRQ_DM355_GPIO1]		= 7,
	[IRQ_DM355_GPIO2]		= 4,
	[IRQ_DM355_GPIO3]		= 4,
	[IRQ_DM355_GPIO4]		= 7,
	[IRQ_DM355_GPIO5]		= 7,
	[IRQ_DM355_GPIO6]		= 7,
	[IRQ_DM355_GPIO7]		= 7,
	[IRQ_DM355_GPIO8]		= 7,
	[IRQ_DM355_GPIO9]		= 7,
	[IRQ_DM355_GPIOBNK0]		= 7,
	[IRQ_DM355_GPIOBNK1]		= 7,
	[IRQ_DM355_GPIOBNK2]		= 7,
	[IRQ_DM355_GPIOBNK3]		= 7,
	[IRQ_DM355_GPIOBNK4]		= 7,
	[IRQ_DM355_GPIOBNK5]		= 7,
	[IRQ_DM355_GPIOBNK6]		= 7,
	[IRQ_COMMTX]			= 7,
	[IRQ_COMMRX]			= 7,
	[IRQ_EMUINT]			= 7,
};

/*----------------------------------------------------------------------*/

static const s8 dma_chan_dm355_no_event[] = {
	12, 13, 24, 56, 57,
	58, 59, 60, 61, 62,
	63,
	-1
};

static const s8
queue_tc_mapping[][2] = {
	/* {event queue no, TC no} */
	{0, 0},
	{1, 1},
	{-1, -1},
};

static const s8
queue_priority_mapping[][2] = {
	/* {event queue no, Priority} */
	{0, 3},
	{1, 7},
	{-1, -1},
};

static struct edma_soc_info dm355_edma_info[] = {
	{
		.n_channel		= 64,
		.n_region		= 4,
		.n_slot			= 128,
		.n_tc			= 2,
		.n_cc			= 1,
		.noevent		= dma_chan_dm355_no_event,
		.queue_tc_mapping	= queue_tc_mapping,
		.queue_priority_mapping	= queue_priority_mapping,
	},
};

static struct resource edma_resources[] = {
	{
		.name	= "edma_cc0",
		.start	= 0x01c00000,
		.end	= 0x01c00000 + SZ_64K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc0",
		.start	= 0x01c10000,
		.end	= 0x01c10000 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc1",
		.start	= 0x01c10400,
		.end	= 0x01c10400 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma0",
		.start	= IRQ_CCINT0,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.name	= "edma0_err",
		.start	= IRQ_CCERRINT,
		.flags	= IORESOURCE_IRQ,
	},
	/* not using (or muxing) TC*_ERR */
};

static struct platform_device dm355_edma_device = {
	.name			= "edma",
	.id			= 0,
	.dev.platform_data	= dm355_edma_info,
	.num_resources		= ARRAY_SIZE(edma_resources),
	.resource		= edma_resources,
};

static struct resource dm355_asp1_resources[] = {
	{
		.start	= DAVINCI_ASP1_BASE,
		.end	= DAVINCI_ASP1_BASE + SZ_8K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= DAVINCI_DMA_ASP1_TX,
		.end	= DAVINCI_DMA_ASP1_TX,
		.flags	= IORESOURCE_DMA,
	},
	{
		.start	= DAVINCI_DMA_ASP1_RX,
		.end	= DAVINCI_DMA_ASP1_RX,
		.flags	= IORESOURCE_DMA,
	},
};

static struct platform_device dm355_asp1_device = {
	.name		= "davinci-asp",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(dm355_asp1_resources),
	.resource	= dm355_asp1_resources,
};

/*----------------------------------------------------------------------*/

static struct map_desc dm355_io_desc[] = {
	{
		.virtual	= IO_VIRT,
		.pfn		= __phys_to_pfn(IO_PHYS),
		.length		= IO_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= SRAM_VIRT,
		.pfn		= __phys_to_pfn(0x00010000),
		.length		= SZ_32K,
		/* MT_MEMORY_NONCACHED requires supersection alignment */
		.type		= MT_DEVICE,
	},
};

/* Contents of JTAG ID register used to identify exact cpu type */
static struct davinci_id dm355_ids[] = {
	{
		.variant	= 0x0,
		.part_no	= 0xb73b,
		.manufacturer	= 0x00f,
		.cpu_id		= DAVINCI_CPU_ID_DM355,
		.name		= "dm355",
	},
};

static void __iomem *dm355_psc_bases[] = {
	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
};

/*
 * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 * T1_TOP: Timer 1, top   :  <unused>
 */
struct davinci_timer_info dm355_timer_info = {
	.timers		= davinci_timer_instance,
	.clockevent_id	= T0_BOT,
	.clocksource_id	= T0_TOP,
};

static struct plat_serial8250_port dm355_serial_platform_data[] = {
	{
		.mapbase	= DAVINCI_UART0_BASE,
		.irq		= IRQ_UARTINT0,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
				  UPF_IOREMAP,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
	},
	{
		.mapbase	= DAVINCI_UART1_BASE,
		.irq		= IRQ_UARTINT1,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
				  UPF_IOREMAP,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
	},
	{
		.mapbase	= DM355_UART2_BASE,
		.irq		= IRQ_DM355_UARTINT2,
		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
				  UPF_IOREMAP,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
	},
	{
		.flags		= 0
	},
};

static struct platform_device dm355_serial_device = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= dm355_serial_platform_data,
	},
};

static struct davinci_soc_info davinci_soc_info_dm355 = {
	.io_desc		= dm355_io_desc,
	.io_desc_num		= ARRAY_SIZE(dm355_io_desc),
	.jtag_id_base		= IO_ADDRESS(0x01c40028),
	.ids			= dm355_ids,
	.ids_num		= ARRAY_SIZE(dm355_ids),
	.cpu_clks		= dm355_clks,
	.psc_bases		= dm355_psc_bases,
	.psc_bases_num		= ARRAY_SIZE(dm355_psc_bases),
	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
	.pinmux_pins		= dm355_pins,
	.pinmux_pins_num	= ARRAY_SIZE(dm355_pins),
	.intc_base		= IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
	.intc_type		= DAVINCI_INTC_TYPE_AINTC,
	.intc_irq_prios		= dm355_default_priorities,
	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
	.timer_info		= &dm355_timer_info,
	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
	.gpio_num		= 104,
	.gpio_irq		= IRQ_DM355_GPIOBNK0,
	.serial_dev		= &dm355_serial_device,
	.sram_dma		= 0x00010000,
	.sram_len		= SZ_32K,
};

void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
{
	/* we don't use ASP1 IRQs, or we'd need to mux them ... */
	if (evt_enable & ASP1_TX_EVT_EN)
		davinci_cfg_reg(DM355_EVT8_ASP1_TX);

	if (evt_enable & ASP1_RX_EVT_EN)
		davinci_cfg_reg(DM355_EVT9_ASP1_RX);

	dm355_asp1_device.dev.platform_data = pdata;
	platform_device_register(&dm355_asp1_device);
}

void __init dm355_init(void)
{
	davinci_common_init(&davinci_soc_info_dm355);
}

static int __init dm355_init_devices(void)
{
	if (!cpu_is_davinci_dm355())
		return 0;

	davinci_cfg_reg(DM355_INT_EDMA_CC);
	platform_device_register(&dm355_edma_device);
	return 0;
}
postcore_initcall(dm355_init_devices);
Commit	Line	Data
95a3477f KH	1	/*
	2	* TI DaVinci DM355 chip specific setup
	3	*
	4	* Author: Kevin Hilman, Deep Root Systems, LLC
	5	*
	6	* 2007 (c) Deep Root Systems, LLC. This file is licensed under
	7	* the terms of the GNU General Public License version 2. This program
	8	* is licensed "as is" without any warranty of any kind, whether express
	9	* or implied.
	10	*/
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/clk.h>
65e866a9	14	#include <linux/serial_8250.h>
95a3477f KH	15	#include <linux/platform_device.h>
95a3477f KH	16	#include <linux/dma-mapping.h>
a994955c	17	#include <linux/gpio.h>
95a3477f KH	18
	19	#include <linux/spi/spi.h>
	20
79c3c0b7 MG	21	#include <asm/mach/map.h>
79c3c0b7 MG	22
95a3477f KH	23	#include <mach/dm355.h>
	24	#include <mach/clock.h>
	25	#include <mach/cputype.h>
	26	#include <mach/edma.h>
	27	#include <mach/psc.h>
	28	#include <mach/mux.h>
	29	#include <mach/irqs.h>
f64691b3	30	#include <mach/time.h>
65e866a9	31	#include <mach/serial.h>
79c3c0b7	32	#include <mach/common.h>
25acf553	33	#include <mach/asp.h>
95a3477f KH	34
	35	#include "clock.h"
	36	#include "mux.h"
	37
96ed299f KH	38	#define DM355_UART2_BASE (IO_PHYS + 0x206000)
96ed299f KH	39
95a3477f KH	40	/*
	41	* Device specific clocks
	42	*/
	43	#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
	44
	45	static struct pll_data pll1_data = {
	46	.num = 1,
	47	.phys_base = DAVINCI_PLL1_BASE,
	48	.flags = PLL_HAS_PREDIV \| PLL_HAS_POSTDIV,
	49	};
	50
	51	static struct pll_data pll2_data = {
	52	.num = 2,
	53	.phys_base = DAVINCI_PLL2_BASE,
	54	.flags = PLL_HAS_PREDIV,
	55	};
	56
	57	static struct clk ref_clk = {
	58	.name = "ref_clk",
	59	/* FIXME -- crystal rate is board-specific */
	60	.rate = DM355_REF_FREQ,
	61	};
	62
	63	static struct clk pll1_clk = {
	64	.name = "pll1",
	65	.parent = &ref_clk,
	66	.flags = CLK_PLL,
	67	.pll_data = &pll1_data,
	68	};
	69
	70	static struct clk pll1_aux_clk = {
	71	.name = "pll1_aux_clk",
	72	.parent = &pll1_clk,
	73	.flags = CLK_PLL \| PRE_PLL,
	74	};
	75
	76	static struct clk pll1_sysclk1 = {
	77	.name = "pll1_sysclk1",
	78	.parent = &pll1_clk,
	79	.flags = CLK_PLL,
	80	.div_reg = PLLDIV1,
	81	};
	82
	83	static struct clk pll1_sysclk2 = {
	84	.name = "pll1_sysclk2",
	85	.parent = &pll1_clk,
	86	.flags = CLK_PLL,
	87	.div_reg = PLLDIV2,
	88	};
	89
	90	static struct clk pll1_sysclk3 = {
	91	.name = "pll1_sysclk3",
	92	.parent = &pll1_clk,
	93	.flags = CLK_PLL,
	94	.div_reg = PLLDIV3,
	95	};
	96
	97	static struct clk pll1_sysclk4 = {
	98	.name = "pll1_sysclk4",
	99	.parent = &pll1_clk,
	100	.flags = CLK_PLL,
	101	.div_reg = PLLDIV4,
	102	};
	103
104	static struct clk pll1_sysclkbp = {
105	.name = "pll1_sysclkbp",
106	.parent = &pll1_clk,
107	.flags = CLK_PLL \| PRE_PLL,
108	.div_reg = BPDIV
109	};
110
111	static struct clk vpss_dac_clk = {
112	.name = "vpss_dac",
113	.parent = &pll1_sysclk3,
114	.lpsc = DM355_LPSC_VPSS_DAC,
115	};
116
117	static struct clk vpss_master_clk = {
118	.name = "vpss_master",
119	.parent = &pll1_sysclk4,
120	.lpsc = DAVINCI_LPSC_VPSSMSTR,
121	.flags = CLK_PSC,
122	};
123
124	static struct clk vpss_slave_clk = {
125	.name = "vpss_slave",
126	.parent = &pll1_sysclk4,
127	.lpsc = DAVINCI_LPSC_VPSSSLV,
128	};
129
130
131	static struct clk clkout1_clk = {
132	.name = "clkout1",
133	.parent = &pll1_aux_clk,
134	/* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
135	};
136
137	static struct clk clkout2_clk = {
138	.name = "clkout2",
139	.parent = &pll1_sysclkbp,
140	};
141
142	static struct clk pll2_clk = {
143	.name = "pll2",
144	.parent = &ref_clk,
145	.flags = CLK_PLL,
146	.pll_data = &pll2_data,
147	};
148
149	static struct clk pll2_sysclk1 = {
150	.name = "pll2_sysclk1",
151	.parent = &pll2_clk,
152	.flags = CLK_PLL,
153	.div_reg = PLLDIV1,
154	};
155
156	static struct clk pll2_sysclkbp = {
157	.name = "pll2_sysclkbp",
158	.parent = &pll2_clk,
159	.flags = CLK_PLL \| PRE_PLL,
160	.div_reg = BPDIV
161	};
162
163	static struct clk clkout3_clk = {
164	.name = "clkout3",
165	.parent = &pll2_sysclkbp,
166	/* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
167	};
168
169	static struct clk arm_clk = {
170	.name = "arm_clk",
171	.parent = &pll1_sysclk1,
172	.lpsc = DAVINCI_LPSC_ARM,
173	.flags = ALWAYS_ENABLED,
174	};
175
176	/*
177	* NOT LISTED below, and not touched by Linux
178	* - in SyncReset state by default
179	* .lpsc = DAVINCI_LPSC_TPCC,
180	* .lpsc = DAVINCI_LPSC_TPTC0,
181	* .lpsc = DAVINCI_LPSC_TPTC1,
182	* .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
183	* .lpsc = DAVINCI_LPSC_MEMSTICK,
184	* - in Enabled state by default
185	* .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
186	* .lpsc = DAVINCI_LPSC_SCR2, // "bus"
187	* .lpsc = DAVINCI_LPSC_SCR3, // "bus"
188	* .lpsc = DAVINCI_LPSC_SCR4, // "bus"
189	* .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
190	* .lpsc = DAVINCI_LPSC_CFG27, // "test"
191	* .lpsc = DAVINCI_LPSC_CFG3, // "test"
192	* .lpsc = DAVINCI_LPSC_CFG5, // "test"
193	*/
194
195	static struct clk mjcp_clk = {
196	.name = "mjcp",
197	.parent = &pll1_sysclk1,
198	.lpsc = DAVINCI_LPSC_IMCOP,
199	};
200
201	static struct clk uart0_clk = {
202	.name = "uart0",
203	.parent = &pll1_aux_clk,
204	.lpsc = DAVINCI_LPSC_UART0,
205	};
206
207	static struct clk uart1_clk = {
208	.name = "uart1",
209	.parent = &pll1_aux_clk,
210	.lpsc = DAVINCI_LPSC_UART1,
211	};
212
213	static struct clk uart2_clk = {
214	.name = "uart2",
215	.parent = &pll1_sysclk2,
216	.lpsc = DAVINCI_LPSC_UART2,
217	};
218
219	static struct clk i2c_clk = {
220	.name = "i2c",
221	.parent = &pll1_aux_clk,
222	.lpsc = DAVINCI_LPSC_I2C,
223	};
224
225	static struct clk asp0_clk = {
226	.name = "asp0",
227	.parent = &pll1_sysclk2,
228	.lpsc = DAVINCI_LPSC_McBSP,
229	};
230
231	static struct clk asp1_clk = {
232	.name = "asp1",
233	.parent = &pll1_sysclk2,
234	.lpsc = DM355_LPSC_McBSP1,
235	};
236
237	static struct clk mmcsd0_clk = {
238	.name = "mmcsd0",
239	.parent = &pll1_sysclk2,
240	.lpsc = DAVINCI_LPSC_MMC_SD,
241	};
242
243	static struct clk mmcsd1_clk = {
244	.name = "mmcsd1",
245	.parent = &pll1_sysclk2,
246	.lpsc = DM355_LPSC_MMC_SD1,
247	};
248
249	static struct clk spi0_clk = {
250	.name = "spi0",
251	.parent = &pll1_sysclk2,
252	.lpsc = DAVINCI_LPSC_SPI,
253	};
254
255	static struct clk spi1_clk = {
256	.name = "spi1",
257	.parent = &pll1_sysclk2,
258	.lpsc = DM355_LPSC_SPI1,
259	};
260
261	static struct clk spi2_clk = {
262	.name = "spi2",
263	.parent = &pll1_sysclk2,
264	.lpsc = DM355_LPSC_SPI2,
265	};
266
267	static struct clk gpio_clk = {
268	.name = "gpio",
269	.parent = &pll1_sysclk2,
270	.lpsc = DAVINCI_LPSC_GPIO,
271	};
272
273	static struct clk aemif_clk = {
274	.name = "aemif",
275	.parent = &pll1_sysclk2,
276	.lpsc = DAVINCI_LPSC_AEMIF,
277	};
278
279	static struct clk pwm0_clk = {
280	.name = "pwm0",
281	.parent = &pll1_aux_clk,
282	.lpsc = DAVINCI_LPSC_PWM0,
283	};
284
285	static struct clk pwm1_clk = {
286	.name = "pwm1",
287	.parent = &pll1_aux_clk,
288	.lpsc = DAVINCI_LPSC_PWM1,
289	};
290
291	static struct clk pwm2_clk = {
292	.name = "pwm2",
293	.parent = &pll1_aux_clk,
294	.lpsc = DAVINCI_LPSC_PWM2,
295	};
296
297	static struct clk pwm3_clk = {
298	.name = "pwm3",
299	.parent = &pll1_aux_clk,
300	.lpsc = DM355_LPSC_PWM3,
301	};
302
303	static struct clk timer0_clk = {
304	.name = "timer0",
305	.parent = &pll1_aux_clk,
306	.lpsc = DAVINCI_LPSC_TIMER0,
307	};
308
309	static struct clk timer1_clk = {
310	.name = "timer1",
311	.parent = &pll1_aux_clk,
312	.lpsc = DAVINCI_LPSC_TIMER1,
313	};
314
315	static struct clk timer2_clk = {
316	.name = "timer2",
317	.parent = &pll1_aux_clk,
318	.lpsc = DAVINCI_LPSC_TIMER2,
319	.usecount = 1, /* REVISIT: why cant' this be disabled? */
320	};
321
322	static struct clk timer3_clk = {
323	.name = "timer3",
324	.parent = &pll1_aux_clk,
325	.lpsc = DM355_LPSC_TIMER3,
326	};
327
328	static struct clk rto_clk = {
329	.name = "rto",
330	.parent = &pll1_aux_clk,
331	.lpsc = DM355_LPSC_RTO,
332	};
333
334	static struct clk usb_clk = {
335	.name = "usb",
336	.parent = &pll1_sysclk2,
337	.lpsc = DAVINCI_LPSC_USB,
338	};
339
340	static struct davinci_clk dm355_clks[] = {
341	CLK(NULL, "ref", &ref_clk),
342	CLK(NULL, "pll1", &pll1_clk),
343	CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
344	CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
345	CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
346	CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
347	CLK(NULL, "pll1_aux", &pll1_aux_clk),
348	CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
349	CLK(NULL, "vpss_dac", &vpss_dac_clk),
350	CLK(NULL, "vpss_master", &vpss_master_clk),
351	CLK(NULL, "vpss_slave", &vpss_slave_clk),
352	CLK(NULL, "clkout1", &clkout1_clk),
353	CLK(NULL, "clkout2", &clkout2_clk),
354	CLK(NULL, "pll2", &pll2_clk),
355	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
356	CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
357	CLK(NULL, "clkout3", &clkout3_clk),
358	CLK(NULL, "arm", &arm_clk),
359	CLK(NULL, "mjcp", &mjcp_clk),
360	CLK(NULL, "uart0", &uart0_clk),
361	CLK(NULL, "uart1", &uart1_clk),
362	CLK(NULL, "uart2", &uart2_clk),
363	CLK("i2c_davinci.1", NULL, &i2c_clk),
25acf553 C	364	CLK(NULL, "asp0", &asp0_clk),
25acf553 C	365	CLK(NULL, "asp1", &asp1_clk),
95a3477f KH	366	CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
	367	CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
	368	CLK(NULL, "spi0", &spi0_clk),
	369	CLK(NULL, "spi1", &spi1_clk),
	370	CLK(NULL, "spi2", &spi2_clk),
	371	CLK(NULL, "gpio", &gpio_clk),
	372	CLK(NULL, "aemif", &aemif_clk),
	373	CLK(NULL, "pwm0", &pwm0_clk),
	374	CLK(NULL, "pwm1", &pwm1_clk),
	375	CLK(NULL, "pwm2", &pwm2_clk),
	376	CLK(NULL, "pwm3", &pwm3_clk),
	377	CLK(NULL, "timer0", &timer0_clk),
	378	CLK(NULL, "timer1", &timer1_clk),
	379	CLK("watchdog", NULL, &timer2_clk),
	380	CLK(NULL, "timer3", &timer3_clk),
	381	CLK(NULL, "rto", &rto_clk),
	382	CLK(NULL, "usb", &usb_clk),
	383	CLK(NULL, NULL, NULL),
	384	};
	385
	386	/----------------------------------------------------------------------/
	387
	388	static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
	389
	390	static struct resource dm355_spi0_resources[] = {
	391	{
	392	.start = 0x01c66000,
	393	.end = 0x01c667ff,
	394	.flags = IORESOURCE_MEM,
	395	},
	396	{
	397	.start = IRQ_DM355_SPINT0_1,
	398	.flags = IORESOURCE_IRQ,
	399	},
	400	/* Not yet used, so not included:
	401	* IORESOURCE_IRQ:
	402	* - IRQ_DM355_SPINT0_0
	403	* IORESOURCE_DMA:
	404	* - DAVINCI_DMA_SPI_SPIX
	405	* - DAVINCI_DMA_SPI_SPIR
	406	*/
	407	};
	408
	409	static struct platform_device dm355_spi0_device = {
	410	.name = "spi_davinci",
	411	.id = 0,
	412	.dev = {
	413	.dma_mask = &dm355_spi0_dma_mask,
	414	.coherent_dma_mask = DMA_BIT_MASK(32),
	415	},
	416	.num_resources = ARRAY_SIZE(dm355_spi0_resources),
	417	.resource = dm355_spi0_resources,
	418	};
	419
	420	void __init dm355_init_spi0(unsigned chipselect_mask,
	421	struct spi_board_info *info, unsigned len)
	422	{
	423	/* for now, assume we need MISO */
	424	davinci_cfg_reg(DM355_SPI0_SDI);
	425
	426	/* not all slaves will be wired up */
	427	if (chipselect_mask & BIT(0))
	428	davinci_cfg_reg(DM355_SPI0_SDENA0);
	429	if (chipselect_mask & BIT(1))
430	davinci_cfg_reg(DM355_SPI0_SDENA1);
431
432	spi_register_board_info(info, len);
433
434	platform_device_register(&dm355_spi0_device);
435	}
436
437	/----------------------------------------------------------------------/
438
5570078c MG	439	#define PINMUX0 0x00
	440	#define PINMUX1 0x04
	441	#define PINMUX2 0x08
	442	#define PINMUX3 0x0c
	443	#define PINMUX4 0x10
	444	#define INTMUX 0x18
	445	#define EVTMUX 0x1c
	446
95a3477f KH	447	/*
	448	* Device specific mux setup
	449	*
	450	* soc description mux mode mode mux dbg
	451	* reg offset mask mode
	452	*/
	453	static const struct mux_config dm355_pins[] = {
0e585952	454	#ifdef CONFIG_DAVINCI_MUX
95a3477f KH	455	MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
	456
	457	MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
	458	MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
	459	MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
	460	MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
	461	MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
	462	MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
	463
	464	MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
	465	MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
	466
	467	MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
	468	MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
	469	MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
	470	MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
	471	MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
	472	MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
	473
	474	MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
	475	MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
	476	MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
	477
	478	INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
	479	INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
	480	INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
	481
	482	EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
	483	EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
	484	EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
0e585952	485	#endif
95a3477f KH	486	};
95a3477f KH	487
673dd36f MG	488	static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
	489	[IRQ_DM355_CCDC_VDINT0] = 2,
	490	[IRQ_DM355_CCDC_VDINT1] = 6,
	491	[IRQ_DM355_CCDC_VDINT2] = 6,
	492	[IRQ_DM355_IPIPE_HST] = 6,
	493	[IRQ_DM355_H3AINT] = 6,
	494	[IRQ_DM355_IPIPE_SDR] = 6,
	495	[IRQ_DM355_IPIPEIFINT] = 6,
	496	[IRQ_DM355_OSDINT] = 7,
	497	[IRQ_DM355_VENCINT] = 6,
	498	[IRQ_ASQINT] = 6,
	499	[IRQ_IMXINT] = 6,
	500	[IRQ_USBINT] = 4,
	501	[IRQ_DM355_RTOINT] = 4,
	502	[IRQ_DM355_UARTINT2] = 7,
	503	[IRQ_DM355_TINT6] = 7,
	504	[IRQ_CCINT0] = 5, /* dma */
	505	[IRQ_CCERRINT] = 5, /* dma */
	506	[IRQ_TCERRINT0] = 5, /* dma */
	507	[IRQ_TCERRINT] = 5, /* dma */
	508	[IRQ_DM355_SPINT2_1] = 7,
	509	[IRQ_DM355_TINT7] = 4,
	510	[IRQ_DM355_SDIOINT0] = 7,
	511	[IRQ_MBXINT] = 7,
	512	[IRQ_MBRINT] = 7,
	513	[IRQ_MMCINT] = 7,
	514	[IRQ_DM355_MMCINT1] = 7,
	515	[IRQ_DM355_PWMINT3] = 7,
	516	[IRQ_DDRINT] = 7,
	517	[IRQ_AEMIFINT] = 7,
	518	[IRQ_DM355_SDIOINT1] = 4,
	519	[IRQ_TINT0_TINT12] = 2, /* clockevent */
	520	[IRQ_TINT0_TINT34] = 2, /* clocksource */
	521	[IRQ_TINT1_TINT12] = 7, /* DSP timer */
	522	[IRQ_TINT1_TINT34] = 7, /* system tick */
	523	[IRQ_PWMINT0] = 7,
	524	[IRQ_PWMINT1] = 7,
	525	[IRQ_PWMINT2] = 7,
	526	[IRQ_I2C] = 3,
	527	[IRQ_UARTINT0] = 3,
	528	[IRQ_UARTINT1] = 3,
	529	[IRQ_DM355_SPINT0_0] = 3,
	530	[IRQ_DM355_SPINT0_1] = 3,
	531	[IRQ_DM355_GPIO0] = 3,
	532	[IRQ_DM355_GPIO1] = 7,
	533	[IRQ_DM355_GPIO2] = 4,
	534	[IRQ_DM355_GPIO3] = 4,
	535	[IRQ_DM355_GPIO4] = 7,
	536	[IRQ_DM355_GPIO5] = 7,
	537	[IRQ_DM355_GPIO6] = 7,
	538	[IRQ_DM355_GPIO7] = 7,
	539	[IRQ_DM355_GPIO8] = 7,
	540	[IRQ_DM355_GPIO9] = 7,
	541	[IRQ_DM355_GPIOBNK0] = 7,
	542	[IRQ_DM355_GPIOBNK1] = 7,
	543	[IRQ_DM355_GPIOBNK2] = 7,
	544	[IRQ_DM355_GPIOBNK3] = 7,
	545	[IRQ_DM355_GPIOBNK4] = 7,
	546	[IRQ_DM355_GPIOBNK5] = 7,
	547	[IRQ_DM355_GPIOBNK6] = 7,
	548	[IRQ_COMMTX] = 7,
	549	[IRQ_COMMRX] = 7,
	550	[IRQ_EMUINT] = 7,
	551	};
552
95a3477f KH	553	/----------------------------------------------------------------------/
	554
	555	static const s8 dma_chan_dm355_no_event[] = {
	556	12, 13, 24, 56, 57,
	557	58, 59, 60, 61, 62,
	558	63,
	559	-1
	560	};
	561
60902a2c SR	562	static const s8
	563	queue_tc_mapping[][2] = {
	564	/* {event queue no, TC no} */
	565	{0, 0},
	566	{1, 1},
	567	{-1, -1},
	568	};
	569
	570	static const s8
	571	queue_priority_mapping[][2] = {
	572	/* {event queue no, Priority} */
	573	{0, 3},
	574	{1, 7},
	575	{-1, -1},
	576	};
	577
	578	static struct edma_soc_info dm355_edma_info[] = {
	579	{
	580	.n_channel = 64,
	581	.n_region = 4,
	582	.n_slot = 128,
	583	.n_tc = 2,
	584	.n_cc = 1,
	585	.noevent = dma_chan_dm355_no_event,
	586	.queue_tc_mapping = queue_tc_mapping,
	587	.queue_priority_mapping = queue_priority_mapping,
	588	},
95a3477f KH	589	};
	590
	591	static struct resource edma_resources[] = {
	592	{
60902a2c	593	.name = "edma_cc0",
95a3477f KH	594	.start = 0x01c00000,
	595	.end = 0x01c00000 + SZ_64K - 1,
	596	.flags = IORESOURCE_MEM,
	597	},
	598	{
	599	.name = "edma_tc0",
	600	.start = 0x01c10000,
	601	.end = 0x01c10000 + SZ_1K - 1,
	602	.flags = IORESOURCE_MEM,
	603	},
	604	{
	605	.name = "edma_tc1",
	606	.start = 0x01c10400,
	607	.end = 0x01c10400 + SZ_1K - 1,
	608	.flags = IORESOURCE_MEM,
	609	},
	610	{
60902a2c	611	.name = "edma0",
95a3477f KH	612	.start = IRQ_CCINT0,
	613	.flags = IORESOURCE_IRQ,
	614	},
	615	{
60902a2c	616	.name = "edma0_err",
95a3477f KH	617	.start = IRQ_CCERRINT,
	618	.flags = IORESOURCE_IRQ,
	619	},
	620	/* not using (or muxing) TC_ERR /
	621	};
	622
	623	static struct platform_device dm355_edma_device = {
	624	.name = "edma",
60902a2c SR	625	.id = 0,
60902a2c SR	626	.dev.platform_data = dm355_edma_info,
95a3477f KH	627	.num_resources = ARRAY_SIZE(edma_resources),
	628	.resource = edma_resources,
	629	};
	630
25acf553 C	631	static struct resource dm355_asp1_resources[] = {
	632	{
	633	.start = DAVINCI_ASP1_BASE,
	634	.end = DAVINCI_ASP1_BASE + SZ_8K - 1,
	635	.flags = IORESOURCE_MEM,
	636	},
	637	{
	638	.start = DAVINCI_DMA_ASP1_TX,
	639	.end = DAVINCI_DMA_ASP1_TX,
	640	.flags = IORESOURCE_DMA,
	641	},
	642	{
	643	.start = DAVINCI_DMA_ASP1_RX,
	644	.end = DAVINCI_DMA_ASP1_RX,
	645	.flags = IORESOURCE_DMA,
	646	},
	647	};
	648
	649	static struct platform_device dm355_asp1_device = {
	650	.name = "davinci-asp",
	651	.id = -1,
	652	.num_resources = ARRAY_SIZE(dm355_asp1_resources),
	653	.resource = dm355_asp1_resources,
	654	};
	655
95a3477f KH	656	/----------------------------------------------------------------------/
95a3477f KH	657
79c3c0b7 MG	658	static struct map_desc dm355_io_desc[] = {
	659	{
	660	.virtual = IO_VIRT,
	661	.pfn = __phys_to_pfn(IO_PHYS),
	662	.length = IO_SIZE,
	663	.type = MT_DEVICE
	664	},
0d04eb47 DB	665	{
	666	.virtual = SRAM_VIRT,
	667	.pfn = __phys_to_pfn(0x00010000),
	668	.length = SZ_32K,
	669	/* MT_MEMORY_NONCACHED requires supersection alignment */
	670	.type = MT_DEVICE,
	671	},
79c3c0b7 MG	672	};
79c3c0b7 MG	673
b9ab1279 MG	674	/* Contents of JTAG ID register used to identify exact cpu type */
	675	static struct davinci_id dm355_ids[] = {
	676	{
	677	.variant = 0x0,
	678	.part_no = 0xb73b,
	679	.manufacturer = 0x00f,
	680	.cpu_id = DAVINCI_CPU_ID_DM355,
	681	.name = "dm355",
	682	},
	683	};
	684
d81d188c MG	685	static void __iomem *dm355_psc_bases[] = {
	686	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
	687	};
	688
f64691b3 MG	689	/*
	690	* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
	691	* T0_TOP: Timer 0, top : clocksource for generic timekeeping
	692	* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
	693	* T1_TOP: Timer 1, top : <unused>
	694	*/
	695	struct davinci_timer_info dm355_timer_info = {
	696	.timers = davinci_timer_instance,
	697	.clockevent_id = T0_BOT,
	698	.clocksource_id = T0_TOP,
	699	};
	700
65e866a9 MG	701	static struct plat_serial8250_port dm355_serial_platform_data[] = {
	702	{
	703	.mapbase = DAVINCI_UART0_BASE,
	704	.irq = IRQ_UARTINT0,
	705	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|
	706	UPF_IOREMAP,
	707	.iotype = UPIO_MEM,
	708	.regshift = 2,
	709	},
	710	{
	711	.mapbase = DAVINCI_UART1_BASE,
	712	.irq = IRQ_UARTINT1,
	713	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|
	714	UPF_IOREMAP,
	715	.iotype = UPIO_MEM,
	716	.regshift = 2,
	717	},
	718	{
	719	.mapbase = DM355_UART2_BASE,
	720	.irq = IRQ_DM355_UARTINT2,
	721	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \|
	722	UPF_IOREMAP,
	723	.iotype = UPIO_MEM,
	724	.regshift = 2,
	725	},
	726	{
	727	.flags = 0
	728	},
	729	};
	730
	731	static struct platform_device dm355_serial_device = {
	732	.name = "serial8250",
	733	.id = PLAT8250_DEV_PLATFORM,
	734	.dev = {
	735	.platform_data = dm355_serial_platform_data,
	736	},
	737	};
	738
79c3c0b7 MG	739	static struct davinci_soc_info davinci_soc_info_dm355 = {
	740	.io_desc = dm355_io_desc,
	741	.io_desc_num = ARRAY_SIZE(dm355_io_desc),
b9ab1279 MG	742	.jtag_id_base = IO_ADDRESS(0x01c40028),
	743	.ids = dm355_ids,
	744	.ids_num = ARRAY_SIZE(dm355_ids),
66e0c399	745	.cpu_clks = dm355_clks,
d81d188c MG	746	.psc_bases = dm355_psc_bases,
d81d188c MG	747	.psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
0e585952 MG	748	.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
	749	.pinmux_pins = dm355_pins,
	750	.pinmux_pins_num = ARRAY_SIZE(dm355_pins),
673dd36f MG	751	.intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
	752	.intc_type = DAVINCI_INTC_TYPE_AINTC,
	753	.intc_irq_prios = dm355_default_priorities,
	754	.intc_irq_num = DAVINCI_N_AINTC_IRQ,
f64691b3	755	.timer_info = &dm355_timer_info,
a994955c MG	756	.gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
	757	.gpio_num = 104,
	758	.gpio_irq = IRQ_DM355_GPIOBNK0,
65e866a9	759	.serial_dev = &dm355_serial_device,
0d04eb47 DB	760	.sram_dma = 0x00010000,
0d04eb47 DB	761	.sram_len = SZ_32K,
79c3c0b7 MG	762	};
79c3c0b7 MG	763
25acf553 C	764	void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
	765	{
	766	/* we don't use ASP1 IRQs, or we'd need to mux them ... */
	767	if (evt_enable & ASP1_TX_EVT_EN)
	768	davinci_cfg_reg(DM355_EVT8_ASP1_TX);
	769
	770	if (evt_enable & ASP1_RX_EVT_EN)
	771	davinci_cfg_reg(DM355_EVT9_ASP1_RX);
	772
	773	dm355_asp1_device.dev.platform_data = pdata;
	774	platform_device_register(&dm355_asp1_device);
	775	}
	776
95a3477f KH	777	void __init dm355_init(void)
95a3477f KH	778	{
79c3c0b7	779	davinci_common_init(&davinci_soc_info_dm355);
95a3477f KH	780	}
	781
	782	static int __init dm355_init_devices(void)
	783	{
	784	if (!cpu_is_davinci_dm355())
	785	return 0;
	786
	787	davinci_cfg_reg(DM355_INT_EDMA_CC);
	788	platform_device_register(&dm355_edma_device);
	789	return 0;
	790	}
	791	postcore_initcall(dm355_init_devices);