]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - arch/arm/mach-davinci/dm365.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'docs-next' of git://git.lwn.net/linux-2.6
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-davinci / dm365.c
CommitLineData
fb8fcb89
SP		 1/*
2 * TI DaVinci DM365 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
fb8fcb89
SP		 15#include <linux/init.h>
16#include <linux/clk.h>
17#include <linux/serial_8250.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20#include <linux/gpio.h>
a3e13e89 21#include <linux/spi/spi.h>
fb8fcb89
SP		 22
23#include <asm/mach/map.h>
24
25#include <mach/dm365.h>
fb8fcb89
SP		 26#include <mach/cputype.h>
27#include <mach/edma.h>
28#include <mach/psc.h>
29#include <mach/mux.h>
30#include <mach/irqs.h>
31#include <mach/time.h>
32#include <mach/serial.h>
33#include <mach/common.h>
e9ab3214 34#include <mach/asp.h>
990c09d5 35#include <mach/keyscan.h>
a3e13e89
SP		 36#include <mach/spi.h>
37
fb8fcb89
SP		 38
39#include "clock.h"
40#include "mux.h"
41
42#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
43
44static struct pll_data pll1_data = {
45 .num = 1,
46 .phys_base = DAVINCI_PLL1_BASE,
47 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
48};
49
50static struct pll_data pll2_data = {
51 .num = 2,
52 .phys_base = DAVINCI_PLL2_BASE,
53 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
54};
55
56static struct clk ref_clk = {
57 .name = "ref_clk",
58 .rate = DM365_REF_FREQ,
59};
60
61static struct clk pll1_clk = {
62 .name = "pll1",
63 .parent = &ref_clk,
64 .flags = CLK_PLL,
65 .pll_data = &pll1_data,
66};
67
68static struct clk pll1_aux_clk = {
69 .name = "pll1_aux_clk",
70 .parent = &pll1_clk,
71 .flags = CLK_PLL | PRE_PLL,
72};
73
74static struct clk pll1_sysclkbp = {
75 .name = "pll1_sysclkbp",
76 .parent = &pll1_clk,
77 .flags = CLK_PLL | PRE_PLL,
78 .div_reg = BPDIV
79};
80
81static struct clk clkout0_clk = {
82 .name = "clkout0",
83 .parent = &pll1_clk,
84 .flags = CLK_PLL | PRE_PLL,
85};
86
87static struct clk pll1_sysclk1 = {
88 .name = "pll1_sysclk1",
89 .parent = &pll1_clk,
90 .flags = CLK_PLL,
91 .div_reg = PLLDIV1,
92};
93
94static struct clk pll1_sysclk2 = {
95 .name = "pll1_sysclk2",
96 .parent = &pll1_clk,
97 .flags = CLK_PLL,
98 .div_reg = PLLDIV2,
99};
100
101static struct clk pll1_sysclk3 = {
102 .name = "pll1_sysclk3",
103 .parent = &pll1_clk,
104 .flags = CLK_PLL,
105 .div_reg = PLLDIV3,
106};
107
108static struct clk pll1_sysclk4 = {
109 .name = "pll1_sysclk4",
110 .parent = &pll1_clk,
111 .flags = CLK_PLL,
112 .div_reg = PLLDIV4,
113};
114
115static struct clk pll1_sysclk5 = {
116 .name = "pll1_sysclk5",
117 .parent = &pll1_clk,
118 .flags = CLK_PLL,
119 .div_reg = PLLDIV5,
120};
121
122static struct clk pll1_sysclk6 = {
123 .name = "pll1_sysclk6",
124 .parent = &pll1_clk,
125 .flags = CLK_PLL,
126 .div_reg = PLLDIV6,
127};
128
129static struct clk pll1_sysclk7 = {
130 .name = "pll1_sysclk7",
131 .parent = &pll1_clk,
132 .flags = CLK_PLL,
133 .div_reg = PLLDIV7,
134};
135
136static struct clk pll1_sysclk8 = {
137 .name = "pll1_sysclk8",
138 .parent = &pll1_clk,
139 .flags = CLK_PLL,
140 .div_reg = PLLDIV8,
141};
142
143static struct clk pll1_sysclk9 = {
144 .name = "pll1_sysclk9",
145 .parent = &pll1_clk,
146 .flags = CLK_PLL,
147 .div_reg = PLLDIV9,
148};
149
150static struct clk pll2_clk = {
151 .name = "pll2",
152 .parent = &ref_clk,
153 .flags = CLK_PLL,
154 .pll_data = &pll2_data,
155};
156
157static struct clk pll2_aux_clk = {
158 .name = "pll2_aux_clk",
159 .parent = &pll2_clk,
160 .flags = CLK_PLL | PRE_PLL,
161};
162
163static struct clk clkout1_clk = {
164 .name = "clkout1",
165 .parent = &pll2_clk,
166 .flags = CLK_PLL | PRE_PLL,
167};
168
169static struct clk pll2_sysclk1 = {
170 .name = "pll2_sysclk1",
171 .parent = &pll2_clk,
172 .flags = CLK_PLL,
173 .div_reg = PLLDIV1,
174};
175
176static struct clk pll2_sysclk2 = {
177 .name = "pll2_sysclk2",
178 .parent = &pll2_clk,
179 .flags = CLK_PLL,
180 .div_reg = PLLDIV2,
181};
182
183static struct clk pll2_sysclk3 = {
184 .name = "pll2_sysclk3",
185 .parent = &pll2_clk,
186 .flags = CLK_PLL,
187 .div_reg = PLLDIV3,
188};
189
190static struct clk pll2_sysclk4 = {
191 .name = "pll2_sysclk4",
192 .parent = &pll2_clk,
193 .flags = CLK_PLL,
194 .div_reg = PLLDIV4,
195};
196
197static struct clk pll2_sysclk5 = {
198 .name = "pll2_sysclk5",
199 .parent = &pll2_clk,
200 .flags = CLK_PLL,
201 .div_reg = PLLDIV5,
202};
203
204static struct clk pll2_sysclk6 = {
205 .name = "pll2_sysclk6",
206 .parent = &pll2_clk,
207 .flags = CLK_PLL,
208 .div_reg = PLLDIV6,
209};
210
211static struct clk pll2_sysclk7 = {
212 .name = "pll2_sysclk7",
213 .parent = &pll2_clk,
214 .flags = CLK_PLL,
215 .div_reg = PLLDIV7,
216};
217
218static struct clk pll2_sysclk8 = {
219 .name = "pll2_sysclk8",
220 .parent = &pll2_clk,
221 .flags = CLK_PLL,
222 .div_reg = PLLDIV8,
223};
224
225static struct clk pll2_sysclk9 = {
226 .name = "pll2_sysclk9",
227 .parent = &pll2_clk,
228 .flags = CLK_PLL,
229 .div_reg = PLLDIV9,
230};
231
232static struct clk vpss_dac_clk = {
233 .name = "vpss_dac",
234 .parent = &pll1_sysclk3,
235 .lpsc = DM365_LPSC_DAC_CLK,
236};
237
238static struct clk vpss_master_clk = {
239 .name = "vpss_master",
240 .parent = &pll1_sysclk5,
241 .lpsc = DM365_LPSC_VPSSMSTR,
242 .flags = CLK_PSC,
243};
244
245static struct clk arm_clk = {
246 .name = "arm_clk",
247 .parent = &pll2_sysclk2,
248 .lpsc = DAVINCI_LPSC_ARM,
249 .flags = ALWAYS_ENABLED,
250};
251
252static struct clk uart0_clk = {
253 .name = "uart0",
254 .parent = &pll1_aux_clk,
255 .lpsc = DAVINCI_LPSC_UART0,
256};
257
258static struct clk uart1_clk = {
259 .name = "uart1",
260 .parent = &pll1_sysclk4,
261 .lpsc = DAVINCI_LPSC_UART1,
262};
263
264static struct clk i2c_clk = {
265 .name = "i2c",
266 .parent = &pll1_aux_clk,
267 .lpsc = DAVINCI_LPSC_I2C,
268};
269
270static struct clk mmcsd0_clk = {
271 .name = "mmcsd0",
272 .parent = &pll1_sysclk8,
273 .lpsc = DAVINCI_LPSC_MMC_SD,
274};
275
276static struct clk mmcsd1_clk = {
277 .name = "mmcsd1",
278 .parent = &pll1_sysclk4,
279 .lpsc = DM365_LPSC_MMC_SD1,
280};
281
282static struct clk spi0_clk = {
283 .name = "spi0",
284 .parent = &pll1_sysclk4,
285 .lpsc = DAVINCI_LPSC_SPI,
286};
287
288static struct clk spi1_clk = {
289 .name = "spi1",
290 .parent = &pll1_sysclk4,
291 .lpsc = DM365_LPSC_SPI1,
292};
293
294static struct clk spi2_clk = {
295 .name = "spi2",
296 .parent = &pll1_sysclk4,
297 .lpsc = DM365_LPSC_SPI2,
298};
299
300static struct clk spi3_clk = {
301 .name = "spi3",
302 .parent = &pll1_sysclk4,
303 .lpsc = DM365_LPSC_SPI3,
304};
305
306static struct clk spi4_clk = {
307 .name = "spi4",
308 .parent = &pll1_aux_clk,
309 .lpsc = DM365_LPSC_SPI4,
310};
311
312static struct clk gpio_clk = {
313 .name = "gpio",
314 .parent = &pll1_sysclk4,
315 .lpsc = DAVINCI_LPSC_GPIO,
316};
317
318static struct clk aemif_clk = {
319 .name = "aemif",
320 .parent = &pll1_sysclk4,
321 .lpsc = DAVINCI_LPSC_AEMIF,
322};
323
324static struct clk pwm0_clk = {
325 .name = "pwm0",
326 .parent = &pll1_aux_clk,
327 .lpsc = DAVINCI_LPSC_PWM0,
328};
329
330static struct clk pwm1_clk = {
331 .name = "pwm1",
332 .parent = &pll1_aux_clk,
333 .lpsc = DAVINCI_LPSC_PWM1,
334};
335
336static struct clk pwm2_clk = {
337 .name = "pwm2",
338 .parent = &pll1_aux_clk,
339 .lpsc = DAVINCI_LPSC_PWM2,
340};
341
342static struct clk pwm3_clk = {
343 .name = "pwm3",
344 .parent = &ref_clk,
345 .lpsc = DM365_LPSC_PWM3,
346};
347
348static struct clk timer0_clk = {
349 .name = "timer0",
350 .parent = &pll1_aux_clk,
351 .lpsc = DAVINCI_LPSC_TIMER0,
352};
353
354static struct clk timer1_clk = {
355 .name = "timer1",
356 .parent = &pll1_aux_clk,
357 .lpsc = DAVINCI_LPSC_TIMER1,
358};
359
360static struct clk timer2_clk = {
361 .name = "timer2",
362 .parent = &pll1_aux_clk,
363 .lpsc = DAVINCI_LPSC_TIMER2,
364 .usecount = 1,
365};
366
367static struct clk timer3_clk = {
368 .name = "timer3",
369 .parent = &pll1_aux_clk,
370 .lpsc = DM365_LPSC_TIMER3,
371};
372
373static struct clk usb_clk = {
374 .name = "usb",
ed160672 375 .parent = &pll1_aux_clk,
fb8fcb89
SP		 376 .lpsc = DAVINCI_LPSC_USB,
377};
378
379static struct clk emac_clk = {
380 .name = "emac",
381 .parent = &pll1_sysclk4,
382 .lpsc = DM365_LPSC_EMAC,
383};
384
385static struct clk voicecodec_clk = {
386 .name = "voice_codec",
387 .parent = &pll2_sysclk4,
388 .lpsc = DM365_LPSC_VOICE_CODEC,
389};
390
391static struct clk asp0_clk = {
392 .name = "asp0",
393 .parent = &pll1_sysclk4,
394 .lpsc = DM365_LPSC_McBSP1,
395};
396
397static struct clk rto_clk = {
398 .name = "rto",
399 .parent = &pll1_sysclk4,
400 .lpsc = DM365_LPSC_RTO,
401};
402
403static struct clk mjcp_clk = {
404 .name = "mjcp",
405 .parent = &pll1_sysclk3,
406 .lpsc = DM365_LPSC_MJCP,
407};
408
08aca087 409static struct clk_lookup dm365_clks[] = {
fb8fcb89
SP		 410 CLK(NULL, "ref", &ref_clk),
411 CLK(NULL, "pll1", &pll1_clk),
412 CLK(NULL, "pll1_aux", &pll1_aux_clk),
413 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
414 CLK(NULL, "clkout0", &clkout0_clk),
415 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
416 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
417 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
418 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
419 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
420 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
421 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
422 CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
423 CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
424 CLK(NULL, "pll2", &pll2_clk),
425 CLK(NULL, "pll2_aux", &pll2_aux_clk),
426 CLK(NULL, "clkout1", &clkout1_clk),
427 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
428 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
429 CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
430 CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
431 CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
432 CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
433 CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
434 CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
435 CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
436 CLK(NULL, "vpss_dac", &vpss_dac_clk),
437 CLK(NULL, "vpss_master", &vpss_master_clk),
438 CLK(NULL, "arm", &arm_clk),
439 CLK(NULL, "uart0", &uart0_clk),
440 CLK(NULL, "uart1", &uart1_clk),
441 CLK("i2c_davinci.1", NULL, &i2c_clk),
442 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
443 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
444 CLK("spi_davinci.0", NULL, &spi0_clk),
445 CLK("spi_davinci.1", NULL, &spi1_clk),
446 CLK("spi_davinci.2", NULL, &spi2_clk),
447 CLK("spi_davinci.3", NULL, &spi3_clk),
448 CLK("spi_davinci.4", NULL, &spi4_clk),
449 CLK(NULL, "gpio", &gpio_clk),
450 CLK(NULL, "aemif", &aemif_clk),
451 CLK(NULL, "pwm0", &pwm0_clk),
452 CLK(NULL, "pwm1", &pwm1_clk),
453 CLK(NULL, "pwm2", &pwm2_clk),
454 CLK(NULL, "pwm3", &pwm3_clk),
455 CLK(NULL, "timer0", &timer0_clk),
456 CLK(NULL, "timer1", &timer1_clk),
457 CLK("watchdog", NULL, &timer2_clk),
458 CLK(NULL, "timer3", &timer3_clk),
459 CLK(NULL, "usb", &usb_clk),
460 CLK("davinci_emac.1", NULL, &emac_clk),
e89861e9 461 CLK("davinci_voicecodec", NULL, &voicecodec_clk),
e9ab3214 462 CLK("davinci-asp.0", NULL, &asp0_clk),
fb8fcb89
SP		 463 CLK(NULL, "rto", &rto_clk),
464 CLK(NULL, "mjcp", &mjcp_clk),
465 CLK(NULL, NULL, NULL),
466};
467
468/*----------------------------------------------------------------------*/
469
fb8fcb89
SP		 470#define INTMUX 0x18
471#define EVTMUX 0x1c
472
473
474static const struct mux_config dm365_pins[] = {
475#ifdef CONFIG_DAVINCI_MUX
476MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
477
478MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
479MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
480MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
481MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
482MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
483MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
484
485MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
486MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
487
7735227e
TK		 488MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
489MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
fb8fcb89
SP		 490MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
491MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
492MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
493MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
7735227e
TK		 494MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
495MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
fb8fcb89
SP		 496
497MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
498MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
499MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
500MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
501MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
502MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
503
504MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
505MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
506MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
507MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
508MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
509
510MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
511MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
512MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
513MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
514MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
515MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
516
517MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
518MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
519MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
520MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
521MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
522MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
523MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
524MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
525MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
526MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
527MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
528MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
529MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
530MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
531MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
532MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
533MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
9f513153 534
990c09d5 535MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
9f513153 536
af5dbaef
SP		 537MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
538MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
539MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false)
540MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false)
541MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false)
542MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false)
543MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false)
544MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false)
545MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false)
546MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false)
547MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false)
548MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false)
549
550MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false)
551MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false)
552MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
553MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false)
554MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
555
556MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false)
557MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false)
558MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false)
559MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false)
560MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false)
561
562MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
563MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
564MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
565MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
566MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
567
568MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false)
569MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false)
570MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
571MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
572MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
573
0efe2b74
TK		 574MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
575MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
576MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
577
af5dbaef 578MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
2168e76d
TK		 579MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
580MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
581MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
af5dbaef
SP		 582MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
583MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
ce100669 584MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
af5dbaef
SP		 585
586MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
587MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
588MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
589MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
590MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
591MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
592MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
593MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
866d2869
SP		 594MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false)
595MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false)
af5dbaef 596
9f513153
SP		 597INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false)
598INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false)
599INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false)
600INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false)
601INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
602INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
603INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
604INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
605INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
606INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
0c30e0d3
SP		 607INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
608INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
609INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
610INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
611INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
612INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
613INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
614INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
e9ab3214
MA		 615
616EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
617EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
e89861e9
MA		 618EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
619EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
fb8fcb89
SP		 620#endif
621};
622
a3e13e89
SP		 623static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
624
625static struct davinci_spi_platform_data dm365_spi0_pdata = {
626 .version = SPI_VERSION_1,
627 .num_chipselect = 2,
628 .clk_internal = 1,
629 .cs_hold = 1,
630 .intr_level = 0,
631 .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
632 .c2tdelay = 0,
633 .t2cdelay = 0,
634};
635
636static struct resource dm365_spi0_resources[] = {
637 {
638 .start = 0x01c66000,
639 .end = 0x01c667ff,
640 .flags = IORESOURCE_MEM,
641 },
642 {
643 .start = IRQ_DM365_SPIINT0_0,
644 .flags = IORESOURCE_IRQ,
645 },
646 {
647 .start = 17,
648 .flags = IORESOURCE_DMA,
649 },
650 {
651 .start = 16,
652 .flags = IORESOURCE_DMA,
653 },
654 {
655 .start = EVENTQ_3,
656 .flags = IORESOURCE_DMA,
657 },
658};
659
660static struct platform_device dm365_spi0_device = {
661 .name = "spi_davinci",
662 .id = 0,
663 .dev = {
664 .dma_mask = &dm365_spi0_dma_mask,
665 .coherent_dma_mask = DMA_BIT_MASK(32),
666 .platform_data = &dm365_spi0_pdata,
667 },
668 .num_resources = ARRAY_SIZE(dm365_spi0_resources),
669 .resource = dm365_spi0_resources,
670};
671
672void __init dm365_init_spi0(unsigned chipselect_mask,
673 struct spi_board_info *info, unsigned len)
674{
675 davinci_cfg_reg(DM365_SPI0_SCLK);
676 davinci_cfg_reg(DM365_SPI0_SDI);
677 davinci_cfg_reg(DM365_SPI0_SDO);
678
679 /* not all slaves will be wired up */
680 if (chipselect_mask & BIT(0))
681 davinci_cfg_reg(DM365_SPI0_SDENA0);
682 if (chipselect_mask & BIT(1))
683 davinci_cfg_reg(DM365_SPI0_SDENA1);
684
685 spi_register_board_info(info, len);
686
687 platform_device_register(&dm365_spi0_device);
688}
689
8ed0a9d4
SP		 690static struct emac_platform_data dm365_emac_pdata = {
691 .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
692 .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
693 .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
694 .mdio_reg_offset = DM365_EMAC_MDIO_OFFSET,
695 .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
696 .version = EMAC_VERSION_2,
697};
698
699static struct resource dm365_emac_resources[] = {
700 {
701 .start = DM365_EMAC_BASE,
702 .end = DM365_EMAC_BASE + 0x47ff,
703 .flags = IORESOURCE_MEM,
704 },
705 {
706 .start = IRQ_DM365_EMAC_RXTHRESH,
707 .end = IRQ_DM365_EMAC_RXTHRESH,
708 .flags = IORESOURCE_IRQ,
709 },
710 {
711 .start = IRQ_DM365_EMAC_RXPULSE,
712 .end = IRQ_DM365_EMAC_RXPULSE,
713 .flags = IORESOURCE_IRQ,
714 },
715 {
716 .start = IRQ_DM365_EMAC_TXPULSE,
717 .end = IRQ_DM365_EMAC_TXPULSE,
718 .flags = IORESOURCE_IRQ,
719 },
720 {
721 .start = IRQ_DM365_EMAC_MISCPULSE,
722 .end = IRQ_DM365_EMAC_MISCPULSE,
723 .flags = IORESOURCE_IRQ,
724 },
725};
726
727static struct platform_device dm365_emac_device = {
728 .name = "davinci_emac",
729 .id = 1,
730 .dev = {
731 .platform_data = &dm365_emac_pdata,
732 },
733 .num_resources = ARRAY_SIZE(dm365_emac_resources),
734 .resource = dm365_emac_resources,
735};
fb8fcb89
SP		 736
737static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
738 [IRQ_VDINT0] = 2,
739 [IRQ_VDINT1] = 6,
740 [IRQ_VDINT2] = 6,
741 [IRQ_HISTINT] = 6,
742 [IRQ_H3AINT] = 6,
743 [IRQ_PRVUINT] = 6,
744 [IRQ_RSZINT] = 6,
745 [IRQ_DM365_INSFINT] = 7,
746 [IRQ_VENCINT] = 6,
747 [IRQ_ASQINT] = 6,
748 [IRQ_IMXINT] = 6,
749 [IRQ_DM365_IMCOPINT] = 4,
750 [IRQ_USBINT] = 4,
751 [IRQ_DM365_RTOINT] = 7,
752 [IRQ_DM365_TINT5] = 7,
753 [IRQ_DM365_TINT6] = 5,
754 [IRQ_CCINT0] = 5,
755 [IRQ_CCERRINT] = 5,
756 [IRQ_TCERRINT0] = 5,
757 [IRQ_TCERRINT] = 7,
758 [IRQ_PSCIN] = 4,
759 [IRQ_DM365_SPINT2_1] = 7,
760 [IRQ_DM365_TINT7] = 7,
761 [IRQ_DM365_SDIOINT0] = 7,
762 [IRQ_MBXINT] = 7,
763 [IRQ_MBRINT] = 7,
764 [IRQ_MMCINT] = 7,
765 [IRQ_DM365_MMCINT1] = 7,
766 [IRQ_DM365_PWMINT3] = 7,
fb8fcb89
SP		 767 [IRQ_AEMIFINT] = 2,
768 [IRQ_DM365_SDIOINT1] = 2,
769 [IRQ_TINT0_TINT12] = 7,
770 [IRQ_TINT0_TINT34] = 7,
771 [IRQ_TINT1_TINT12] = 7,
772 [IRQ_TINT1_TINT34] = 7,
773 [IRQ_PWMINT0] = 7,
774 [IRQ_PWMINT1] = 3,
775 [IRQ_PWMINT2] = 3,
776 [IRQ_I2C] = 3,
777 [IRQ_UARTINT0] = 3,
778 [IRQ_UARTINT1] = 3,
99381b4f 779 [IRQ_DM365_RTCINT] = 3,
fb8fcb89
SP		 780 [IRQ_DM365_SPIINT0_0] = 3,
781 [IRQ_DM365_SPIINT3_0] = 3,
782 [IRQ_DM365_GPIO0] = 3,
783 [IRQ_DM365_GPIO1] = 7,
784 [IRQ_DM365_GPIO2] = 4,
785 [IRQ_DM365_GPIO3] = 4,
786 [IRQ_DM365_GPIO4] = 7,
787 [IRQ_DM365_GPIO5] = 7,
788 [IRQ_DM365_GPIO6] = 7,
789 [IRQ_DM365_GPIO7] = 7,
790 [IRQ_DM365_EMAC_RXTHRESH] = 7,
791 [IRQ_DM365_EMAC_RXPULSE] = 7,
792 [IRQ_DM365_EMAC_TXPULSE] = 7,
793 [IRQ_DM365_EMAC_MISCPULSE] = 7,
794 [IRQ_DM365_GPIO12] = 7,
795 [IRQ_DM365_GPIO13] = 7,
796 [IRQ_DM365_GPIO14] = 7,
797 [IRQ_DM365_GPIO15] = 7,
798 [IRQ_DM365_KEYINT] = 7,
799 [IRQ_DM365_TCERRINT2] = 7,
800 [IRQ_DM365_TCERRINT3] = 7,
801 [IRQ_DM365_EMUINT] = 7,
802};
803
15061b5d
SP		 804/* Four Transfer Controllers on DM365 */
805static const s8
806dm365_queue_tc_mapping[][2] = {
807 /* {event queue no, TC no} */
808 {0, 0},
809 {1, 1},
810 {2, 2},
811 {3, 3},
812 {-1, -1},
813};
814
815static const s8
816dm365_queue_priority_mapping[][2] = {
817 /* {event queue no, Priority} */
818 {0, 7},
819 {1, 7},
820 {2, 7},
821 {3, 0},
822 {-1, -1},
823};
824
825static struct edma_soc_info dm365_edma_info[] = {
826 {
827 .n_channel = 64,
828 .n_region = 4,
829 .n_slot = 256,
830 .n_tc = 4,
831 .n_cc = 1,
832 .queue_tc_mapping = dm365_queue_tc_mapping,
833 .queue_priority_mapping = dm365_queue_priority_mapping,
7307d093 834 .default_queue = EVENTQ_3,
15061b5d
SP		 835 },
836};
837
838static struct resource edma_resources[] = {
839 {
840 .name = "edma_cc0",
841 .start = 0x01c00000,
842 .end = 0x01c00000 + SZ_64K - 1,
843 .flags = IORESOURCE_MEM,
844 },
845 {
846 .name = "edma_tc0",
847 .start = 0x01c10000,
848 .end = 0x01c10000 + SZ_1K - 1,
849 .flags = IORESOURCE_MEM,
850 },
851 {
852 .name = "edma_tc1",
853 .start = 0x01c10400,
854 .end = 0x01c10400 + SZ_1K - 1,
855 .flags = IORESOURCE_MEM,
856 },
857 {
858 .name = "edma_tc2",
859 .start = 0x01c10800,
860 .end = 0x01c10800 + SZ_1K - 1,
861 .flags = IORESOURCE_MEM,
862 },
863 {
864 .name = "edma_tc3",
865 .start = 0x01c10c00,
866 .end = 0x01c10c00 + SZ_1K - 1,
867 .flags = IORESOURCE_MEM,
868 },
869 {
870 .name = "edma0",
871 .start = IRQ_CCINT0,
872 .flags = IORESOURCE_IRQ,
873 },
874 {
875 .name = "edma0_err",
876 .start = IRQ_CCERRINT,
877 .flags = IORESOURCE_IRQ,
878 },
879 /* not using TC*_ERR */
880};
881
882static struct platform_device dm365_edma_device = {
883 .name = "edma",
884 .id = 0,
885 .dev.platform_data = dm365_edma_info,
886 .num_resources = ARRAY_SIZE(edma_resources),
887 .resource = edma_resources,
888};
889
e9ab3214
MA		 890static struct resource dm365_asp_resources[] = {
891 {
892 .start = DAVINCI_DM365_ASP0_BASE,
893 .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
894 .flags = IORESOURCE_MEM,
895 },
896 {
897 .start = DAVINCI_DMA_ASP0_TX,
898 .end = DAVINCI_DMA_ASP0_TX,
899 .flags = IORESOURCE_DMA,
900 },
901 {
902 .start = DAVINCI_DMA_ASP0_RX,
903 .end = DAVINCI_DMA_ASP0_RX,
904 .flags = IORESOURCE_DMA,
905 },
906};
907
908static struct platform_device dm365_asp_device = {
909 .name = "davinci-asp",
910 .id = 0,
911 .num_resources = ARRAY_SIZE(dm365_asp_resources),
912 .resource = dm365_asp_resources,
913};
914
e89861e9
MA		 915static struct resource dm365_vc_resources[] = {
916 {
917 .start = DAVINCI_DM365_VC_BASE,
918 .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
919 .flags = IORESOURCE_MEM,
920 },
921 {
922 .start = DAVINCI_DMA_VC_TX,
923 .end = DAVINCI_DMA_VC_TX,
924 .flags = IORESOURCE_DMA,
925 },
926 {
927 .start = DAVINCI_DMA_VC_RX,
928 .end = DAVINCI_DMA_VC_RX,
929 .flags = IORESOURCE_DMA,
930 },
931};
932
933static struct platform_device dm365_vc_device = {
934 .name = "davinci_voicecodec",
935 .id = -1,
936 .num_resources = ARRAY_SIZE(dm365_vc_resources),
937 .resource = dm365_vc_resources,
938};
939
99381b4f
MA		 940static struct resource dm365_rtc_resources[] = {
941 {
942 .start = DM365_RTC_BASE,
943 .end = DM365_RTC_BASE + SZ_1K - 1,
944 .flags = IORESOURCE_MEM,
945 },
946 {
947 .start = IRQ_DM365_RTCINT,
948 .flags = IORESOURCE_IRQ,
949 },
950};
951
952static struct platform_device dm365_rtc_device = {
953 .name = "rtc_davinci",
954 .id = 0,
955 .num_resources = ARRAY_SIZE(dm365_rtc_resources),
956 .resource = dm365_rtc_resources,
957};
958
fb8fcb89
SP		 959static struct map_desc dm365_io_desc[] = {
960 {
961 .virtual = IO_VIRT,
962 .pfn = __phys_to_pfn(IO_PHYS),
963 .length = IO_SIZE,
964 .type = MT_DEVICE
965 },
966 {
967 .virtual = SRAM_VIRT,
968 .pfn = __phys_to_pfn(0x00010000),
969 .length = SZ_32K,
970 /* MT_MEMORY_NONCACHED requires supersection alignment */
971 .type = MT_DEVICE,
972 },
973};
974
990c09d5
MA		 975static struct resource dm365_ks_resources[] = {
976 {
977 /* registers */
978 .start = DM365_KEYSCAN_BASE,
979 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
980 .flags = IORESOURCE_MEM,
981 },
982 {
983 /* interrupt */
984 .start = IRQ_DM365_KEYINT,
985 .end = IRQ_DM365_KEYINT,
986 .flags = IORESOURCE_IRQ,
987 },
988};
989
990static struct platform_device dm365_ks_device = {
991 .name = "davinci_keyscan",
992 .id = 0,
993 .num_resources = ARRAY_SIZE(dm365_ks_resources),
994 .resource = dm365_ks_resources,
995};
996
fb8fcb89
SP		 997/* Contents of JTAG ID register used to identify exact cpu type */
998static struct davinci_id dm365_ids[] = {
999 {
1000 .variant = 0x0,
1001 .part_no = 0xb83e,
1002 .manufacturer = 0x017,
1003 .cpu_id = DAVINCI_CPU_ID_DM365,
cc36e97b
SP		 1004 .name = "dm365_rev1.1",
1005 },
1006 {
1007 .variant = 0x8,
1008 .part_no = 0xb83e,
1009 .manufacturer = 0x017,
1010 .cpu_id = DAVINCI_CPU_ID_DM365,
1011 .name = "dm365_rev1.2",
fb8fcb89
SP		 1012 },
1013};
1014
e4c822c7 1015static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
fb8fcb89 1016
28552c2e 1017static struct davinci_timer_info dm365_timer_info = {
fb8fcb89
SP		 1018 .timers = davinci_timer_instance,
1019 .clockevent_id = T0_BOT,
1020 .clocksource_id = T0_TOP,
1021};
1022
1023static struct plat_serial8250_port dm365_serial_platform_data[] = {
1024 {
1025 .mapbase = DAVINCI_UART0_BASE,
1026 .irq = IRQ_UARTINT0,
1027 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1028 UPF_IOREMAP,
1029 .iotype = UPIO_MEM,
1030 .regshift = 2,
1031 },
1032 {
1033 .mapbase = DAVINCI_UART1_BASE,
1034 .irq = IRQ_UARTINT1,
1035 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1036 UPF_IOREMAP,
1037 .iotype = UPIO_MEM,
1038 .regshift = 2,
1039 },
1040 {
1041 .flags = 0
1042 },
1043};
1044
1045static struct platform_device dm365_serial_device = {
1046 .name = "serial8250",
1047 .id = PLAT8250_DEV_PLATFORM,
1048 .dev = {
1049 .platform_data = dm365_serial_platform_data,
1050 },
1051};
1052
1053static struct davinci_soc_info davinci_soc_info_dm365 = {
1054 .io_desc = dm365_io_desc,
1055 .io_desc_num = ARRAY_SIZE(dm365_io_desc),
3347db83 1056 .jtag_id_reg = 0x01c40028,
fb8fcb89
SP		 1057 .ids = dm365_ids,
1058 .ids_num = ARRAY_SIZE(dm365_ids),
1059 .cpu_clks = dm365_clks,
1060 .psc_bases = dm365_psc_bases,
1061 .psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
779b0d53 1062 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
fb8fcb89
SP		 1063 .pinmux_pins = dm365_pins,
1064 .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
bd808947 1065 .intc_base = DAVINCI_ARM_INTC_BASE,
fb8fcb89
SP		 1066 .intc_type = DAVINCI_INTC_TYPE_AINTC,
1067 .intc_irq_prios = dm365_default_priorities,
1068 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
1069 .timer_info = &dm365_timer_info,
686b634a 1070 .gpio_type = GPIO_TYPE_DAVINCI,
b8d44293 1071 .gpio_base = DAVINCI_GPIO_BASE,
fb8fcb89 1072 .gpio_num = 104,
7a36071e
DB		 1073 .gpio_irq = IRQ_DM365_GPIO0,
1074 .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */
fb8fcb89 1075 .serial_dev = &dm365_serial_device,
8ed0a9d4 1076 .emac_pdata = &dm365_emac_pdata,
fb8fcb89
SP		 1077 .sram_dma = 0x00010000,
1078 .sram_len = SZ_32K,
c78a5bc2 1079 .reset_device = &davinci_wdt_device,
fb8fcb89
SP		 1080};
1081
e9ab3214
MA		 1082void __init dm365_init_asp(struct snd_platform_data *pdata)
1083{
1084 davinci_cfg_reg(DM365_MCBSP0_BDX);
1085 davinci_cfg_reg(DM365_MCBSP0_X);
1086 davinci_cfg_reg(DM365_MCBSP0_BFSX);
1087 davinci_cfg_reg(DM365_MCBSP0_BDR);
1088 davinci_cfg_reg(DM365_MCBSP0_R);
1089 davinci_cfg_reg(DM365_MCBSP0_BFSR);
1090 davinci_cfg_reg(DM365_EVT2_ASP_TX);
1091 davinci_cfg_reg(DM365_EVT3_ASP_RX);
1092 dm365_asp_device.dev.platform_data = pdata;
1093 platform_device_register(&dm365_asp_device);
1094}
1095
e89861e9
MA		 1096void __init dm365_init_vc(struct snd_platform_data *pdata)
1097{
1098 davinci_cfg_reg(DM365_EVT2_VC_TX);
1099 davinci_cfg_reg(DM365_EVT3_VC_RX);
1100 dm365_vc_device.dev.platform_data = pdata;
1101 platform_device_register(&dm365_vc_device);
1102}
1103
990c09d5
MA		 1104void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
1105{
990c09d5
MA		 1106 dm365_ks_device.dev.platform_data = pdata;
1107 platform_device_register(&dm365_ks_device);
1108}
1109
99381b4f
MA		 1110void __init dm365_init_rtc(void)
1111{
1112 davinci_cfg_reg(DM365_INT_PRTCSS);
1113 platform_device_register(&dm365_rtc_device);
1114}
1115
fb8fcb89
SP		 1116void __init dm365_init(void)
1117{
1118 davinci_common_init(&davinci_soc_info_dm365);
1119}
8ed0a9d4 1120
f2a4c59d
MK		 1121static struct resource dm365_vpss_resources[] = {
1122 {
1123 /* VPSS ISP5 Base address */
1124 .name = "isp5",
1125 .start = 0x01c70000,
1126 .end = 0x01c70000 + 0xff,
1127 .flags = IORESOURCE_MEM,
1128 },
1129 {
1130 /* VPSS CLK Base address */
1131 .name = "vpss",
1132 .start = 0x01c70200,
1133 .end = 0x01c70200 + 0xff,
1134 .flags = IORESOURCE_MEM,
1135 },
1136};
1137
1138static struct platform_device dm365_vpss_device = {
1139 .name = "vpss",
1140 .id = -1,
1141 .dev.platform_data = "dm365_vpss",
1142 .num_resources = ARRAY_SIZE(dm365_vpss_resources),
1143 .resource = dm365_vpss_resources,
1144};
1145
1146static struct resource vpfe_resources[] = {
1147 {
1148 .start = IRQ_VDINT0,
1149 .end = IRQ_VDINT0,
1150 .flags = IORESOURCE_IRQ,
1151 },
1152 {
1153 .start = IRQ_VDINT1,
1154 .end = IRQ_VDINT1,
1155 .flags = IORESOURCE_IRQ,
1156 },
1157};
1158
1159static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
1160static struct platform_device vpfe_capture_dev = {
1161 .name = CAPTURE_DRV_NAME,
1162 .id = -1,
1163 .num_resources = ARRAY_SIZE(vpfe_resources),
1164 .resource = vpfe_resources,
1165 .dev = {
1166 .dma_mask = &vpfe_capture_dma_mask,
1167 .coherent_dma_mask = DMA_BIT_MASK(32),
1168 },
1169};
1170
1171static void dm365_isif_setup_pinmux(void)
1172{
1173 davinci_cfg_reg(DM365_VIN_CAM_WEN);
1174 davinci_cfg_reg(DM365_VIN_CAM_VD);
1175 davinci_cfg_reg(DM365_VIN_CAM_HD);
1176 davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
1177 davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
1178}
1179
1180static struct resource isif_resource[] = {
1181 /* ISIF Base address */
1182 {
1183 .start = 0x01c71000,
1184 .end = 0x01c71000 + 0x1ff,
1185 .flags = IORESOURCE_MEM,
1186 },
1187 /* ISIF Linearization table 0 */
1188 {
1189 .start = 0x1C7C000,
1190 .end = 0x1C7C000 + 0x2ff,
1191 .flags = IORESOURCE_MEM,
1192 },
1193 /* ISIF Linearization table 1 */
1194 {
1195 .start = 0x1C7C400,
1196 .end = 0x1C7C400 + 0x2ff,
1197 .flags = IORESOURCE_MEM,
1198 },
1199};
1200static struct platform_device dm365_isif_dev = {
1201 .name = "isif",
1202 .id = -1,
1203 .num_resources = ARRAY_SIZE(isif_resource),
1204 .resource = isif_resource,
1205 .dev = {
1206 .dma_mask = &vpfe_capture_dma_mask,
1207 .coherent_dma_mask = DMA_BIT_MASK(32),
1208 .platform_data = dm365_isif_setup_pinmux,
1209 },
1210};
1211
8ed0a9d4
SP		 1212static int __init dm365_init_devices(void)
1213{
1214 if (!cpu_is_davinci_dm365())
1215 return 0;
1216
15061b5d
SP		 1217 davinci_cfg_reg(DM365_INT_EDMA_CC);
1218 platform_device_register(&dm365_edma_device);
8ed0a9d4 1219 platform_device_register(&dm365_emac_device);
f2a4c59d
MK		 1220 /* Add isif clock alias */
1221 clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL);
1222 platform_device_register(&dm365_vpss_device);
1223 platform_device_register(&dm365_isif_dev);
1224 platform_device_register(&vpfe_capture_dev);
8ed0a9d4
SP		 1225 return 0;
1226}
1227postcore_initcall(dm365_init_devices);
f2a4c59d
MK		 1228
1229void dm365_set_vpfe_config(struct vpfe_config *cfg)
1230{
1231 vpfe_capture_dev.dev.platform_data = cfg;
1232}
Ubuntu Hirsute Linux kernel mirror