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e38d92fd KH |
1 | /* |
2 | * TI DaVinci DM644x chip specific setup | |
3 | * | |
4 | * Author: Kevin Hilman, Deep Root Systems, LLC | |
5 | * | |
6 | * 2007 (c) Deep Root Systems, LLC. This file is licensed under | |
7 | * the terms of the GNU General Public License version 2. This program | |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/clk.h> | |
65e866a9 | 14 | #include <linux/serial_8250.h> |
e38d92fd | 15 | #include <linux/platform_device.h> |
a994955c | 16 | #include <linux/gpio.h> |
e38d92fd | 17 | |
79c3c0b7 MG |
18 | #include <asm/mach/map.h> |
19 | ||
e38d92fd KH |
20 | #include <mach/dm646x.h> |
21 | #include <mach/clock.h> | |
22 | #include <mach/cputype.h> | |
23 | #include <mach/edma.h> | |
24 | #include <mach/irqs.h> | |
25 | #include <mach/psc.h> | |
26 | #include <mach/mux.h> | |
f64691b3 | 27 | #include <mach/time.h> |
65e866a9 | 28 | #include <mach/serial.h> |
79c3c0b7 | 29 | #include <mach/common.h> |
e38d92fd KH |
30 | |
31 | #include "clock.h" | |
32 | #include "mux.h" | |
33 | ||
34 | /* | |
35 | * Device specific clocks | |
36 | */ | |
37 | #define DM646X_REF_FREQ 27000000 | |
38 | #define DM646X_AUX_FREQ 24000000 | |
39 | ||
40 | static struct pll_data pll1_data = { | |
41 | .num = 1, | |
42 | .phys_base = DAVINCI_PLL1_BASE, | |
43 | }; | |
44 | ||
45 | static struct pll_data pll2_data = { | |
46 | .num = 2, | |
47 | .phys_base = DAVINCI_PLL2_BASE, | |
48 | }; | |
49 | ||
50 | static struct clk ref_clk = { | |
51 | .name = "ref_clk", | |
52 | .rate = DM646X_REF_FREQ, | |
53 | }; | |
54 | ||
55 | static struct clk aux_clkin = { | |
56 | .name = "aux_clkin", | |
57 | .rate = DM646X_AUX_FREQ, | |
58 | }; | |
59 | ||
60 | static struct clk pll1_clk = { | |
61 | .name = "pll1", | |
62 | .parent = &ref_clk, | |
63 | .pll_data = &pll1_data, | |
64 | .flags = CLK_PLL, | |
65 | }; | |
66 | ||
67 | static struct clk pll1_sysclk1 = { | |
68 | .name = "pll1_sysclk1", | |
69 | .parent = &pll1_clk, | |
70 | .flags = CLK_PLL, | |
71 | .div_reg = PLLDIV1, | |
72 | }; | |
73 | ||
74 | static struct clk pll1_sysclk2 = { | |
75 | .name = "pll1_sysclk2", | |
76 | .parent = &pll1_clk, | |
77 | .flags = CLK_PLL, | |
78 | .div_reg = PLLDIV2, | |
79 | }; | |
80 | ||
81 | static struct clk pll1_sysclk3 = { | |
82 | .name = "pll1_sysclk3", | |
83 | .parent = &pll1_clk, | |
84 | .flags = CLK_PLL, | |
85 | .div_reg = PLLDIV3, | |
86 | }; | |
87 | ||
88 | static struct clk pll1_sysclk4 = { | |
89 | .name = "pll1_sysclk4", | |
90 | .parent = &pll1_clk, | |
91 | .flags = CLK_PLL, | |
92 | .div_reg = PLLDIV4, | |
93 | }; | |
94 | ||
95 | static struct clk pll1_sysclk5 = { | |
96 | .name = "pll1_sysclk5", | |
97 | .parent = &pll1_clk, | |
98 | .flags = CLK_PLL, | |
99 | .div_reg = PLLDIV5, | |
100 | }; | |
101 | ||
102 | static struct clk pll1_sysclk6 = { | |
103 | .name = "pll1_sysclk6", | |
104 | .parent = &pll1_clk, | |
105 | .flags = CLK_PLL, | |
106 | .div_reg = PLLDIV6, | |
107 | }; | |
108 | ||
109 | static struct clk pll1_sysclk8 = { | |
110 | .name = "pll1_sysclk8", | |
111 | .parent = &pll1_clk, | |
112 | .flags = CLK_PLL, | |
113 | .div_reg = PLLDIV8, | |
114 | }; | |
115 | ||
116 | static struct clk pll1_sysclk9 = { | |
117 | .name = "pll1_sysclk9", | |
118 | .parent = &pll1_clk, | |
119 | .flags = CLK_PLL, | |
120 | .div_reg = PLLDIV9, | |
121 | }; | |
122 | ||
123 | static struct clk pll1_sysclkbp = { | |
124 | .name = "pll1_sysclkbp", | |
125 | .parent = &pll1_clk, | |
126 | .flags = CLK_PLL | PRE_PLL, | |
127 | .div_reg = BPDIV, | |
128 | }; | |
129 | ||
130 | static struct clk pll1_aux_clk = { | |
131 | .name = "pll1_aux_clk", | |
132 | .parent = &pll1_clk, | |
133 | .flags = CLK_PLL | PRE_PLL, | |
134 | }; | |
135 | ||
136 | static struct clk pll2_clk = { | |
137 | .name = "pll2_clk", | |
138 | .parent = &ref_clk, | |
139 | .pll_data = &pll2_data, | |
140 | .flags = CLK_PLL, | |
141 | }; | |
142 | ||
143 | static struct clk pll2_sysclk1 = { | |
144 | .name = "pll2_sysclk1", | |
145 | .parent = &pll2_clk, | |
146 | .flags = CLK_PLL, | |
147 | .div_reg = PLLDIV1, | |
148 | }; | |
149 | ||
150 | static struct clk dsp_clk = { | |
151 | .name = "dsp", | |
152 | .parent = &pll1_sysclk1, | |
153 | .lpsc = DM646X_LPSC_C64X_CPU, | |
154 | .flags = PSC_DSP, | |
155 | .usecount = 1, /* REVISIT how to disable? */ | |
156 | }; | |
157 | ||
158 | static struct clk arm_clk = { | |
159 | .name = "arm", | |
160 | .parent = &pll1_sysclk2, | |
161 | .lpsc = DM646X_LPSC_ARM, | |
162 | .flags = ALWAYS_ENABLED, | |
163 | }; | |
164 | ||
165 | static struct clk uart0_clk = { | |
166 | .name = "uart0", | |
167 | .parent = &aux_clkin, | |
168 | .lpsc = DM646X_LPSC_UART0, | |
169 | }; | |
170 | ||
171 | static struct clk uart1_clk = { | |
172 | .name = "uart1", | |
173 | .parent = &aux_clkin, | |
174 | .lpsc = DM646X_LPSC_UART1, | |
175 | }; | |
176 | ||
177 | static struct clk uart2_clk = { | |
178 | .name = "uart2", | |
179 | .parent = &aux_clkin, | |
180 | .lpsc = DM646X_LPSC_UART2, | |
181 | }; | |
182 | ||
183 | static struct clk i2c_clk = { | |
184 | .name = "I2CCLK", | |
185 | .parent = &pll1_sysclk3, | |
186 | .lpsc = DM646X_LPSC_I2C, | |
187 | }; | |
188 | ||
189 | static struct clk gpio_clk = { | |
190 | .name = "gpio", | |
191 | .parent = &pll1_sysclk3, | |
192 | .lpsc = DM646X_LPSC_GPIO, | |
193 | }; | |
194 | ||
195 | static struct clk aemif_clk = { | |
196 | .name = "aemif", | |
197 | .parent = &pll1_sysclk3, | |
198 | .lpsc = DM646X_LPSC_AEMIF, | |
199 | .flags = ALWAYS_ENABLED, | |
200 | }; | |
201 | ||
202 | static struct clk emac_clk = { | |
203 | .name = "emac", | |
204 | .parent = &pll1_sysclk3, | |
205 | .lpsc = DM646X_LPSC_EMAC, | |
206 | }; | |
207 | ||
208 | static struct clk pwm0_clk = { | |
209 | .name = "pwm0", | |
210 | .parent = &pll1_sysclk3, | |
211 | .lpsc = DM646X_LPSC_PWM0, | |
212 | .usecount = 1, /* REVIST: disabling hangs system */ | |
213 | }; | |
214 | ||
215 | static struct clk pwm1_clk = { | |
216 | .name = "pwm1", | |
217 | .parent = &pll1_sysclk3, | |
218 | .lpsc = DM646X_LPSC_PWM1, | |
219 | .usecount = 1, /* REVIST: disabling hangs system */ | |
220 | }; | |
221 | ||
222 | static struct clk timer0_clk = { | |
223 | .name = "timer0", | |
224 | .parent = &pll1_sysclk3, | |
225 | .lpsc = DM646X_LPSC_TIMER0, | |
226 | }; | |
227 | ||
228 | static struct clk timer1_clk = { | |
229 | .name = "timer1", | |
230 | .parent = &pll1_sysclk3, | |
231 | .lpsc = DM646X_LPSC_TIMER1, | |
232 | }; | |
233 | ||
234 | static struct clk timer2_clk = { | |
235 | .name = "timer2", | |
236 | .parent = &pll1_sysclk3, | |
237 | .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */ | |
238 | }; | |
239 | ||
240 | static struct clk vpif0_clk = { | |
241 | .name = "vpif0", | |
242 | .parent = &ref_clk, | |
243 | .lpsc = DM646X_LPSC_VPSSMSTR, | |
244 | .flags = ALWAYS_ENABLED, | |
245 | }; | |
246 | ||
247 | static struct clk vpif1_clk = { | |
248 | .name = "vpif1", | |
249 | .parent = &ref_clk, | |
250 | .lpsc = DM646X_LPSC_VPSSSLV, | |
251 | .flags = ALWAYS_ENABLED, | |
252 | }; | |
253 | ||
254 | struct davinci_clk dm646x_clks[] = { | |
255 | CLK(NULL, "ref", &ref_clk), | |
256 | CLK(NULL, "aux", &aux_clkin), | |
257 | CLK(NULL, "pll1", &pll1_clk), | |
258 | CLK(NULL, "pll1_sysclk", &pll1_sysclk1), | |
259 | CLK(NULL, "pll1_sysclk", &pll1_sysclk2), | |
260 | CLK(NULL, "pll1_sysclk", &pll1_sysclk3), | |
261 | CLK(NULL, "pll1_sysclk", &pll1_sysclk4), | |
262 | CLK(NULL, "pll1_sysclk", &pll1_sysclk5), | |
263 | CLK(NULL, "pll1_sysclk", &pll1_sysclk6), | |
264 | CLK(NULL, "pll1_sysclk", &pll1_sysclk8), | |
265 | CLK(NULL, "pll1_sysclk", &pll1_sysclk9), | |
266 | CLK(NULL, "pll1_sysclk", &pll1_sysclkbp), | |
267 | CLK(NULL, "pll1_aux", &pll1_aux_clk), | |
268 | CLK(NULL, "pll2", &pll2_clk), | |
269 | CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), | |
270 | CLK(NULL, "dsp", &dsp_clk), | |
271 | CLK(NULL, "arm", &arm_clk), | |
272 | CLK(NULL, "uart0", &uart0_clk), | |
273 | CLK(NULL, "uart1", &uart1_clk), | |
274 | CLK(NULL, "uart2", &uart2_clk), | |
275 | CLK("i2c_davinci.1", NULL, &i2c_clk), | |
276 | CLK(NULL, "gpio", &gpio_clk), | |
277 | CLK(NULL, "aemif", &aemif_clk), | |
278 | CLK("davinci_emac.1", NULL, &emac_clk), | |
279 | CLK(NULL, "pwm0", &pwm0_clk), | |
280 | CLK(NULL, "pwm1", &pwm1_clk), | |
281 | CLK(NULL, "timer0", &timer0_clk), | |
282 | CLK(NULL, "timer1", &timer1_clk), | |
283 | CLK("watchdog", NULL, &timer2_clk), | |
284 | CLK(NULL, "vpif0", &vpif0_clk), | |
285 | CLK(NULL, "vpif1", &vpif1_clk), | |
286 | CLK(NULL, NULL, NULL), | |
287 | }; | |
288 | ||
972412b6 MG |
289 | static struct emac_platform_data dm646x_emac_pdata = { |
290 | .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET, | |
291 | .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET, | |
292 | .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET, | |
293 | .mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET, | |
294 | .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE, | |
295 | .version = EMAC_VERSION_2, | |
296 | }; | |
297 | ||
ac7b75b5 KH |
298 | static struct resource dm646x_emac_resources[] = { |
299 | { | |
300 | .start = DM646X_EMAC_BASE, | |
301 | .end = DM646X_EMAC_BASE + 0x47ff, | |
302 | .flags = IORESOURCE_MEM, | |
303 | }, | |
304 | { | |
305 | .start = IRQ_DM646X_EMACRXTHINT, | |
306 | .end = IRQ_DM646X_EMACRXTHINT, | |
307 | .flags = IORESOURCE_IRQ, | |
308 | }, | |
309 | { | |
310 | .start = IRQ_DM646X_EMACRXINT, | |
311 | .end = IRQ_DM646X_EMACRXINT, | |
312 | .flags = IORESOURCE_IRQ, | |
313 | }, | |
314 | { | |
315 | .start = IRQ_DM646X_EMACTXINT, | |
316 | .end = IRQ_DM646X_EMACTXINT, | |
317 | .flags = IORESOURCE_IRQ, | |
318 | }, | |
319 | { | |
320 | .start = IRQ_DM646X_EMACMISCINT, | |
321 | .end = IRQ_DM646X_EMACMISCINT, | |
322 | .flags = IORESOURCE_IRQ, | |
323 | }, | |
324 | }; | |
325 | ||
326 | static struct platform_device dm646x_emac_device = { | |
327 | .name = "davinci_emac", | |
328 | .id = 1, | |
972412b6 MG |
329 | .dev = { |
330 | .platform_data = &dm646x_emac_pdata, | |
331 | }, | |
ac7b75b5 KH |
332 | .num_resources = ARRAY_SIZE(dm646x_emac_resources), |
333 | .resource = dm646x_emac_resources, | |
334 | }; | |
335 | ||
5570078c MG |
336 | #define PINMUX0 0x00 |
337 | #define PINMUX1 0x04 | |
338 | ||
e38d92fd KH |
339 | /* |
340 | * Device specific mux setup | |
341 | * | |
342 | * soc description mux mode mode mux dbg | |
343 | * reg offset mask mode | |
344 | */ | |
345 | static const struct mux_config dm646x_pins[] = { | |
0e585952 | 346 | #ifdef CONFIG_DAVINCI_MUX |
e38d92fd KH |
347 | MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true) |
348 | ||
349 | MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false) | |
350 | ||
351 | MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false) | |
352 | ||
353 | MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true) | |
354 | ||
355 | MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true) | |
356 | ||
357 | MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true) | |
358 | ||
359 | MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true) | |
360 | ||
361 | MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true) | |
362 | ||
363 | MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true) | |
364 | ||
365 | MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true) | |
366 | ||
367 | MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true) | |
368 | ||
369 | MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true) | |
370 | ||
371 | MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true) | |
372 | ||
373 | MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true) | |
0e585952 | 374 | #endif |
e38d92fd KH |
375 | }; |
376 | ||
673dd36f MG |
377 | static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { |
378 | [IRQ_DM646X_VP_VERTINT0] = 7, | |
379 | [IRQ_DM646X_VP_VERTINT1] = 7, | |
380 | [IRQ_DM646X_VP_VERTINT2] = 7, | |
381 | [IRQ_DM646X_VP_VERTINT3] = 7, | |
382 | [IRQ_DM646X_VP_ERRINT] = 7, | |
383 | [IRQ_DM646X_RESERVED_1] = 7, | |
384 | [IRQ_DM646X_RESERVED_2] = 7, | |
385 | [IRQ_DM646X_WDINT] = 7, | |
386 | [IRQ_DM646X_CRGENINT0] = 7, | |
387 | [IRQ_DM646X_CRGENINT1] = 7, | |
388 | [IRQ_DM646X_TSIFINT0] = 7, | |
389 | [IRQ_DM646X_TSIFINT1] = 7, | |
390 | [IRQ_DM646X_VDCEINT] = 7, | |
391 | [IRQ_DM646X_USBINT] = 7, | |
392 | [IRQ_DM646X_USBDMAINT] = 7, | |
393 | [IRQ_DM646X_PCIINT] = 7, | |
394 | [IRQ_CCINT0] = 7, /* dma */ | |
395 | [IRQ_CCERRINT] = 7, /* dma */ | |
396 | [IRQ_TCERRINT0] = 7, /* dma */ | |
397 | [IRQ_TCERRINT] = 7, /* dma */ | |
398 | [IRQ_DM646X_TCERRINT2] = 7, | |
399 | [IRQ_DM646X_TCERRINT3] = 7, | |
400 | [IRQ_DM646X_IDE] = 7, | |
401 | [IRQ_DM646X_HPIINT] = 7, | |
402 | [IRQ_DM646X_EMACRXTHINT] = 7, | |
403 | [IRQ_DM646X_EMACRXINT] = 7, | |
404 | [IRQ_DM646X_EMACTXINT] = 7, | |
405 | [IRQ_DM646X_EMACMISCINT] = 7, | |
406 | [IRQ_DM646X_MCASP0TXINT] = 7, | |
407 | [IRQ_DM646X_MCASP0RXINT] = 7, | |
408 | [IRQ_AEMIFINT] = 7, | |
409 | [IRQ_DM646X_RESERVED_3] = 7, | |
410 | [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */ | |
411 | [IRQ_TINT0_TINT34] = 7, /* clocksource */ | |
412 | [IRQ_TINT1_TINT12] = 7, /* DSP timer */ | |
413 | [IRQ_TINT1_TINT34] = 7, /* system tick */ | |
414 | [IRQ_PWMINT0] = 7, | |
415 | [IRQ_PWMINT1] = 7, | |
416 | [IRQ_DM646X_VLQINT] = 7, | |
417 | [IRQ_I2C] = 7, | |
418 | [IRQ_UARTINT0] = 7, | |
419 | [IRQ_UARTINT1] = 7, | |
420 | [IRQ_DM646X_UARTINT2] = 7, | |
421 | [IRQ_DM646X_SPINT0] = 7, | |
422 | [IRQ_DM646X_SPINT1] = 7, | |
423 | [IRQ_DM646X_DSP2ARMINT] = 7, | |
424 | [IRQ_DM646X_RESERVED_4] = 7, | |
425 | [IRQ_DM646X_PSCINT] = 7, | |
426 | [IRQ_DM646X_GPIO0] = 7, | |
427 | [IRQ_DM646X_GPIO1] = 7, | |
428 | [IRQ_DM646X_GPIO2] = 7, | |
429 | [IRQ_DM646X_GPIO3] = 7, | |
430 | [IRQ_DM646X_GPIO4] = 7, | |
431 | [IRQ_DM646X_GPIO5] = 7, | |
432 | [IRQ_DM646X_GPIO6] = 7, | |
433 | [IRQ_DM646X_GPIO7] = 7, | |
434 | [IRQ_DM646X_GPIOBNK0] = 7, | |
435 | [IRQ_DM646X_GPIOBNK1] = 7, | |
436 | [IRQ_DM646X_GPIOBNK2] = 7, | |
437 | [IRQ_DM646X_DDRINT] = 7, | |
438 | [IRQ_DM646X_AEMIFINT] = 7, | |
439 | [IRQ_COMMTX] = 7, | |
440 | [IRQ_COMMRX] = 7, | |
441 | [IRQ_EMUINT] = 7, | |
442 | }; | |
443 | ||
e38d92fd KH |
444 | /*----------------------------------------------------------------------*/ |
445 | ||
446 | static const s8 dma_chan_dm646x_no_event[] = { | |
447 | 0, 1, 2, 3, 13, | |
448 | 14, 15, 24, 25, 26, | |
449 | 27, 30, 31, 54, 55, | |
450 | 56, | |
451 | -1 | |
452 | }; | |
453 | ||
454 | static struct edma_soc_info dm646x_edma_info = { | |
455 | .n_channel = 64, | |
456 | .n_region = 6, /* 0-1, 4-7 */ | |
457 | .n_slot = 512, | |
458 | .n_tc = 4, | |
459 | .noevent = dma_chan_dm646x_no_event, | |
460 | }; | |
461 | ||
462 | static struct resource edma_resources[] = { | |
463 | { | |
464 | .name = "edma_cc", | |
465 | .start = 0x01c00000, | |
466 | .end = 0x01c00000 + SZ_64K - 1, | |
467 | .flags = IORESOURCE_MEM, | |
468 | }, | |
469 | { | |
470 | .name = "edma_tc0", | |
471 | .start = 0x01c10000, | |
472 | .end = 0x01c10000 + SZ_1K - 1, | |
473 | .flags = IORESOURCE_MEM, | |
474 | }, | |
475 | { | |
476 | .name = "edma_tc1", | |
477 | .start = 0x01c10400, | |
478 | .end = 0x01c10400 + SZ_1K - 1, | |
479 | .flags = IORESOURCE_MEM, | |
480 | }, | |
481 | { | |
482 | .name = "edma_tc2", | |
483 | .start = 0x01c10800, | |
484 | .end = 0x01c10800 + SZ_1K - 1, | |
485 | .flags = IORESOURCE_MEM, | |
486 | }, | |
487 | { | |
488 | .name = "edma_tc3", | |
489 | .start = 0x01c10c00, | |
490 | .end = 0x01c10c00 + SZ_1K - 1, | |
491 | .flags = IORESOURCE_MEM, | |
492 | }, | |
493 | { | |
494 | .start = IRQ_CCINT0, | |
495 | .flags = IORESOURCE_IRQ, | |
496 | }, | |
497 | { | |
498 | .start = IRQ_CCERRINT, | |
499 | .flags = IORESOURCE_IRQ, | |
500 | }, | |
501 | /* not using TC*_ERR */ | |
502 | }; | |
503 | ||
504 | static struct platform_device dm646x_edma_device = { | |
505 | .name = "edma", | |
506 | .id = -1, | |
507 | .dev.platform_data = &dm646x_edma_info, | |
508 | .num_resources = ARRAY_SIZE(edma_resources), | |
509 | .resource = edma_resources, | |
510 | }; | |
511 | ||
512 | /*----------------------------------------------------------------------*/ | |
513 | ||
79c3c0b7 MG |
514 | static struct map_desc dm646x_io_desc[] = { |
515 | { | |
516 | .virtual = IO_VIRT, | |
517 | .pfn = __phys_to_pfn(IO_PHYS), | |
518 | .length = IO_SIZE, | |
519 | .type = MT_DEVICE | |
520 | }, | |
0d04eb47 DB |
521 | { |
522 | .virtual = SRAM_VIRT, | |
523 | .pfn = __phys_to_pfn(0x00010000), | |
524 | .length = SZ_32K, | |
525 | /* MT_MEMORY_NONCACHED requires supersection alignment */ | |
526 | .type = MT_DEVICE, | |
527 | }, | |
79c3c0b7 MG |
528 | }; |
529 | ||
b9ab1279 MG |
530 | /* Contents of JTAG ID register used to identify exact cpu type */ |
531 | static struct davinci_id dm646x_ids[] = { | |
532 | { | |
533 | .variant = 0x0, | |
534 | .part_no = 0xb770, | |
535 | .manufacturer = 0x017, | |
536 | .cpu_id = DAVINCI_CPU_ID_DM6467, | |
537 | .name = "dm6467", | |
538 | }, | |
539 | }; | |
540 | ||
d81d188c MG |
541 | static void __iomem *dm646x_psc_bases[] = { |
542 | IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), | |
543 | }; | |
544 | ||
f64691b3 MG |
545 | /* |
546 | * T0_BOT: Timer 0, bottom: clockevent source for hrtimers | |
547 | * T0_TOP: Timer 0, top : clocksource for generic timekeeping | |
548 | * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) | |
549 | * T1_TOP: Timer 1, top : <unused> | |
550 | */ | |
551 | struct davinci_timer_info dm646x_timer_info = { | |
552 | .timers = davinci_timer_instance, | |
553 | .clockevent_id = T0_BOT, | |
554 | .clocksource_id = T0_TOP, | |
555 | }; | |
556 | ||
65e866a9 MG |
557 | static struct plat_serial8250_port dm646x_serial_platform_data[] = { |
558 | { | |
559 | .mapbase = DAVINCI_UART0_BASE, | |
560 | .irq = IRQ_UARTINT0, | |
561 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
562 | UPF_IOREMAP, | |
563 | .iotype = UPIO_MEM32, | |
564 | .regshift = 2, | |
565 | }, | |
566 | { | |
567 | .mapbase = DAVINCI_UART1_BASE, | |
568 | .irq = IRQ_UARTINT1, | |
569 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
570 | UPF_IOREMAP, | |
571 | .iotype = UPIO_MEM32, | |
572 | .regshift = 2, | |
573 | }, | |
574 | { | |
575 | .mapbase = DAVINCI_UART2_BASE, | |
576 | .irq = IRQ_DM646X_UARTINT2, | |
577 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | |
578 | UPF_IOREMAP, | |
579 | .iotype = UPIO_MEM32, | |
580 | .regshift = 2, | |
581 | }, | |
582 | { | |
583 | .flags = 0 | |
584 | }, | |
585 | }; | |
586 | ||
587 | static struct platform_device dm646x_serial_device = { | |
588 | .name = "serial8250", | |
589 | .id = PLAT8250_DEV_PLATFORM, | |
590 | .dev = { | |
591 | .platform_data = dm646x_serial_platform_data, | |
592 | }, | |
593 | }; | |
594 | ||
79c3c0b7 MG |
595 | static struct davinci_soc_info davinci_soc_info_dm646x = { |
596 | .io_desc = dm646x_io_desc, | |
597 | .io_desc_num = ARRAY_SIZE(dm646x_io_desc), | |
b9ab1279 MG |
598 | .jtag_id_base = IO_ADDRESS(0x01c40028), |
599 | .ids = dm646x_ids, | |
600 | .ids_num = ARRAY_SIZE(dm646x_ids), | |
66e0c399 | 601 | .cpu_clks = dm646x_clks, |
d81d188c MG |
602 | .psc_bases = dm646x_psc_bases, |
603 | .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases), | |
0e585952 MG |
604 | .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE), |
605 | .pinmux_pins = dm646x_pins, | |
606 | .pinmux_pins_num = ARRAY_SIZE(dm646x_pins), | |
673dd36f MG |
607 | .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE), |
608 | .intc_type = DAVINCI_INTC_TYPE_AINTC, | |
609 | .intc_irq_prios = dm646x_default_priorities, | |
610 | .intc_irq_num = DAVINCI_N_AINTC_IRQ, | |
f64691b3 | 611 | .timer_info = &dm646x_timer_info, |
951d6f6d | 612 | .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE), |
a994955c MG |
613 | .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE), |
614 | .gpio_num = 43, /* Only 33 usable */ | |
615 | .gpio_irq = IRQ_DM646X_GPIOBNK0, | |
65e866a9 | 616 | .serial_dev = &dm646x_serial_device, |
972412b6 | 617 | .emac_pdata = &dm646x_emac_pdata, |
0d04eb47 DB |
618 | .sram_dma = 0x10010000, |
619 | .sram_len = SZ_32K, | |
79c3c0b7 MG |
620 | }; |
621 | ||
e38d92fd KH |
622 | void __init dm646x_init(void) |
623 | { | |
79c3c0b7 | 624 | davinci_common_init(&davinci_soc_info_dm646x); |
e38d92fd KH |
625 | } |
626 | ||
627 | static int __init dm646x_init_devices(void) | |
628 | { | |
629 | if (!cpu_is_davinci_dm646x()) | |
630 | return 0; | |
631 | ||
632 | platform_device_register(&dm646x_edma_device); | |
972412b6 | 633 | platform_device_register(&dm646x_emac_device); |
e38d92fd KH |
634 | return 0; |
635 | } | |
636 | postcore_initcall(dm646x_init_devices); |