[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-davinci / dm646x.c

/*
 * TI DaVinci DM644x chip specific setup
 *
 * Author: Kevin Hilman, Deep Root Systems, LLC
 *
 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>

#include <asm/mach/map.h>

#include <mach/dm646x.h>
#include <mach/clock.h>
#include <mach/cputype.h>
#include <mach/edma.h>
#include <mach/irqs.h>
#include <mach/psc.h>
#include <mach/mux.h>
#include <mach/time.h>
#include <mach/common.h>

#include "clock.h"
#include "mux.h"

/*
 * Device specific clocks
 */
#define DM646X_REF_FREQ		27000000
#define DM646X_AUX_FREQ		24000000

static struct pll_data pll1_data = {
	.num       = 1,
	.phys_base = DAVINCI_PLL1_BASE,
};

static struct pll_data pll2_data = {
	.num       = 2,
	.phys_base = DAVINCI_PLL2_BASE,
};

static struct clk ref_clk = {
	.name = "ref_clk",
	.rate = DM646X_REF_FREQ,
};

static struct clk aux_clkin = {
	.name = "aux_clkin",
	.rate = DM646X_AUX_FREQ,
};

static struct clk pll1_clk = {
	.name = "pll1",
	.parent = &ref_clk,
	.pll_data = &pll1_data,
	.flags = CLK_PLL,
};

static struct clk pll1_sysclk1 = {
	.name = "pll1_sysclk1",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV1,
};

static struct clk pll1_sysclk2 = {
	.name = "pll1_sysclk2",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV2,
};

static struct clk pll1_sysclk3 = {
	.name = "pll1_sysclk3",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV3,
};

static struct clk pll1_sysclk4 = {
	.name = "pll1_sysclk4",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV4,
};

static struct clk pll1_sysclk5 = {
	.name = "pll1_sysclk5",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV5,
};

static struct clk pll1_sysclk6 = {
	.name = "pll1_sysclk6",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV6,
};

static struct clk pll1_sysclk8 = {
	.name = "pll1_sysclk8",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV8,
};

static struct clk pll1_sysclk9 = {
	.name = "pll1_sysclk9",
	.parent = &pll1_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV9,
};

static struct clk pll1_sysclkbp = {
	.name = "pll1_sysclkbp",
	.parent = &pll1_clk,
	.flags = CLK_PLL | PRE_PLL,
	.div_reg = BPDIV,
};

static struct clk pll1_aux_clk = {
	.name = "pll1_aux_clk",
	.parent = &pll1_clk,
	.flags = CLK_PLL | PRE_PLL,
};

static struct clk pll2_clk = {
	.name = "pll2_clk",
	.parent = &ref_clk,
	.pll_data = &pll2_data,
	.flags = CLK_PLL,
};

static struct clk pll2_sysclk1 = {
	.name = "pll2_sysclk1",
	.parent = &pll2_clk,
	.flags = CLK_PLL,
	.div_reg = PLLDIV1,
};

static struct clk dsp_clk = {
	.name = "dsp",
	.parent = &pll1_sysclk1,
	.lpsc = DM646X_LPSC_C64X_CPU,
	.flags = PSC_DSP,
	.usecount = 1,			/* REVISIT how to disable? */
};

static struct clk arm_clk = {
	.name = "arm",
	.parent = &pll1_sysclk2,
	.lpsc = DM646X_LPSC_ARM,
	.flags = ALWAYS_ENABLED,
};

static struct clk uart0_clk = {
	.name = "uart0",
	.parent = &aux_clkin,
	.lpsc = DM646X_LPSC_UART0,
};

static struct clk uart1_clk = {
	.name = "uart1",
	.parent = &aux_clkin,
	.lpsc = DM646X_LPSC_UART1,
};

static struct clk uart2_clk = {
	.name = "uart2",
	.parent = &aux_clkin,
	.lpsc = DM646X_LPSC_UART2,
};

static struct clk i2c_clk = {
	.name = "I2CCLK",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_I2C,
};

static struct clk gpio_clk = {
	.name = "gpio",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_GPIO,
};

static struct clk aemif_clk = {
	.name = "aemif",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_AEMIF,
	.flags = ALWAYS_ENABLED,
};

static struct clk emac_clk = {
	.name = "emac",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_EMAC,
};

static struct clk pwm0_clk = {
	.name = "pwm0",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_PWM0,
	.usecount = 1,            /* REVIST: disabling hangs system */
};

static struct clk pwm1_clk = {
	.name = "pwm1",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_PWM1,
	.usecount = 1,            /* REVIST: disabling hangs system */
};

static struct clk timer0_clk = {
	.name = "timer0",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_TIMER0,
};

static struct clk timer1_clk = {
	.name = "timer1",
	.parent = &pll1_sysclk3,
	.lpsc = DM646X_LPSC_TIMER1,
};

static struct clk timer2_clk = {
	.name = "timer2",
	.parent = &pll1_sysclk3,
	.flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
};

static struct clk vpif0_clk = {
	.name = "vpif0",
	.parent = &ref_clk,
	.lpsc = DM646X_LPSC_VPSSMSTR,
	.flags = ALWAYS_ENABLED,
};

static struct clk vpif1_clk = {
	.name = "vpif1",
	.parent = &ref_clk,
	.lpsc = DM646X_LPSC_VPSSSLV,
	.flags = ALWAYS_ENABLED,
};

struct davinci_clk dm646x_clks[] = {
	CLK(NULL, "ref", &ref_clk),
	CLK(NULL, "aux", &aux_clkin),
	CLK(NULL, "pll1", &pll1_clk),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
	CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
	CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
	CLK(NULL, "pll1_aux", &pll1_aux_clk),
	CLK(NULL, "pll2", &pll2_clk),
	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
	CLK(NULL, "dsp", &dsp_clk),
	CLK(NULL, "arm", &arm_clk),
	CLK(NULL, "uart0", &uart0_clk),
	CLK(NULL, "uart1", &uart1_clk),
	CLK(NULL, "uart2", &uart2_clk),
	CLK("i2c_davinci.1", NULL, &i2c_clk),
	CLK(NULL, "gpio", &gpio_clk),
	CLK(NULL, "aemif", &aemif_clk),
	CLK("davinci_emac.1", NULL, &emac_clk),
	CLK(NULL, "pwm0", &pwm0_clk),
	CLK(NULL, "pwm1", &pwm1_clk),
	CLK(NULL, "timer0", &timer0_clk),
	CLK(NULL, "timer1", &timer1_clk),
	CLK("watchdog", NULL, &timer2_clk),
	CLK(NULL, "vpif0", &vpif0_clk),
	CLK(NULL, "vpif1", &vpif1_clk),
	CLK(NULL, NULL, NULL),
};

#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
static struct resource dm646x_emac_resources[] = {
	{
		.start	= DM646X_EMAC_BASE,
		.end	= DM646X_EMAC_BASE + 0x47ff,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_DM646X_EMACRXTHINT,
		.end	= IRQ_DM646X_EMACRXTHINT,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= IRQ_DM646X_EMACRXINT,
		.end	= IRQ_DM646X_EMACRXINT,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= IRQ_DM646X_EMACTXINT,
		.end	= IRQ_DM646X_EMACTXINT,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= IRQ_DM646X_EMACMISCINT,
		.end	= IRQ_DM646X_EMACMISCINT,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dm646x_emac_device = {
	.name		= "davinci_emac",
	.id		= 1,
	.num_resources	= ARRAY_SIZE(dm646x_emac_resources),
	.resource	= dm646x_emac_resources,
};

#endif

/*
 * Device specific mux setup
 *
 *	soc	description	mux  mode   mode  mux	 dbg
 *				reg  offset mask  mode
 */
static const struct mux_config dm646x_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
MUX_CFG(DM646X, ATAEN,		0,   0,     1,	  1,	 true)

MUX_CFG(DM646X, AUDCK1,		0,   29,    1,	  0,	 false)

MUX_CFG(DM646X, AUDCK0,		0,   28,    1,	  0,	 false)

MUX_CFG(DM646X, CRGMUX,			0,   24,    7,    5,	 true)

MUX_CFG(DM646X, STSOMUX_DISABLE,	0,   22,    3,    0,	 true)

MUX_CFG(DM646X, STSIMUX_DISABLE,	0,   20,    3,    0,	 true)

MUX_CFG(DM646X, PTSOMUX_DISABLE,	0,   18,    3,    0,	 true)

MUX_CFG(DM646X, PTSIMUX_DISABLE,	0,   16,    3,    0,	 true)

MUX_CFG(DM646X, STSOMUX,		0,   22,    3,    2,	 true)

MUX_CFG(DM646X, STSIMUX,		0,   20,    3,    2,	 true)

MUX_CFG(DM646X, PTSOMUX_PARALLEL,	0,   18,    3,    2,	 true)

MUX_CFG(DM646X, PTSIMUX_PARALLEL,	0,   16,    3,    2,	 true)

MUX_CFG(DM646X, PTSOMUX_SERIAL,		0,   18,    3,    3,	 true)

MUX_CFG(DM646X, PTSIMUX_SERIAL,		0,   16,    3,    3,	 true)
#endif
};

static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
	[IRQ_DM646X_VP_VERTINT0]        = 7,
	[IRQ_DM646X_VP_VERTINT1]        = 7,
	[IRQ_DM646X_VP_VERTINT2]        = 7,
	[IRQ_DM646X_VP_VERTINT3]        = 7,
	[IRQ_DM646X_VP_ERRINT]          = 7,
	[IRQ_DM646X_RESERVED_1]         = 7,
	[IRQ_DM646X_RESERVED_2]         = 7,
	[IRQ_DM646X_WDINT]              = 7,
	[IRQ_DM646X_CRGENINT0]          = 7,
	[IRQ_DM646X_CRGENINT1]          = 7,
	[IRQ_DM646X_TSIFINT0]           = 7,
	[IRQ_DM646X_TSIFINT1]           = 7,
	[IRQ_DM646X_VDCEINT]            = 7,
	[IRQ_DM646X_USBINT]             = 7,
	[IRQ_DM646X_USBDMAINT]          = 7,
	[IRQ_DM646X_PCIINT]             = 7,
	[IRQ_CCINT0]                    = 7,    /* dma */
	[IRQ_CCERRINT]                  = 7,    /* dma */
	[IRQ_TCERRINT0]                 = 7,    /* dma */
	[IRQ_TCERRINT]                  = 7,    /* dma */
	[IRQ_DM646X_TCERRINT2]          = 7,
	[IRQ_DM646X_TCERRINT3]          = 7,
	[IRQ_DM646X_IDE]                = 7,
	[IRQ_DM646X_HPIINT]             = 7,
	[IRQ_DM646X_EMACRXTHINT]        = 7,
	[IRQ_DM646X_EMACRXINT]          = 7,
	[IRQ_DM646X_EMACTXINT]          = 7,
	[IRQ_DM646X_EMACMISCINT]        = 7,
	[IRQ_DM646X_MCASP0TXINT]        = 7,
	[IRQ_DM646X_MCASP0RXINT]        = 7,
	[IRQ_AEMIFINT]                  = 7,
	[IRQ_DM646X_RESERVED_3]         = 7,
	[IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
	[IRQ_TINT0_TINT34]              = 7,    /* clocksource */
	[IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
	[IRQ_TINT1_TINT34]              = 7,    /* system tick */
	[IRQ_PWMINT0]                   = 7,
	[IRQ_PWMINT1]                   = 7,
	[IRQ_DM646X_VLQINT]             = 7,
	[IRQ_I2C]                       = 7,
	[IRQ_UARTINT0]                  = 7,
	[IRQ_UARTINT1]                  = 7,
	[IRQ_DM646X_UARTINT2]           = 7,
	[IRQ_DM646X_SPINT0]             = 7,
	[IRQ_DM646X_SPINT1]             = 7,
	[IRQ_DM646X_DSP2ARMINT]         = 7,
	[IRQ_DM646X_RESERVED_4]         = 7,
	[IRQ_DM646X_PSCINT]             = 7,
	[IRQ_DM646X_GPIO0]              = 7,
	[IRQ_DM646X_GPIO1]              = 7,
	[IRQ_DM646X_GPIO2]              = 7,
	[IRQ_DM646X_GPIO3]              = 7,
	[IRQ_DM646X_GPIO4]              = 7,
	[IRQ_DM646X_GPIO5]              = 7,
	[IRQ_DM646X_GPIO6]              = 7,
	[IRQ_DM646X_GPIO7]              = 7,
	[IRQ_DM646X_GPIOBNK0]           = 7,
	[IRQ_DM646X_GPIOBNK1]           = 7,
	[IRQ_DM646X_GPIOBNK2]           = 7,
	[IRQ_DM646X_DDRINT]             = 7,
	[IRQ_DM646X_AEMIFINT]           = 7,
	[IRQ_COMMTX]                    = 7,
	[IRQ_COMMRX]                    = 7,
	[IRQ_EMUINT]                    = 7,
};

/*----------------------------------------------------------------------*/

static const s8 dma_chan_dm646x_no_event[] = {
	 0,  1,  2,  3, 13,
	14, 15, 24, 25, 26,
	27, 30, 31, 54, 55,
	56,
	-1
};

static struct edma_soc_info dm646x_edma_info = {
	.n_channel	= 64,
	.n_region	= 6,	/* 0-1, 4-7 */
	.n_slot		= 512,
	.n_tc		= 4,
	.noevent	= dma_chan_dm646x_no_event,
};

static struct resource edma_resources[] = {
	{
		.name	= "edma_cc",
		.start	= 0x01c00000,
		.end	= 0x01c00000 + SZ_64K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc0",
		.start	= 0x01c10000,
		.end	= 0x01c10000 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc1",
		.start	= 0x01c10400,
		.end	= 0x01c10400 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc2",
		.start	= 0x01c10800,
		.end	= 0x01c10800 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "edma_tc3",
		.start	= 0x01c10c00,
		.end	= 0x01c10c00 + SZ_1K - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_CCINT0,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= IRQ_CCERRINT,
		.flags	= IORESOURCE_IRQ,
	},
	/* not using TC*_ERR */
};

static struct platform_device dm646x_edma_device = {
	.name			= "edma",
	.id			= -1,
	.dev.platform_data	= &dm646x_edma_info,
	.num_resources		= ARRAY_SIZE(edma_resources),
	.resource		= edma_resources,
};

/*----------------------------------------------------------------------*/

#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)

void dm646x_init_emac(struct emac_platform_data *pdata)
{
	pdata->ctrl_reg_offset		= DM646X_EMAC_CNTRL_OFFSET;
	pdata->ctrl_mod_reg_offset	= DM646X_EMAC_CNTRL_MOD_OFFSET;
	pdata->ctrl_ram_offset		= DM646X_EMAC_CNTRL_RAM_OFFSET;
	pdata->mdio_reg_offset		= DM646X_EMAC_MDIO_OFFSET;
	pdata->ctrl_ram_size		= DM646X_EMAC_CNTRL_RAM_SIZE;
	pdata->version			= EMAC_VERSION_2;
	dm646x_emac_device.dev.platform_data = pdata;
	platform_device_register(&dm646x_emac_device);
}
#else

void dm646x_init_emac(struct emac_platform_data *unused) {}

#endif

static struct map_desc dm646x_io_desc[] = {
	{
		.virtual	= IO_VIRT,
		.pfn		= __phys_to_pfn(IO_PHYS),
		.length		= IO_SIZE,
		.type		= MT_DEVICE
	},
};

/* Contents of JTAG ID register used to identify exact cpu type */
static struct davinci_id dm646x_ids[] = {
	{
		.variant	= 0x0,
		.part_no	= 0xb770,
		.manufacturer	= 0x017,
		.cpu_id		= DAVINCI_CPU_ID_DM6467,
		.name		= "dm6467",
	},
};

static void __iomem *dm646x_psc_bases[] = {
	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
};

/*
 * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 * T1_TOP: Timer 1, top   :  <unused>
 */
struct davinci_timer_info dm646x_timer_info = {
	.timers		= davinci_timer_instance,
	.clockevent_id	= T0_BOT,
	.clocksource_id	= T0_TOP,
};

static struct davinci_soc_info davinci_soc_info_dm646x = {
	.io_desc		= dm646x_io_desc,
	.io_desc_num		= ARRAY_SIZE(dm646x_io_desc),
	.jtag_id_base		= IO_ADDRESS(0x01c40028),
	.ids			= dm646x_ids,
	.ids_num		= ARRAY_SIZE(dm646x_ids),
	.cpu_clks		= dm646x_clks,
	.psc_bases		= dm646x_psc_bases,
	.psc_bases_num		= ARRAY_SIZE(dm646x_psc_bases),
	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
	.pinmux_pins		= dm646x_pins,
	.pinmux_pins_num	= ARRAY_SIZE(dm646x_pins),
	.intc_base		= IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
	.intc_type		= DAVINCI_INTC_TYPE_AINTC,
	.intc_irq_prios		= dm646x_default_priorities,
	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
	.timer_info		= &dm646x_timer_info,
	.wdt_base		= IO_ADDRESS(DAVINCI_WDOG_BASE),
	.gpio_base		= IO_ADDRESS(DAVINCI_GPIO_BASE),
	.gpio_num		= 43, /* Only 33 usable */
	.gpio_irq		= IRQ_DM646X_GPIOBNK0,
};

void __init dm646x_init(void)
{
	davinci_common_init(&davinci_soc_info_dm646x);
}

static int __init dm646x_init_devices(void)
{
	if (!cpu_is_davinci_dm646x())
		return 0;

	platform_device_register(&dm646x_edma_device);
	return 0;
}
postcore_initcall(dm646x_init_devices);
Commit	Line	Data
e38d92fd KH	1	/*
	2	* TI DaVinci DM644x chip specific setup
	3	*
	4	* Author: Kevin Hilman, Deep Root Systems, LLC
	5	*
	6	* 2007 (c) Deep Root Systems, LLC. This file is licensed under
	7	* the terms of the GNU General Public License version 2. This program
	8	* is licensed "as is" without any warranty of any kind, whether express
	9	* or implied.
	10	*/
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/clk.h>
	14	#include <linux/platform_device.h>
a994955c	15	#include <linux/gpio.h>
e38d92fd	16
79c3c0b7 MG	17	#include <asm/mach/map.h>
79c3c0b7 MG	18
e38d92fd KH	19	#include <mach/dm646x.h>
	20	#include <mach/clock.h>
	21	#include <mach/cputype.h>
	22	#include <mach/edma.h>
	23	#include <mach/irqs.h>
	24	#include <mach/psc.h>
	25	#include <mach/mux.h>
f64691b3	26	#include <mach/time.h>
79c3c0b7	27	#include <mach/common.h>
e38d92fd KH	28
	29	#include "clock.h"
	30	#include "mux.h"
	31
	32	/*
	33	* Device specific clocks
	34	*/
	35	#define DM646X_REF_FREQ 27000000
	36	#define DM646X_AUX_FREQ 24000000
	37
	38	static struct pll_data pll1_data = {
	39	.num = 1,
	40	.phys_base = DAVINCI_PLL1_BASE,
	41	};
	42
	43	static struct pll_data pll2_data = {
	44	.num = 2,
	45	.phys_base = DAVINCI_PLL2_BASE,
	46	};
	47
	48	static struct clk ref_clk = {
	49	.name = "ref_clk",
	50	.rate = DM646X_REF_FREQ,
	51	};
	52
	53	static struct clk aux_clkin = {
	54	.name = "aux_clkin",
	55	.rate = DM646X_AUX_FREQ,
	56	};
	57
	58	static struct clk pll1_clk = {
	59	.name = "pll1",
	60	.parent = &ref_clk,
	61	.pll_data = &pll1_data,
	62	.flags = CLK_PLL,
	63	};
	64
	65	static struct clk pll1_sysclk1 = {
	66	.name = "pll1_sysclk1",
	67	.parent = &pll1_clk,
	68	.flags = CLK_PLL,
	69	.div_reg = PLLDIV1,
	70	};
	71
	72	static struct clk pll1_sysclk2 = {
	73	.name = "pll1_sysclk2",
	74	.parent = &pll1_clk,
	75	.flags = CLK_PLL,
	76	.div_reg = PLLDIV2,
	77	};
	78
	79	static struct clk pll1_sysclk3 = {
	80	.name = "pll1_sysclk3",
	81	.parent = &pll1_clk,
	82	.flags = CLK_PLL,
	83	.div_reg = PLLDIV3,
	84	};
	85
	86	static struct clk pll1_sysclk4 = {
	87	.name = "pll1_sysclk4",
	88	.parent = &pll1_clk,
	89	.flags = CLK_PLL,
	90	.div_reg = PLLDIV4,
	91	};
92
93	static struct clk pll1_sysclk5 = {
94	.name = "pll1_sysclk5",
95	.parent = &pll1_clk,
96	.flags = CLK_PLL,
97	.div_reg = PLLDIV5,
98	};
99
100	static struct clk pll1_sysclk6 = {
101	.name = "pll1_sysclk6",
102	.parent = &pll1_clk,
103	.flags = CLK_PLL,
104	.div_reg = PLLDIV6,
105	};
106
107	static struct clk pll1_sysclk8 = {
108	.name = "pll1_sysclk8",
109	.parent = &pll1_clk,
110	.flags = CLK_PLL,
111	.div_reg = PLLDIV8,
112	};
113
114	static struct clk pll1_sysclk9 = {
115	.name = "pll1_sysclk9",
116	.parent = &pll1_clk,
117	.flags = CLK_PLL,
118	.div_reg = PLLDIV9,
119	};
120
121	static struct clk pll1_sysclkbp = {
122	.name = "pll1_sysclkbp",
123	.parent = &pll1_clk,
124	.flags = CLK_PLL \| PRE_PLL,
125	.div_reg = BPDIV,
126	};
127
128	static struct clk pll1_aux_clk = {
129	.name = "pll1_aux_clk",
130	.parent = &pll1_clk,
131	.flags = CLK_PLL \| PRE_PLL,
132	};
133
134	static struct clk pll2_clk = {
135	.name = "pll2_clk",
136	.parent = &ref_clk,
137	.pll_data = &pll2_data,
138	.flags = CLK_PLL,
139	};
140
141	static struct clk pll2_sysclk1 = {
142	.name = "pll2_sysclk1",
143	.parent = &pll2_clk,
144	.flags = CLK_PLL,
145	.div_reg = PLLDIV1,
146	};
147
148	static struct clk dsp_clk = {
149	.name = "dsp",
150	.parent = &pll1_sysclk1,
151	.lpsc = DM646X_LPSC_C64X_CPU,
152	.flags = PSC_DSP,
153	.usecount = 1, /* REVISIT how to disable? */
154	};
155
156	static struct clk arm_clk = {
157	.name = "arm",
158	.parent = &pll1_sysclk2,
159	.lpsc = DM646X_LPSC_ARM,
160	.flags = ALWAYS_ENABLED,
161	};
162
163	static struct clk uart0_clk = {
164	.name = "uart0",
165	.parent = &aux_clkin,
166	.lpsc = DM646X_LPSC_UART0,
167	};
168
169	static struct clk uart1_clk = {
170	.name = "uart1",
171	.parent = &aux_clkin,
172	.lpsc = DM646X_LPSC_UART1,
173	};
174
175	static struct clk uart2_clk = {
176	.name = "uart2",
177	.parent = &aux_clkin,
178	.lpsc = DM646X_LPSC_UART2,
179	};
180
181	static struct clk i2c_clk = {
182	.name = "I2CCLK",
183	.parent = &pll1_sysclk3,
184	.lpsc = DM646X_LPSC_I2C,
185	};
186
187	static struct clk gpio_clk = {
188	.name = "gpio",
189	.parent = &pll1_sysclk3,
190	.lpsc = DM646X_LPSC_GPIO,
191	};
192
193	static struct clk aemif_clk = {
194	.name = "aemif",
195	.parent = &pll1_sysclk3,
196	.lpsc = DM646X_LPSC_AEMIF,
197	.flags = ALWAYS_ENABLED,
198	};
199
200	static struct clk emac_clk = {
201	.name = "emac",
202	.parent = &pll1_sysclk3,
203	.lpsc = DM646X_LPSC_EMAC,
204	};
205
206	static struct clk pwm0_clk = {
207	.name = "pwm0",
208	.parent = &pll1_sysclk3,
209	.lpsc = DM646X_LPSC_PWM0,
210	.usecount = 1, /* REVIST: disabling hangs system */
211	};
212
213	static struct clk pwm1_clk = {
214	.name = "pwm1",
215	.parent = &pll1_sysclk3,
216	.lpsc = DM646X_LPSC_PWM1,
217	.usecount = 1, /* REVIST: disabling hangs system */
218	};
219
220	static struct clk timer0_clk = {
221	.name = "timer0",
222	.parent = &pll1_sysclk3,
223	.lpsc = DM646X_LPSC_TIMER0,
224	};
225
226	static struct clk timer1_clk = {
227	.name = "timer1",
228	.parent = &pll1_sysclk3,
229	.lpsc = DM646X_LPSC_TIMER1,
230	};
231
232	static struct clk timer2_clk = {
233	.name = "timer2",
234	.parent = &pll1_sysclk3,
235	.flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
236	};
237
238	static struct clk vpif0_clk = {
239	.name = "vpif0",
240	.parent = &ref_clk,
241	.lpsc = DM646X_LPSC_VPSSMSTR,
242	.flags = ALWAYS_ENABLED,
243	};
244
245	static struct clk vpif1_clk = {
246	.name = "vpif1",
247	.parent = &ref_clk,
248	.lpsc = DM646X_LPSC_VPSSSLV,
249	.flags = ALWAYS_ENABLED,
250	};
251
252	struct davinci_clk dm646x_clks[] = {
253	CLK(NULL, "ref", &ref_clk),
254	CLK(NULL, "aux", &aux_clkin),
255	CLK(NULL, "pll1", &pll1_clk),
256	CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
257	CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
258	CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
259	CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
260	CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
261	CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
262	CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
263	CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
264	CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
265	CLK(NULL, "pll1_aux", &pll1_aux_clk),
266	CLK(NULL, "pll2", &pll2_clk),
267	CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
268	CLK(NULL, "dsp", &dsp_clk),
269	CLK(NULL, "arm", &arm_clk),
270	CLK(NULL, "uart0", &uart0_clk),
271	CLK(NULL, "uart1", &uart1_clk),
272	CLK(NULL, "uart2", &uart2_clk),
273	CLK("i2c_davinci.1", NULL, &i2c_clk),
274	CLK(NULL, "gpio", &gpio_clk),
275	CLK(NULL, "aemif", &aemif_clk),
276	CLK("davinci_emac.1", NULL, &emac_clk),
277	CLK(NULL, "pwm0", &pwm0_clk),
278	CLK(NULL, "pwm1", &pwm1_clk),
279	CLK(NULL, "timer0", &timer0_clk),
280	CLK(NULL, "timer1", &timer1_clk),
281	CLK("watchdog", NULL, &timer2_clk),
282	CLK(NULL, "vpif0", &vpif0_clk),
283	CLK(NULL, "vpif1", &vpif1_clk),
284	CLK(NULL, NULL, NULL),
285	};
286
ac7b75b5 KH	287	#if defined(CONFIG_TI_DAVINCI_EMAC) \|\| defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
	288	static struct resource dm646x_emac_resources[] = {
	289	{
	290	.start = DM646X_EMAC_BASE,
	291	.end = DM646X_EMAC_BASE + 0x47ff,
	292	.flags = IORESOURCE_MEM,
	293	},
	294	{
	295	.start = IRQ_DM646X_EMACRXTHINT,
	296	.end = IRQ_DM646X_EMACRXTHINT,
	297	.flags = IORESOURCE_IRQ,
	298	},
	299	{
	300	.start = IRQ_DM646X_EMACRXINT,
	301	.end = IRQ_DM646X_EMACRXINT,
	302	.flags = IORESOURCE_IRQ,
	303	},
	304	{
	305	.start = IRQ_DM646X_EMACTXINT,
	306	.end = IRQ_DM646X_EMACTXINT,
	307	.flags = IORESOURCE_IRQ,
	308	},
	309	{
	310	.start = IRQ_DM646X_EMACMISCINT,
	311	.end = IRQ_DM646X_EMACMISCINT,
	312	.flags = IORESOURCE_IRQ,
	313	},
	314	};
	315
	316	static struct platform_device dm646x_emac_device = {
	317	.name = "davinci_emac",
	318	.id = 1,
	319	.num_resources = ARRAY_SIZE(dm646x_emac_resources),
	320	.resource = dm646x_emac_resources,
	321	};
	322
	323	#endif
	324
e38d92fd KH	325	/*
	326	* Device specific mux setup
	327	*
	328	* soc description mux mode mode mux dbg
	329	* reg offset mask mode
	330	*/
	331	static const struct mux_config dm646x_pins[] = {
0e585952	332	#ifdef CONFIG_DAVINCI_MUX
e38d92fd KH	333	MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true)
	334
	335	MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
	336
	337	MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
	338
	339	MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
	340
	341	MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
	342
	343	MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
	344
	345	MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
	346
	347	MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
	348
	349	MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
	350
	351	MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
	352
	353	MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
	354
	355	MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
	356
	357	MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
	358
	359	MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
0e585952	360	#endif
e38d92fd KH	361	};
e38d92fd KH	362
673dd36f MG	363	static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
	364	[IRQ_DM646X_VP_VERTINT0] = 7,
	365	[IRQ_DM646X_VP_VERTINT1] = 7,
	366	[IRQ_DM646X_VP_VERTINT2] = 7,
	367	[IRQ_DM646X_VP_VERTINT3] = 7,
	368	[IRQ_DM646X_VP_ERRINT] = 7,
	369	[IRQ_DM646X_RESERVED_1] = 7,
	370	[IRQ_DM646X_RESERVED_2] = 7,
	371	[IRQ_DM646X_WDINT] = 7,
	372	[IRQ_DM646X_CRGENINT0] = 7,
	373	[IRQ_DM646X_CRGENINT1] = 7,
	374	[IRQ_DM646X_TSIFINT0] = 7,
	375	[IRQ_DM646X_TSIFINT1] = 7,
	376	[IRQ_DM646X_VDCEINT] = 7,
	377	[IRQ_DM646X_USBINT] = 7,
	378	[IRQ_DM646X_USBDMAINT] = 7,
	379	[IRQ_DM646X_PCIINT] = 7,
	380	[IRQ_CCINT0] = 7, /* dma */
	381	[IRQ_CCERRINT] = 7, /* dma */
	382	[IRQ_TCERRINT0] = 7, /* dma */
	383	[IRQ_TCERRINT] = 7, /* dma */
	384	[IRQ_DM646X_TCERRINT2] = 7,
	385	[IRQ_DM646X_TCERRINT3] = 7,
	386	[IRQ_DM646X_IDE] = 7,
	387	[IRQ_DM646X_HPIINT] = 7,
	388	[IRQ_DM646X_EMACRXTHINT] = 7,
	389	[IRQ_DM646X_EMACRXINT] = 7,
	390	[IRQ_DM646X_EMACTXINT] = 7,
	391	[IRQ_DM646X_EMACMISCINT] = 7,
	392	[IRQ_DM646X_MCASP0TXINT] = 7,
	393	[IRQ_DM646X_MCASP0RXINT] = 7,
	394	[IRQ_AEMIFINT] = 7,
	395	[IRQ_DM646X_RESERVED_3] = 7,
	396	[IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
	397	[IRQ_TINT0_TINT34] = 7, /* clocksource */
	398	[IRQ_TINT1_TINT12] = 7, /* DSP timer */
	399	[IRQ_TINT1_TINT34] = 7, /* system tick */
	400	[IRQ_PWMINT0] = 7,
	401	[IRQ_PWMINT1] = 7,
	402	[IRQ_DM646X_VLQINT] = 7,
	403	[IRQ_I2C] = 7,
	404	[IRQ_UARTINT0] = 7,
	405	[IRQ_UARTINT1] = 7,
	406	[IRQ_DM646X_UARTINT2] = 7,
	407	[IRQ_DM646X_SPINT0] = 7,
	408	[IRQ_DM646X_SPINT1] = 7,
	409	[IRQ_DM646X_DSP2ARMINT] = 7,
	410	[IRQ_DM646X_RESERVED_4] = 7,
	411	[IRQ_DM646X_PSCINT] = 7,
	412	[IRQ_DM646X_GPIO0] = 7,
	413	[IRQ_DM646X_GPIO1] = 7,
	414	[IRQ_DM646X_GPIO2] = 7,
	415	[IRQ_DM646X_GPIO3] = 7,
	416	[IRQ_DM646X_GPIO4] = 7,
	417	[IRQ_DM646X_GPIO5] = 7,
	418	[IRQ_DM646X_GPIO6] = 7,
	419	[IRQ_DM646X_GPIO7] = 7,
	420	[IRQ_DM646X_GPIOBNK0] = 7,
	421	[IRQ_DM646X_GPIOBNK1] = 7,
	422	[IRQ_DM646X_GPIOBNK2] = 7,
	423	[IRQ_DM646X_DDRINT] = 7,
	424	[IRQ_DM646X_AEMIFINT] = 7,
	425	[IRQ_COMMTX] = 7,
	426	[IRQ_COMMRX] = 7,
427	[IRQ_EMUINT] = 7,
428	};
429
e38d92fd KH	430	/----------------------------------------------------------------------/
	431
	432	static const s8 dma_chan_dm646x_no_event[] = {
	433	0, 1, 2, 3, 13,
	434	14, 15, 24, 25, 26,
	435	27, 30, 31, 54, 55,
	436	56,
	437	-1
	438	};
	439
	440	static struct edma_soc_info dm646x_edma_info = {
	441	.n_channel = 64,
	442	.n_region = 6, /* 0-1, 4-7 */
	443	.n_slot = 512,
	444	.n_tc = 4,
	445	.noevent = dma_chan_dm646x_no_event,
	446	};
	447
	448	static struct resource edma_resources[] = {
	449	{
	450	.name = "edma_cc",
	451	.start = 0x01c00000,
	452	.end = 0x01c00000 + SZ_64K - 1,
	453	.flags = IORESOURCE_MEM,
	454	},
	455	{
	456	.name = "edma_tc0",
	457	.start = 0x01c10000,
	458	.end = 0x01c10000 + SZ_1K - 1,
	459	.flags = IORESOURCE_MEM,
	460	},
	461	{
	462	.name = "edma_tc1",
	463	.start = 0x01c10400,
	464	.end = 0x01c10400 + SZ_1K - 1,
	465	.flags = IORESOURCE_MEM,
	466	},
	467	{
	468	.name = "edma_tc2",
	469	.start = 0x01c10800,
	470	.end = 0x01c10800 + SZ_1K - 1,
	471	.flags = IORESOURCE_MEM,
	472	},
	473	{
	474	.name = "edma_tc3",
	475	.start = 0x01c10c00,
	476	.end = 0x01c10c00 + SZ_1K - 1,
	477	.flags = IORESOURCE_MEM,
	478	},
	479	{
	480	.start = IRQ_CCINT0,
	481	.flags = IORESOURCE_IRQ,
	482	},
	483	{
	484	.start = IRQ_CCERRINT,
	485	.flags = IORESOURCE_IRQ,
	486	},
	487	/* not using TC_ERR /
	488	};
	489
	490	static struct platform_device dm646x_edma_device = {
	491	.name = "edma",
	492	.id = -1,
	493	.dev.platform_data = &dm646x_edma_info,
494	.num_resources = ARRAY_SIZE(edma_resources),
495	.resource = edma_resources,
496	};
497
498	/----------------------------------------------------------------------/
499
ac7b75b5 KH	500	#if defined(CONFIG_TI_DAVINCI_EMAC) \|\| defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
	501
	502	void dm646x_init_emac(struct emac_platform_data *pdata)
	503	{
	504	pdata->ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET;
	505	pdata->ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET;
	506	pdata->ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET;
	507	pdata->mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET;
	508	pdata->ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE;
	509	pdata->version = EMAC_VERSION_2;
	510	dm646x_emac_device.dev.platform_data = pdata;
	511	platform_device_register(&dm646x_emac_device);
	512	}
	513	#else
	514
	515	void dm646x_init_emac(struct emac_platform_data *unused) {}
	516
	517	#endif
	518
79c3c0b7 MG	519	static struct map_desc dm646x_io_desc[] = {
	520	{
	521	.virtual = IO_VIRT,
	522	.pfn = __phys_to_pfn(IO_PHYS),
	523	.length = IO_SIZE,
	524	.type = MT_DEVICE
	525	},
	526	};
	527
b9ab1279 MG	528	/* Contents of JTAG ID register used to identify exact cpu type */
	529	static struct davinci_id dm646x_ids[] = {
	530	{
	531	.variant = 0x0,
	532	.part_no = 0xb770,
	533	.manufacturer = 0x017,
	534	.cpu_id = DAVINCI_CPU_ID_DM6467,
	535	.name = "dm6467",
	536	},
	537	};
	538
d81d188c MG	539	static void __iomem *dm646x_psc_bases[] = {
	540	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
	541	};
	542
f64691b3 MG	543	/*
	544	* T0_BOT: Timer 0, bottom: clockevent source for hrtimers
	545	* T0_TOP: Timer 0, top : clocksource for generic timekeeping
	546	* T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
	547	* T1_TOP: Timer 1, top : <unused>
	548	*/
	549	struct davinci_timer_info dm646x_timer_info = {
	550	.timers = davinci_timer_instance,
	551	.clockevent_id = T0_BOT,
	552	.clocksource_id = T0_TOP,
	553	};
	554
79c3c0b7 MG	555	static struct davinci_soc_info davinci_soc_info_dm646x = {
	556	.io_desc = dm646x_io_desc,
	557	.io_desc_num = ARRAY_SIZE(dm646x_io_desc),
b9ab1279 MG	558	.jtag_id_base = IO_ADDRESS(0x01c40028),
	559	.ids = dm646x_ids,
	560	.ids_num = ARRAY_SIZE(dm646x_ids),
66e0c399	561	.cpu_clks = dm646x_clks,
d81d188c MG	562	.psc_bases = dm646x_psc_bases,
d81d188c MG	563	.psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
0e585952 MG	564	.pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
	565	.pinmux_pins = dm646x_pins,
	566	.pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
673dd36f MG	567	.intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
	568	.intc_type = DAVINCI_INTC_TYPE_AINTC,
	569	.intc_irq_prios = dm646x_default_priorities,
	570	.intc_irq_num = DAVINCI_N_AINTC_IRQ,
f64691b3	571	.timer_info = &dm646x_timer_info,
951d6f6d	572	.wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE),
a994955c MG	573	.gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
	574	.gpio_num = 43, /* Only 33 usable */
	575	.gpio_irq = IRQ_DM646X_GPIOBNK0,
79c3c0b7 MG	576	};
79c3c0b7 MG	577
e38d92fd KH	578	void __init dm646x_init(void)
e38d92fd KH	579	{
79c3c0b7	580	davinci_common_init(&davinci_soc_info_dm646x);
e38d92fd KH	581	}
	582
	583	static int __init dm646x_init_devices(void)
	584	{
	585	if (!cpu_is_davinci_dm646x())
	586	return 0;
	587
	588	platform_device_register(&dm646x_edma_device);
	589	return 0;
	590	}
	591	postcore_initcall(dm646x_init_devices);