]>
Commit | Line | Data |
---|---|---|
e38d92fd KH |
1 | /* |
2 | * TI DaVinci DM644x chip specific setup | |
3 | * | |
4 | * Author: Kevin Hilman, Deep Root Systems, LLC | |
5 | * | |
6 | * 2007 (c) Deep Root Systems, LLC. This file is licensed under | |
7 | * the terms of the GNU General Public License version 2. This program | |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/clk.h> | |
14 | #include <linux/platform_device.h> | |
15 | ||
79c3c0b7 MG |
16 | #include <asm/mach/map.h> |
17 | ||
e38d92fd KH |
18 | #include <mach/dm646x.h> |
19 | #include <mach/clock.h> | |
20 | #include <mach/cputype.h> | |
21 | #include <mach/edma.h> | |
22 | #include <mach/irqs.h> | |
23 | #include <mach/psc.h> | |
24 | #include <mach/mux.h> | |
79c3c0b7 | 25 | #include <mach/common.h> |
e38d92fd KH |
26 | |
27 | #include "clock.h" | |
28 | #include "mux.h" | |
29 | ||
30 | /* | |
31 | * Device specific clocks | |
32 | */ | |
33 | #define DM646X_REF_FREQ 27000000 | |
34 | #define DM646X_AUX_FREQ 24000000 | |
35 | ||
36 | static struct pll_data pll1_data = { | |
37 | .num = 1, | |
38 | .phys_base = DAVINCI_PLL1_BASE, | |
39 | }; | |
40 | ||
41 | static struct pll_data pll2_data = { | |
42 | .num = 2, | |
43 | .phys_base = DAVINCI_PLL2_BASE, | |
44 | }; | |
45 | ||
46 | static struct clk ref_clk = { | |
47 | .name = "ref_clk", | |
48 | .rate = DM646X_REF_FREQ, | |
49 | }; | |
50 | ||
51 | static struct clk aux_clkin = { | |
52 | .name = "aux_clkin", | |
53 | .rate = DM646X_AUX_FREQ, | |
54 | }; | |
55 | ||
56 | static struct clk pll1_clk = { | |
57 | .name = "pll1", | |
58 | .parent = &ref_clk, | |
59 | .pll_data = &pll1_data, | |
60 | .flags = CLK_PLL, | |
61 | }; | |
62 | ||
63 | static struct clk pll1_sysclk1 = { | |
64 | .name = "pll1_sysclk1", | |
65 | .parent = &pll1_clk, | |
66 | .flags = CLK_PLL, | |
67 | .div_reg = PLLDIV1, | |
68 | }; | |
69 | ||
70 | static struct clk pll1_sysclk2 = { | |
71 | .name = "pll1_sysclk2", | |
72 | .parent = &pll1_clk, | |
73 | .flags = CLK_PLL, | |
74 | .div_reg = PLLDIV2, | |
75 | }; | |
76 | ||
77 | static struct clk pll1_sysclk3 = { | |
78 | .name = "pll1_sysclk3", | |
79 | .parent = &pll1_clk, | |
80 | .flags = CLK_PLL, | |
81 | .div_reg = PLLDIV3, | |
82 | }; | |
83 | ||
84 | static struct clk pll1_sysclk4 = { | |
85 | .name = "pll1_sysclk4", | |
86 | .parent = &pll1_clk, | |
87 | .flags = CLK_PLL, | |
88 | .div_reg = PLLDIV4, | |
89 | }; | |
90 | ||
91 | static struct clk pll1_sysclk5 = { | |
92 | .name = "pll1_sysclk5", | |
93 | .parent = &pll1_clk, | |
94 | .flags = CLK_PLL, | |
95 | .div_reg = PLLDIV5, | |
96 | }; | |
97 | ||
98 | static struct clk pll1_sysclk6 = { | |
99 | .name = "pll1_sysclk6", | |
100 | .parent = &pll1_clk, | |
101 | .flags = CLK_PLL, | |
102 | .div_reg = PLLDIV6, | |
103 | }; | |
104 | ||
105 | static struct clk pll1_sysclk8 = { | |
106 | .name = "pll1_sysclk8", | |
107 | .parent = &pll1_clk, | |
108 | .flags = CLK_PLL, | |
109 | .div_reg = PLLDIV8, | |
110 | }; | |
111 | ||
112 | static struct clk pll1_sysclk9 = { | |
113 | .name = "pll1_sysclk9", | |
114 | .parent = &pll1_clk, | |
115 | .flags = CLK_PLL, | |
116 | .div_reg = PLLDIV9, | |
117 | }; | |
118 | ||
119 | static struct clk pll1_sysclkbp = { | |
120 | .name = "pll1_sysclkbp", | |
121 | .parent = &pll1_clk, | |
122 | .flags = CLK_PLL | PRE_PLL, | |
123 | .div_reg = BPDIV, | |
124 | }; | |
125 | ||
126 | static struct clk pll1_aux_clk = { | |
127 | .name = "pll1_aux_clk", | |
128 | .parent = &pll1_clk, | |
129 | .flags = CLK_PLL | PRE_PLL, | |
130 | }; | |
131 | ||
132 | static struct clk pll2_clk = { | |
133 | .name = "pll2_clk", | |
134 | .parent = &ref_clk, | |
135 | .pll_data = &pll2_data, | |
136 | .flags = CLK_PLL, | |
137 | }; | |
138 | ||
139 | static struct clk pll2_sysclk1 = { | |
140 | .name = "pll2_sysclk1", | |
141 | .parent = &pll2_clk, | |
142 | .flags = CLK_PLL, | |
143 | .div_reg = PLLDIV1, | |
144 | }; | |
145 | ||
146 | static struct clk dsp_clk = { | |
147 | .name = "dsp", | |
148 | .parent = &pll1_sysclk1, | |
149 | .lpsc = DM646X_LPSC_C64X_CPU, | |
150 | .flags = PSC_DSP, | |
151 | .usecount = 1, /* REVISIT how to disable? */ | |
152 | }; | |
153 | ||
154 | static struct clk arm_clk = { | |
155 | .name = "arm", | |
156 | .parent = &pll1_sysclk2, | |
157 | .lpsc = DM646X_LPSC_ARM, | |
158 | .flags = ALWAYS_ENABLED, | |
159 | }; | |
160 | ||
161 | static struct clk uart0_clk = { | |
162 | .name = "uart0", | |
163 | .parent = &aux_clkin, | |
164 | .lpsc = DM646X_LPSC_UART0, | |
165 | }; | |
166 | ||
167 | static struct clk uart1_clk = { | |
168 | .name = "uart1", | |
169 | .parent = &aux_clkin, | |
170 | .lpsc = DM646X_LPSC_UART1, | |
171 | }; | |
172 | ||
173 | static struct clk uart2_clk = { | |
174 | .name = "uart2", | |
175 | .parent = &aux_clkin, | |
176 | .lpsc = DM646X_LPSC_UART2, | |
177 | }; | |
178 | ||
179 | static struct clk i2c_clk = { | |
180 | .name = "I2CCLK", | |
181 | .parent = &pll1_sysclk3, | |
182 | .lpsc = DM646X_LPSC_I2C, | |
183 | }; | |
184 | ||
185 | static struct clk gpio_clk = { | |
186 | .name = "gpio", | |
187 | .parent = &pll1_sysclk3, | |
188 | .lpsc = DM646X_LPSC_GPIO, | |
189 | }; | |
190 | ||
191 | static struct clk aemif_clk = { | |
192 | .name = "aemif", | |
193 | .parent = &pll1_sysclk3, | |
194 | .lpsc = DM646X_LPSC_AEMIF, | |
195 | .flags = ALWAYS_ENABLED, | |
196 | }; | |
197 | ||
198 | static struct clk emac_clk = { | |
199 | .name = "emac", | |
200 | .parent = &pll1_sysclk3, | |
201 | .lpsc = DM646X_LPSC_EMAC, | |
202 | }; | |
203 | ||
204 | static struct clk pwm0_clk = { | |
205 | .name = "pwm0", | |
206 | .parent = &pll1_sysclk3, | |
207 | .lpsc = DM646X_LPSC_PWM0, | |
208 | .usecount = 1, /* REVIST: disabling hangs system */ | |
209 | }; | |
210 | ||
211 | static struct clk pwm1_clk = { | |
212 | .name = "pwm1", | |
213 | .parent = &pll1_sysclk3, | |
214 | .lpsc = DM646X_LPSC_PWM1, | |
215 | .usecount = 1, /* REVIST: disabling hangs system */ | |
216 | }; | |
217 | ||
218 | static struct clk timer0_clk = { | |
219 | .name = "timer0", | |
220 | .parent = &pll1_sysclk3, | |
221 | .lpsc = DM646X_LPSC_TIMER0, | |
222 | }; | |
223 | ||
224 | static struct clk timer1_clk = { | |
225 | .name = "timer1", | |
226 | .parent = &pll1_sysclk3, | |
227 | .lpsc = DM646X_LPSC_TIMER1, | |
228 | }; | |
229 | ||
230 | static struct clk timer2_clk = { | |
231 | .name = "timer2", | |
232 | .parent = &pll1_sysclk3, | |
233 | .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */ | |
234 | }; | |
235 | ||
236 | static struct clk vpif0_clk = { | |
237 | .name = "vpif0", | |
238 | .parent = &ref_clk, | |
239 | .lpsc = DM646X_LPSC_VPSSMSTR, | |
240 | .flags = ALWAYS_ENABLED, | |
241 | }; | |
242 | ||
243 | static struct clk vpif1_clk = { | |
244 | .name = "vpif1", | |
245 | .parent = &ref_clk, | |
246 | .lpsc = DM646X_LPSC_VPSSSLV, | |
247 | .flags = ALWAYS_ENABLED, | |
248 | }; | |
249 | ||
250 | struct davinci_clk dm646x_clks[] = { | |
251 | CLK(NULL, "ref", &ref_clk), | |
252 | CLK(NULL, "aux", &aux_clkin), | |
253 | CLK(NULL, "pll1", &pll1_clk), | |
254 | CLK(NULL, "pll1_sysclk", &pll1_sysclk1), | |
255 | CLK(NULL, "pll1_sysclk", &pll1_sysclk2), | |
256 | CLK(NULL, "pll1_sysclk", &pll1_sysclk3), | |
257 | CLK(NULL, "pll1_sysclk", &pll1_sysclk4), | |
258 | CLK(NULL, "pll1_sysclk", &pll1_sysclk5), | |
259 | CLK(NULL, "pll1_sysclk", &pll1_sysclk6), | |
260 | CLK(NULL, "pll1_sysclk", &pll1_sysclk8), | |
261 | CLK(NULL, "pll1_sysclk", &pll1_sysclk9), | |
262 | CLK(NULL, "pll1_sysclk", &pll1_sysclkbp), | |
263 | CLK(NULL, "pll1_aux", &pll1_aux_clk), | |
264 | CLK(NULL, "pll2", &pll2_clk), | |
265 | CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), | |
266 | CLK(NULL, "dsp", &dsp_clk), | |
267 | CLK(NULL, "arm", &arm_clk), | |
268 | CLK(NULL, "uart0", &uart0_clk), | |
269 | CLK(NULL, "uart1", &uart1_clk), | |
270 | CLK(NULL, "uart2", &uart2_clk), | |
271 | CLK("i2c_davinci.1", NULL, &i2c_clk), | |
272 | CLK(NULL, "gpio", &gpio_clk), | |
273 | CLK(NULL, "aemif", &aemif_clk), | |
274 | CLK("davinci_emac.1", NULL, &emac_clk), | |
275 | CLK(NULL, "pwm0", &pwm0_clk), | |
276 | CLK(NULL, "pwm1", &pwm1_clk), | |
277 | CLK(NULL, "timer0", &timer0_clk), | |
278 | CLK(NULL, "timer1", &timer1_clk), | |
279 | CLK("watchdog", NULL, &timer2_clk), | |
280 | CLK(NULL, "vpif0", &vpif0_clk), | |
281 | CLK(NULL, "vpif1", &vpif1_clk), | |
282 | CLK(NULL, NULL, NULL), | |
283 | }; | |
284 | ||
ac7b75b5 KH |
285 | #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE) |
286 | static struct resource dm646x_emac_resources[] = { | |
287 | { | |
288 | .start = DM646X_EMAC_BASE, | |
289 | .end = DM646X_EMAC_BASE + 0x47ff, | |
290 | .flags = IORESOURCE_MEM, | |
291 | }, | |
292 | { | |
293 | .start = IRQ_DM646X_EMACRXTHINT, | |
294 | .end = IRQ_DM646X_EMACRXTHINT, | |
295 | .flags = IORESOURCE_IRQ, | |
296 | }, | |
297 | { | |
298 | .start = IRQ_DM646X_EMACRXINT, | |
299 | .end = IRQ_DM646X_EMACRXINT, | |
300 | .flags = IORESOURCE_IRQ, | |
301 | }, | |
302 | { | |
303 | .start = IRQ_DM646X_EMACTXINT, | |
304 | .end = IRQ_DM646X_EMACTXINT, | |
305 | .flags = IORESOURCE_IRQ, | |
306 | }, | |
307 | { | |
308 | .start = IRQ_DM646X_EMACMISCINT, | |
309 | .end = IRQ_DM646X_EMACMISCINT, | |
310 | .flags = IORESOURCE_IRQ, | |
311 | }, | |
312 | }; | |
313 | ||
314 | static struct platform_device dm646x_emac_device = { | |
315 | .name = "davinci_emac", | |
316 | .id = 1, | |
317 | .num_resources = ARRAY_SIZE(dm646x_emac_resources), | |
318 | .resource = dm646x_emac_resources, | |
319 | }; | |
320 | ||
321 | #endif | |
322 | ||
e38d92fd KH |
323 | /* |
324 | * Device specific mux setup | |
325 | * | |
326 | * soc description mux mode mode mux dbg | |
327 | * reg offset mask mode | |
328 | */ | |
329 | static const struct mux_config dm646x_pins[] = { | |
330 | MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true) | |
331 | ||
332 | MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false) | |
333 | ||
334 | MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false) | |
335 | ||
336 | MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true) | |
337 | ||
338 | MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true) | |
339 | ||
340 | MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true) | |
341 | ||
342 | MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true) | |
343 | ||
344 | MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true) | |
345 | ||
346 | MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true) | |
347 | ||
348 | MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true) | |
349 | ||
350 | MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true) | |
351 | ||
352 | MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true) | |
353 | ||
354 | MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true) | |
355 | ||
356 | MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true) | |
357 | }; | |
358 | ||
359 | /*----------------------------------------------------------------------*/ | |
360 | ||
361 | static const s8 dma_chan_dm646x_no_event[] = { | |
362 | 0, 1, 2, 3, 13, | |
363 | 14, 15, 24, 25, 26, | |
364 | 27, 30, 31, 54, 55, | |
365 | 56, | |
366 | -1 | |
367 | }; | |
368 | ||
369 | static struct edma_soc_info dm646x_edma_info = { | |
370 | .n_channel = 64, | |
371 | .n_region = 6, /* 0-1, 4-7 */ | |
372 | .n_slot = 512, | |
373 | .n_tc = 4, | |
374 | .noevent = dma_chan_dm646x_no_event, | |
375 | }; | |
376 | ||
377 | static struct resource edma_resources[] = { | |
378 | { | |
379 | .name = "edma_cc", | |
380 | .start = 0x01c00000, | |
381 | .end = 0x01c00000 + SZ_64K - 1, | |
382 | .flags = IORESOURCE_MEM, | |
383 | }, | |
384 | { | |
385 | .name = "edma_tc0", | |
386 | .start = 0x01c10000, | |
387 | .end = 0x01c10000 + SZ_1K - 1, | |
388 | .flags = IORESOURCE_MEM, | |
389 | }, | |
390 | { | |
391 | .name = "edma_tc1", | |
392 | .start = 0x01c10400, | |
393 | .end = 0x01c10400 + SZ_1K - 1, | |
394 | .flags = IORESOURCE_MEM, | |
395 | }, | |
396 | { | |
397 | .name = "edma_tc2", | |
398 | .start = 0x01c10800, | |
399 | .end = 0x01c10800 + SZ_1K - 1, | |
400 | .flags = IORESOURCE_MEM, | |
401 | }, | |
402 | { | |
403 | .name = "edma_tc3", | |
404 | .start = 0x01c10c00, | |
405 | .end = 0x01c10c00 + SZ_1K - 1, | |
406 | .flags = IORESOURCE_MEM, | |
407 | }, | |
408 | { | |
409 | .start = IRQ_CCINT0, | |
410 | .flags = IORESOURCE_IRQ, | |
411 | }, | |
412 | { | |
413 | .start = IRQ_CCERRINT, | |
414 | .flags = IORESOURCE_IRQ, | |
415 | }, | |
416 | /* not using TC*_ERR */ | |
417 | }; | |
418 | ||
419 | static struct platform_device dm646x_edma_device = { | |
420 | .name = "edma", | |
421 | .id = -1, | |
422 | .dev.platform_data = &dm646x_edma_info, | |
423 | .num_resources = ARRAY_SIZE(edma_resources), | |
424 | .resource = edma_resources, | |
425 | }; | |
426 | ||
427 | /*----------------------------------------------------------------------*/ | |
428 | ||
ac7b75b5 KH |
429 | #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE) |
430 | ||
431 | void dm646x_init_emac(struct emac_platform_data *pdata) | |
432 | { | |
433 | pdata->ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET; | |
434 | pdata->ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET; | |
435 | pdata->ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET; | |
436 | pdata->mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET; | |
437 | pdata->ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE; | |
438 | pdata->version = EMAC_VERSION_2; | |
439 | dm646x_emac_device.dev.platform_data = pdata; | |
440 | platform_device_register(&dm646x_emac_device); | |
441 | } | |
442 | #else | |
443 | ||
444 | void dm646x_init_emac(struct emac_platform_data *unused) {} | |
445 | ||
446 | #endif | |
447 | ||
79c3c0b7 MG |
448 | static struct map_desc dm646x_io_desc[] = { |
449 | { | |
450 | .virtual = IO_VIRT, | |
451 | .pfn = __phys_to_pfn(IO_PHYS), | |
452 | .length = IO_SIZE, | |
453 | .type = MT_DEVICE | |
454 | }, | |
455 | }; | |
456 | ||
b9ab1279 MG |
457 | /* Contents of JTAG ID register used to identify exact cpu type */ |
458 | static struct davinci_id dm646x_ids[] = { | |
459 | { | |
460 | .variant = 0x0, | |
461 | .part_no = 0xb770, | |
462 | .manufacturer = 0x017, | |
463 | .cpu_id = DAVINCI_CPU_ID_DM6467, | |
464 | .name = "dm6467", | |
465 | }, | |
466 | }; | |
467 | ||
d81d188c MG |
468 | static void __iomem *dm646x_psc_bases[] = { |
469 | IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE), | |
470 | }; | |
471 | ||
79c3c0b7 MG |
472 | static struct davinci_soc_info davinci_soc_info_dm646x = { |
473 | .io_desc = dm646x_io_desc, | |
474 | .io_desc_num = ARRAY_SIZE(dm646x_io_desc), | |
b9ab1279 MG |
475 | .jtag_id_base = IO_ADDRESS(0x01c40028), |
476 | .ids = dm646x_ids, | |
477 | .ids_num = ARRAY_SIZE(dm646x_ids), | |
66e0c399 | 478 | .cpu_clks = dm646x_clks, |
d81d188c MG |
479 | .psc_bases = dm646x_psc_bases, |
480 | .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases), | |
79c3c0b7 MG |
481 | }; |
482 | ||
e38d92fd KH |
483 | void __init dm646x_init(void) |
484 | { | |
79c3c0b7 | 485 | davinci_common_init(&davinci_soc_info_dm646x); |
e38d92fd KH |
486 | davinci_mux_register(dm646x_pins, ARRAY_SIZE(dm646x_pins)); |
487 | } | |
488 | ||
489 | static int __init dm646x_init_devices(void) | |
490 | { | |
491 | if (!cpu_is_davinci_dm646x()) | |
492 | return 0; | |
493 | ||
494 | platform_device_register(&dm646x_edma_device); | |
495 | return 0; | |
496 | } | |
497 | postcore_initcall(dm646x_init_devices); |