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Commit | Line | Data |
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3d9edf09 VB |
1 | /* |
2 | * TI DaVinci GPIO Support | |
3 | * | |
dce1115b | 4 | * Copyright (c) 2006-2007 David Brownell |
3d9edf09 VB |
5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/errno.h> | |
14 | #include <linux/kernel.h> | |
3d9edf09 VB |
15 | #include <linux/clk.h> |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
3d9edf09 | 18 | |
a09e64fb | 19 | #include <mach/gpio.h> |
3d9edf09 VB |
20 | |
21 | #include <asm/mach/irq.h> | |
22 | ||
dce1115b | 23 | static DEFINE_SPINLOCK(gpio_lock); |
3d9edf09 | 24 | |
ba4a984e | 25 | #define chip2controller(chip) \ |
99e9e52d | 26 | container_of(chip, struct davinci_gpio_controller, chip) |
ba4a984e | 27 | |
99e9e52d | 28 | static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; |
3d9edf09 | 29 | |
3d9edf09 | 30 | /* create a non-inlined version */ |
99e9e52d | 31 | static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio) |
3d9edf09 VB |
32 | { |
33 | return __gpio_to_controller(gpio); | |
34 | } | |
35 | ||
99e9e52d | 36 | static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) |
21ce873d | 37 | { |
99e9e52d | 38 | struct davinci_gpio_regs __iomem *g; |
21ce873d | 39 | |
99e9e52d | 40 | g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq); |
21ce873d KH |
41 | |
42 | return g; | |
43 | } | |
44 | ||
dc756026 | 45 | static int __init davinci_gpio_irq_setup(void); |
dce1115b DB |
46 | |
47 | /*--------------------------------------------------------------------------*/ | |
48 | ||
3d9edf09 | 49 | /* |
dce1115b DB |
50 | * board setup code *MUST* set PINMUX0 and PINMUX1 as |
51 | * needed, and enable the GPIO clock. | |
3d9edf09 | 52 | */ |
dce1115b | 53 | |
ba4a984e CC |
54 | static inline int __davinci_direction(struct gpio_chip *chip, |
55 | unsigned offset, bool out, int value) | |
3d9edf09 | 56 | { |
99e9e52d CC |
57 | struct davinci_gpio_controller *d = chip2controller(chip); |
58 | struct davinci_gpio_regs __iomem *g = d->regs; | |
dce1115b | 59 | u32 temp; |
ba4a984e | 60 | u32 mask = 1 << offset; |
3d9edf09 | 61 | |
dce1115b DB |
62 | spin_lock(&gpio_lock); |
63 | temp = __raw_readl(&g->dir); | |
ba4a984e CC |
64 | if (out) { |
65 | temp &= ~mask; | |
66 | __raw_writel(mask, value ? &g->set_data : &g->clr_data); | |
67 | } else { | |
68 | temp |= mask; | |
69 | } | |
dce1115b DB |
70 | __raw_writel(temp, &g->dir); |
71 | spin_unlock(&gpio_lock); | |
3d9edf09 | 72 | |
dce1115b DB |
73 | return 0; |
74 | } | |
3d9edf09 | 75 | |
ba4a984e CC |
76 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
77 | { | |
78 | return __davinci_direction(chip, offset, false, 0); | |
79 | } | |
80 | ||
81 | static int | |
82 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) | |
83 | { | |
84 | return __davinci_direction(chip, offset, true, value); | |
85 | } | |
86 | ||
3d9edf09 VB |
87 | /* |
88 | * Read the pin's value (works even if it's set up as output); | |
89 | * returns zero/nonzero. | |
90 | * | |
91 | * Note that changes are synched to the GPIO clock, so reading values back | |
92 | * right after you've set them may give old values. | |
93 | */ | |
dce1115b | 94 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
3d9edf09 | 95 | { |
99e9e52d CC |
96 | struct davinci_gpio_controller *d = chip2controller(chip); |
97 | struct davinci_gpio_regs __iomem *g = d->regs; | |
3d9edf09 | 98 | |
dce1115b | 99 | return (1 << offset) & __raw_readl(&g->in_data); |
3d9edf09 | 100 | } |
3d9edf09 | 101 | |
dce1115b DB |
102 | /* |
103 | * Assuming the pin is muxed as a gpio output, set its output value. | |
104 | */ | |
105 | static void | |
106 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 107 | { |
99e9e52d CC |
108 | struct davinci_gpio_controller *d = chip2controller(chip); |
109 | struct davinci_gpio_regs __iomem *g = d->regs; | |
3d9edf09 | 110 | |
dce1115b DB |
111 | __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); |
112 | } | |
113 | ||
114 | static int __init davinci_gpio_setup(void) | |
115 | { | |
116 | int i, base; | |
a994955c MG |
117 | unsigned ngpio; |
118 | struct davinci_soc_info *soc_info = &davinci_soc_info; | |
dce1115b | 119 | |
a994955c MG |
120 | /* |
121 | * The gpio banks conceptually expose a segmented bitmap, | |
474dad54 DB |
122 | * and "ngpio" is one more than the largest zero-based |
123 | * bit index that's valid. | |
124 | */ | |
a994955c MG |
125 | ngpio = soc_info->gpio_num; |
126 | if (ngpio == 0) { | |
474dad54 DB |
127 | pr_err("GPIO setup: how many GPIOs?\n"); |
128 | return -EINVAL; | |
129 | } | |
130 | ||
131 | if (WARN_ON(DAVINCI_N_GPIO < ngpio)) | |
132 | ngpio = DAVINCI_N_GPIO; | |
133 | ||
134 | for (i = 0, base = 0; base < ngpio; i++, base += 32) { | |
dce1115b DB |
135 | chips[i].chip.label = "DaVinci"; |
136 | ||
137 | chips[i].chip.direction_input = davinci_direction_in; | |
138 | chips[i].chip.get = davinci_gpio_get; | |
139 | chips[i].chip.direction_output = davinci_direction_out; | |
140 | chips[i].chip.set = davinci_gpio_set; | |
141 | ||
142 | chips[i].chip.base = base; | |
474dad54 | 143 | chips[i].chip.ngpio = ngpio - base; |
dce1115b DB |
144 | if (chips[i].chip.ngpio > 32) |
145 | chips[i].chip.ngpio = 32; | |
146 | ||
99e9e52d | 147 | chips[i].regs = gpio2regs(base); |
dce1115b DB |
148 | |
149 | gpiochip_add(&chips[i].chip); | |
150 | } | |
3d9edf09 | 151 | |
dc756026 | 152 | davinci_gpio_irq_setup(); |
3d9edf09 VB |
153 | return 0; |
154 | } | |
dce1115b | 155 | pure_initcall(davinci_gpio_setup); |
3d9edf09 | 156 | |
dce1115b | 157 | /*--------------------------------------------------------------------------*/ |
3d9edf09 VB |
158 | /* |
159 | * We expect irqs will normally be set up as input pins, but they can also be | |
160 | * used as output pins ... which is convenient for testing. | |
161 | * | |
474dad54 | 162 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
7a36071e | 163 | * to their GPIOBNK0 irq, with a bit less overhead. |
3d9edf09 | 164 | * |
474dad54 | 165 | * All those INTC hookups (direct, plus several IRQ banks) can also |
3d9edf09 VB |
166 | * serve as EDMA event triggers. |
167 | */ | |
168 | ||
169 | static void gpio_irq_disable(unsigned irq) | |
170 | { | |
99e9e52d | 171 | struct davinci_gpio_regs __iomem *g = irq2regs(irq); |
7a36071e | 172 | u32 mask = (u32) get_irq_data(irq); |
3d9edf09 VB |
173 | |
174 | __raw_writel(mask, &g->clr_falling); | |
175 | __raw_writel(mask, &g->clr_rising); | |
176 | } | |
177 | ||
178 | static void gpio_irq_enable(unsigned irq) | |
179 | { | |
99e9e52d | 180 | struct davinci_gpio_regs __iomem *g = irq2regs(irq); |
7a36071e | 181 | u32 mask = (u32) get_irq_data(irq); |
df4aab46 | 182 | unsigned status = irq_desc[irq].status; |
3d9edf09 | 183 | |
df4aab46 DB |
184 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
185 | if (!status) | |
186 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | |
187 | ||
188 | if (status & IRQ_TYPE_EDGE_FALLING) | |
3d9edf09 | 189 | __raw_writel(mask, &g->set_falling); |
df4aab46 | 190 | if (status & IRQ_TYPE_EDGE_RISING) |
3d9edf09 VB |
191 | __raw_writel(mask, &g->set_rising); |
192 | } | |
193 | ||
194 | static int gpio_irq_type(unsigned irq, unsigned trigger) | |
195 | { | |
99e9e52d | 196 | struct davinci_gpio_regs __iomem *g = irq2regs(irq); |
7a36071e | 197 | u32 mask = (u32) get_irq_data(irq); |
3d9edf09 VB |
198 | |
199 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
200 | return -EINVAL; | |
201 | ||
202 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; | |
203 | irq_desc[irq].status |= trigger; | |
204 | ||
df4aab46 DB |
205 | /* don't enable the IRQ if it's currently disabled */ |
206 | if (irq_desc[irq].depth == 0) { | |
207 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) | |
208 | ? &g->set_falling : &g->clr_falling); | |
209 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) | |
210 | ? &g->set_rising : &g->clr_rising); | |
211 | } | |
3d9edf09 VB |
212 | return 0; |
213 | } | |
214 | ||
215 | static struct irq_chip gpio_irqchip = { | |
216 | .name = "GPIO", | |
217 | .enable = gpio_irq_enable, | |
218 | .disable = gpio_irq_disable, | |
219 | .set_type = gpio_irq_type, | |
220 | }; | |
221 | ||
222 | static void | |
223 | gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
224 | { | |
99e9e52d | 225 | struct davinci_gpio_regs __iomem *g = irq2regs(irq); |
3d9edf09 VB |
226 | u32 mask = 0xffff; |
227 | ||
228 | /* we only care about one bank */ | |
229 | if (irq & 1) | |
230 | mask <<= 16; | |
231 | ||
232 | /* temporarily mask (level sensitive) parent IRQ */ | |
dc756026 | 233 | desc->chip->mask(irq); |
3d9edf09 VB |
234 | desc->chip->ack(irq); |
235 | while (1) { | |
236 | u32 status; | |
3d9edf09 VB |
237 | int n; |
238 | int res; | |
239 | ||
240 | /* ack any irqs */ | |
241 | status = __raw_readl(&g->intstat) & mask; | |
242 | if (!status) | |
243 | break; | |
244 | __raw_writel(status, &g->intstat); | |
245 | if (irq & 1) | |
246 | status >>= 16; | |
247 | ||
248 | /* now demux them to the right lowlevel handler */ | |
249 | n = (int)get_irq_data(irq); | |
3d9edf09 VB |
250 | while (status) { |
251 | res = ffs(status); | |
252 | n += res; | |
d8aa0251 | 253 | generic_handle_irq(n - 1); |
3d9edf09 VB |
254 | status >>= res; |
255 | } | |
256 | } | |
257 | desc->chip->unmask(irq); | |
258 | /* now it may re-trigger */ | |
259 | } | |
260 | ||
7a36071e DB |
261 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) |
262 | { | |
99e9e52d | 263 | struct davinci_gpio_controller *d = chip2controller(chip); |
7a36071e DB |
264 | |
265 | if (d->irq_base >= 0) | |
266 | return d->irq_base + offset; | |
267 | else | |
268 | return -ENODEV; | |
269 | } | |
270 | ||
271 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | |
272 | { | |
273 | struct davinci_soc_info *soc_info = &davinci_soc_info; | |
274 | ||
275 | /* NOTE: we assume for now that only irqs in the first gpio_chip | |
276 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). | |
277 | */ | |
278 | if (offset < soc_info->gpio_unbanked) | |
279 | return soc_info->gpio_irq + offset; | |
280 | else | |
281 | return -ENODEV; | |
282 | } | |
283 | ||
284 | static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger) | |
285 | { | |
99e9e52d | 286 | struct davinci_gpio_regs __iomem *g = irq2regs(irq); |
7a36071e DB |
287 | u32 mask = (u32) get_irq_data(irq); |
288 | ||
289 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
290 | return -EINVAL; | |
291 | ||
292 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) | |
293 | ? &g->set_falling : &g->clr_falling); | |
294 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) | |
295 | ? &g->set_rising : &g->clr_rising); | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
3d9edf09 | 300 | /* |
474dad54 DB |
301 | * NOTE: for suspend/resume, probably best to make a platform_device with |
302 | * suspend_late/resume_resume calls hooking into results of the set_wake() | |
3d9edf09 VB |
303 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
304 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 | |
474dad54 | 305 | * (dm6446) can be set appropriately for GPIOV33 pins. |
3d9edf09 VB |
306 | */ |
307 | ||
308 | static int __init davinci_gpio_irq_setup(void) | |
309 | { | |
310 | unsigned gpio, irq, bank; | |
311 | struct clk *clk; | |
474dad54 | 312 | u32 binten = 0; |
a994955c MG |
313 | unsigned ngpio, bank_irq; |
314 | struct davinci_soc_info *soc_info = &davinci_soc_info; | |
99e9e52d | 315 | struct davinci_gpio_regs __iomem *g; |
a994955c MG |
316 | |
317 | ngpio = soc_info->gpio_num; | |
474dad54 | 318 | |
a994955c MG |
319 | bank_irq = soc_info->gpio_irq; |
320 | if (bank_irq == 0) { | |
474dad54 DB |
321 | printk(KERN_ERR "Don't know first GPIO bank IRQ.\n"); |
322 | return -EINVAL; | |
323 | } | |
3d9edf09 VB |
324 | |
325 | clk = clk_get(NULL, "gpio"); | |
326 | if (IS_ERR(clk)) { | |
327 | printk(KERN_ERR "Error %ld getting gpio clock?\n", | |
328 | PTR_ERR(clk)); | |
474dad54 | 329 | return PTR_ERR(clk); |
3d9edf09 | 330 | } |
3d9edf09 VB |
331 | clk_enable(clk); |
332 | ||
7a36071e DB |
333 | /* Arrange gpio_to_irq() support, handling either direct IRQs or |
334 | * banked IRQs. Having GPIOs in the first GPIO bank use direct | |
335 | * IRQs, while the others use banked IRQs, would need some setup | |
336 | * tweaks to recognize hardware which can do that. | |
337 | */ | |
338 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { | |
339 | chips[bank].chip.to_irq = gpio_to_irq_banked; | |
340 | chips[bank].irq_base = soc_info->gpio_unbanked | |
341 | ? -EINVAL | |
342 | : (soc_info->intc_irq_num + gpio); | |
343 | } | |
344 | ||
345 | /* | |
346 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO | |
347 | * controller only handling trigger modes. We currently assume no | |
348 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. | |
349 | */ | |
350 | if (soc_info->gpio_unbanked) { | |
351 | static struct irq_chip gpio_irqchip_unbanked; | |
352 | ||
353 | /* pass "bank 0" GPIO IRQs to AINTC */ | |
354 | chips[0].chip.to_irq = gpio_to_irq_unbanked; | |
355 | binten = BIT(0); | |
356 | ||
357 | /* AINTC handles mask/unmask; GPIO handles triggering */ | |
358 | irq = bank_irq; | |
359 | gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq)); | |
360 | gpio_irqchip_unbanked.name = "GPIO-AINTC"; | |
361 | gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked; | |
362 | ||
363 | /* default trigger: both edges */ | |
99e9e52d | 364 | g = gpio2regs(0); |
7a36071e DB |
365 | __raw_writel(~0, &g->set_falling); |
366 | __raw_writel(~0, &g->set_rising); | |
367 | ||
368 | /* set the direct IRQs up to use that irqchip */ | |
369 | for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { | |
370 | set_irq_chip(irq, &gpio_irqchip_unbanked); | |
371 | set_irq_data(irq, (void *) __gpio_mask(gpio)); | |
21ce873d | 372 | set_irq_chip_data(irq, (__force void *) g); |
7a36071e DB |
373 | irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH; |
374 | } | |
375 | ||
376 | goto done; | |
377 | } | |
378 | ||
379 | /* | |
380 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we | |
381 | * then chain through our own handler. | |
382 | */ | |
474dad54 DB |
383 | for (gpio = 0, irq = gpio_to_irq(0), bank = 0; |
384 | gpio < ngpio; | |
385 | bank++, bank_irq++) { | |
3d9edf09 VB |
386 | unsigned i; |
387 | ||
7a36071e | 388 | /* disabled by default, enabled only as needed */ |
99e9e52d | 389 | g = gpio2regs(gpio); |
3d9edf09 VB |
390 | __raw_writel(~0, &g->clr_falling); |
391 | __raw_writel(~0, &g->clr_rising); | |
392 | ||
393 | /* set up all irqs in this bank */ | |
474dad54 | 394 | set_irq_chained_handler(bank_irq, gpio_irq_handler); |
21ce873d KH |
395 | set_irq_chip_data(bank_irq, (__force void *) g); |
396 | set_irq_data(bank_irq, (void *) irq); | |
3d9edf09 | 397 | |
474dad54 | 398 | for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { |
3d9edf09 | 399 | set_irq_chip(irq, &gpio_irqchip); |
21ce873d | 400 | set_irq_chip_data(irq, (__force void *) g); |
7a36071e | 401 | set_irq_data(irq, (void *) __gpio_mask(gpio)); |
3d9edf09 VB |
402 | set_irq_handler(irq, handle_simple_irq); |
403 | set_irq_flags(irq, IRQF_VALID); | |
404 | } | |
474dad54 DB |
405 | |
406 | binten |= BIT(bank); | |
3d9edf09 VB |
407 | } |
408 | ||
7a36071e | 409 | done: |
3d9edf09 VB |
410 | /* BINTEN -- per-bank interrupt enable. genirq would also let these |
411 | * bits be set/cleared dynamically. | |
412 | */ | |
a994955c | 413 | __raw_writel(binten, soc_info->gpio_base + 0x08); |
3d9edf09 VB |
414 | |
415 | printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); | |
416 | ||
417 | return 0; | |
418 | } |