[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-davinci / pm.c

/*
 * DaVinci Power Management Routines
 *
 * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/pm.h>
#include <linux/suspend.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/spinlock.h>

#include <asm/cacheflush.h>
#include <asm/delay.h>
#include <asm/io.h>

#include <mach/common.h>
#include <mach/da8xx.h>
#include <mach/mux.h>
#include <mach/pm.h>

#include "clock.h"
#include "psc.h"
#include "sram.h"

#define DA850_PLL1_BASE		0x01e1a000
#define DEEPSLEEP_SLEEPCOUNT_MASK	0xFFFF
#define DEEPSLEEP_SLEEPCOUNT		128

static void (*davinci_sram_suspend) (struct davinci_pm_config *);
static struct davinci_pm_config pm_config = {
	.sleepcount = DEEPSLEEP_SLEEPCOUNT,
	.ddrpsc_num = DA8XX_LPSC1_EMIF3C,
};

static void davinci_sram_push(void *dest, void *src, unsigned int size)
{
	memcpy(dest, src, size);
	flush_icache_range((unsigned long)dest, (unsigned long)(dest + size));
}

static void davinci_pm_suspend(void)
{
	unsigned val;

	if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {

		/* Switch CPU PLL to bypass mode */
		val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
		val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
		__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);

		udelay(PLL_BYPASS_TIME);

		/* Powerdown CPU PLL */
		val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
		val |= PLLCTL_PLLPWRDN;
		__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
	}

	/* Configure sleep count in deep sleep register */
	val = __raw_readl(pm_config.deepsleep_reg);
	val &= ~DEEPSLEEP_SLEEPCOUNT_MASK,
	val |= pm_config.sleepcount;
	__raw_writel(val, pm_config.deepsleep_reg);

	/* System goes to sleep in this call */
	davinci_sram_suspend(&pm_config);

	if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {

		/* put CPU PLL in reset */
		val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
		val &= ~PLLCTL_PLLRST;
		__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);

		/* put CPU PLL in power down */
		val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
		val &= ~PLLCTL_PLLPWRDN;
		__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);

		/* wait for CPU PLL reset */
		udelay(PLL_RESET_TIME);

		/* bring CPU PLL out of reset */
		val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
		val |= PLLCTL_PLLRST;
		__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);

		/* Wait for CPU PLL to lock */
		udelay(PLL_LOCK_TIME);

		/* Remove CPU PLL from bypass mode */
		val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
		val &= ~PLLCTL_PLLENSRC;
		val |= PLLCTL_PLLEN;
		__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
	}
}

static int davinci_pm_enter(suspend_state_t state)
{
	int ret = 0;

	switch (state) {
	case PM_SUSPEND_MEM:
		davinci_pm_suspend();
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static const struct platform_suspend_ops davinci_pm_ops = {
	.enter		= davinci_pm_enter,
	.valid		= suspend_valid_only_mem,
};

int __init davinci_pm_init(void)
{
	int ret;

	ret = davinci_cfg_reg(DA850_RTC_ALARM);
	if (ret)
		return ret;

	pm_config.ddr2_ctlr_base = da8xx_get_mem_ctlr();
	pm_config.deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);

	pm_config.cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
	if (!pm_config.cpupll_reg_base)
		return -ENOMEM;

	pm_config.ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
	if (!pm_config.ddrpll_reg_base) {
		ret = -ENOMEM;
		goto no_ddrpll_mem;
	}

	pm_config.ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
	if (!pm_config.ddrpsc_reg_base) {
		ret = -ENOMEM;
		goto no_ddrpsc_mem;
	}

	davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
	if (!davinci_sram_suspend) {
		pr_err("PM: cannot allocate SRAM memory\n");
		ret = -ENOMEM;
		goto no_sram_mem;
	}

	davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend,
						davinci_cpu_suspend_sz);

	suspend_set_ops(&davinci_pm_ops);

	return 0;

no_sram_mem:
	iounmap(pm_config.ddrpsc_reg_base);
no_ddrpsc_mem:
	iounmap(pm_config.ddrpll_reg_base);
no_ddrpll_mem:
	iounmap(pm_config.cpupll_reg_base);
	return ret;
}
Commit	Line	Data
efc1bb8a SN	1	/*
	2	* DaVinci Power Management Routines
	3	*
	4	* Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/pm.h>
	12	#include <linux/suspend.h>
	13	#include <linux/module.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/clk.h>
	16	#include <linux/spinlock.h>
	17
	18	#include <asm/cacheflush.h>
	19	#include <asm/delay.h>
b7f080cf	20	#include <asm/io.h>
efc1bb8a	21
215a084d	22	#include <mach/common.h>
efc1bb8a	23	#include <mach/da8xx.h>
aa9aa1ec	24	#include <mach/mux.h>
efc1bb8a SN	25	#include <mach/pm.h>
	26
	27	#include "clock.h"
aa9aa1ec KH	28	#include "psc.h"
aa9aa1ec KH	29	#include "sram.h"
efc1bb8a	30
aa9aa1ec	31	#define DA850_PLL1_BASE 0x01e1a000
efc1bb8a	32	#define DEEPSLEEP_SLEEPCOUNT_MASK 0xFFFF
aa9aa1ec	33	#define DEEPSLEEP_SLEEPCOUNT 128
efc1bb8a SN	34
efc1bb8a SN	35	static void (davinci_sram_suspend) (struct davinci_pm_config );
aa9aa1ec KH	36	static struct davinci_pm_config pm_config = {
	37	.sleepcount = DEEPSLEEP_SLEEPCOUNT,
	38	.ddrpsc_num = DA8XX_LPSC1_EMIF3C,
	39	};
	40
efc1bb8a SN	41	static void davinci_sram_push(void dest, void src, unsigned int size)
	42	{
	43	memcpy(dest, src, size);
	44	flush_icache_range((unsigned long)dest, (unsigned long)(dest + size));
	45	}
	46
	47	static void davinci_pm_suspend(void)
	48	{
	49	unsigned val;
	50
1428ed1a	51	if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {
efc1bb8a SN	52
efc1bb8a SN	53	/* Switch CPU PLL to bypass mode */
1428ed1a	54	val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
efc1bb8a	55	val &= ~(PLLCTL_PLLENSRC \| PLLCTL_PLLEN);
1428ed1a	56	__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
efc1bb8a SN	57
	58	udelay(PLL_BYPASS_TIME);
	59
	60	/* Powerdown CPU PLL */
1428ed1a	61	val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
efc1bb8a	62	val \|= PLLCTL_PLLPWRDN;
1428ed1a	63	__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
efc1bb8a SN	64	}
	65
	66	/* Configure sleep count in deep sleep register */
1428ed1a	67	val = __raw_readl(pm_config.deepsleep_reg);
efc1bb8a	68	val &= ~DEEPSLEEP_SLEEPCOUNT_MASK,
1428ed1a KH	69	val \|= pm_config.sleepcount;
1428ed1a KH	70	__raw_writel(val, pm_config.deepsleep_reg);
efc1bb8a SN	71
efc1bb8a SN	72	/* System goes to sleep in this call */
1428ed1a	73	davinci_sram_suspend(&pm_config);
efc1bb8a	74
1428ed1a	75	if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) {
efc1bb8a SN	76
efc1bb8a SN	77	/* put CPU PLL in reset */
1428ed1a	78	val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
efc1bb8a	79	val &= ~PLLCTL_PLLRST;
1428ed1a	80	__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
efc1bb8a SN	81
efc1bb8a SN	82	/* put CPU PLL in power down */
1428ed1a	83	val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
efc1bb8a	84	val &= ~PLLCTL_PLLPWRDN;
1428ed1a	85	__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
efc1bb8a SN	86
	87	/* wait for CPU PLL reset */
	88	udelay(PLL_RESET_TIME);
	89
	90	/* bring CPU PLL out of reset */
1428ed1a	91	val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
efc1bb8a	92	val \|= PLLCTL_PLLRST;
1428ed1a	93	__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
efc1bb8a SN	94
	95	/* Wait for CPU PLL to lock */
	96	udelay(PLL_LOCK_TIME);
	97
	98	/* Remove CPU PLL from bypass mode */
1428ed1a	99	val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL);
efc1bb8a SN	100	val &= ~PLLCTL_PLLENSRC;
efc1bb8a SN	101	val \|= PLLCTL_PLLEN;
1428ed1a	102	__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL);
efc1bb8a SN	103	}
	104	}
	105
	106	static int davinci_pm_enter(suspend_state_t state)
	107	{
	108	int ret = 0;
	109
	110	switch (state) {
efc1bb8a SN	111	case PM_SUSPEND_MEM:
	112	davinci_pm_suspend();
	113	break;
	114	default:
	115	ret = -EINVAL;
	116	}
	117
	118	return ret;
	119	}
	120
2f55ac07	121	static const struct platform_suspend_ops davinci_pm_ops = {
efc1bb8a SN	122	.enter = davinci_pm_enter,
	123	.valid = suspend_valid_only_mem,
	124	};
	125
aa9aa1ec	126	int __init davinci_pm_init(void)
efc1bb8a	127	{
aa9aa1ec KH	128	int ret;
	129
	130	ret = davinci_cfg_reg(DA850_RTC_ALARM);
	131	if (ret)
	132	return ret;
	133
1428ed1a KH	134	pm_config.ddr2_ctlr_base = da8xx_get_mem_ctlr();
1428ed1a KH	135	pm_config.deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
aa9aa1ec	136
1428ed1a KH	137	pm_config.cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
1428ed1a KH	138	if (!pm_config.cpupll_reg_base)
aa9aa1ec KH	139	return -ENOMEM;
aa9aa1ec KH	140
1428ed1a KH	141	pm_config.ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
1428ed1a KH	142	if (!pm_config.ddrpll_reg_base) {
aa9aa1ec KH	143	ret = -ENOMEM;
	144	goto no_ddrpll_mem;
	145	}
	146
1428ed1a KH	147	pm_config.ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
1428ed1a KH	148	if (!pm_config.ddrpsc_reg_base) {
aa9aa1ec KH	149	ret = -ENOMEM;
aa9aa1ec KH	150	goto no_ddrpsc_mem;
efc1bb8a SN	151	}
	152
	153	davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
	154	if (!davinci_sram_suspend) {
aa9aa1ec	155	pr_err("PM: cannot allocate SRAM memory\n");
f3f6cc81 CJ	156	ret = -ENOMEM;
f3f6cc81 CJ	157	goto no_sram_mem;
efc1bb8a SN	158	}
	159
	160	davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend,
	161	davinci_cpu_suspend_sz);
	162
	163	suspend_set_ops(&davinci_pm_ops);
	164
95d7c1f1 CJ	165	return 0;
95d7c1f1 CJ	166
f3f6cc81 CJ	167	no_sram_mem:
f3f6cc81 CJ	168	iounmap(pm_config.ddrpsc_reg_base);
aa9aa1ec	169	no_ddrpsc_mem:
1428ed1a	170	iounmap(pm_config.ddrpll_reg_base);
aa9aa1ec	171	no_ddrpll_mem:
1428ed1a	172	iounmap(pm_config.cpupll_reg_base);
aa9aa1ec	173	return ret;
efc1bb8a	174	}