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7c6337e2 KH |
1 | /* |
2 | * TI DaVinci Power and Sleep Controller (PSC) | |
3 | * | |
4 | * Copyright (C) 2006 Texas Instruments. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | * | |
20 | */ | |
21 | #include <linux/kernel.h> | |
7c6337e2 | 22 | #include <linux/init.h> |
fced80c7 | 23 | #include <linux/io.h> |
7c6337e2 | 24 | |
c5b736d0 | 25 | #include <mach/cputype.h> |
a09e64fb | 26 | #include <mach/psc.h> |
7c6337e2 | 27 | |
a51ca38b SN |
28 | #include "clock.h" |
29 | ||
c5b736d0 | 30 | /* Return nonzero iff the domain's clock is active */ |
d81d188c | 31 | int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) |
7c6337e2 | 32 | { |
d81d188c MG |
33 | void __iomem *psc_base; |
34 | u32 mdstat; | |
35 | struct davinci_soc_info *soc_info = &davinci_soc_info; | |
36 | ||
37 | if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { | |
38 | pr_warning("PSC: Bad psc data: 0x%x[%d]\n", | |
39 | (int)soc_info->psc_bases, ctlr); | |
40 | return 0; | |
41 | } | |
42 | ||
e4c822c7 | 43 | psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K); |
d81d188c | 44 | mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); |
e4c822c7 | 45 | iounmap(psc_base); |
c5b736d0 KH |
46 | |
47 | /* if clocked, state can be "Enable" or "SyncReset" */ | |
48 | return mdstat & BIT(12); | |
7c6337e2 KH |
49 | } |
50 | ||
51 | /* Enable or disable a PSC domain */ | |
d81d188c | 52 | void davinci_psc_config(unsigned int domain, unsigned int ctlr, |
a51ca38b | 53 | unsigned int id, bool enable, u32 flags) |
7c6337e2 | 54 | { |
fe277d9b | 55 | u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl; |
d81d188c MG |
56 | void __iomem *psc_base; |
57 | struct davinci_soc_info *soc_info = &davinci_soc_info; | |
a51ca38b | 58 | u32 next_state = PSC_STATE_ENABLE; |
7c6337e2 | 59 | |
d81d188c MG |
60 | if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) { |
61 | pr_warning("PSC: Bad psc data: 0x%x[%d]\n", | |
62 | (int)soc_info->psc_bases, ctlr); | |
63 | return; | |
64 | } | |
65 | ||
e4c822c7 | 66 | psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K); |
d81d188c | 67 | |
a51ca38b SN |
68 | if (!enable) { |
69 | if (flags & PSC_SWRSTDISABLE) | |
70 | next_state = PSC_STATE_SWRSTDISABLE; | |
71 | else | |
72 | next_state = PSC_STATE_DISABLE; | |
73 | } | |
74 | ||
c5b736d0 | 75 | mdctl = __raw_readl(psc_base + MDCTL + 4 * id); |
fe277d9b MG |
76 | mdctl &= ~MDSTAT_STATE_MASK; |
77 | mdctl |= next_state; | |
aad70de2 SN |
78 | if (flags & PSC_FORCE) |
79 | mdctl |= MDCTL_FORCE; | |
c5b736d0 | 80 | __raw_writel(mdctl, psc_base + MDCTL + 4 * id); |
83f53220 | 81 | |
c5b736d0 | 82 | pdstat = __raw_readl(psc_base + PDSTAT); |
83f53220 | 83 | if ((pdstat & 0x00000001) == 0) { |
c5b736d0 | 84 | pdctl1 = __raw_readl(psc_base + PDCTL1); |
83f53220 | 85 | pdctl1 |= 0x1; |
c5b736d0 | 86 | __raw_writel(pdctl1, psc_base + PDCTL1); |
83f53220 VB |
87 | |
88 | ptcmd = 1 << domain; | |
c5b736d0 | 89 | __raw_writel(ptcmd, psc_base + PTCMD); |
7c6337e2 | 90 | |
83f53220 | 91 | do { |
c5b736d0 | 92 | epcpr = __raw_readl(psc_base + EPCPR); |
83f53220 | 93 | } while ((((epcpr >> domain) & 1) == 0)); |
7c6337e2 | 94 | |
c5b736d0 | 95 | pdctl1 = __raw_readl(psc_base + PDCTL1); |
83f53220 | 96 | pdctl1 |= 0x100; |
c5b736d0 | 97 | __raw_writel(pdctl1, psc_base + PDCTL1); |
7c6337e2 | 98 | } else { |
83f53220 | 99 | ptcmd = 1 << domain; |
c5b736d0 | 100 | __raw_writel(ptcmd, psc_base + PTCMD); |
7c6337e2 KH |
101 | } |
102 | ||
1a07bfb5 NK |
103 | do { |
104 | ptstat = __raw_readl(psc_base + PTSTAT); | |
105 | } while (!(((ptstat >> domain) & 1) == 0)); | |
106 | ||
83f53220 | 107 | do { |
c5b736d0 | 108 | mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); |
fe277d9b | 109 | } while (!((mdstat & MDSTAT_STATE_MASK) == next_state)); |
e4c822c7 CC |
110 | |
111 | iounmap(psc_base); | |
7c6337e2 | 112 | } |